Charakteristische Produkte

Charakteristische Applikationen

Die N3290 MJPEG-Serie von Nuvoton ist ein bis 200 MHz getaktetes ARM926EJ-S und eine auf Hardware-JPEG-Codec basierende Produktgruppe, die auf kostengünstige ELA- (Bildungslernhilfe) , Video-Baby-Monitor-, Wi-Fi-Kamera- und HMI (Mensch-Maschine-Schnittstelle) Anwendungen abzielt. Die N3290-Serie ist ein 64-pol. und 128-pol. LQFP-Modul mit 2 MB, 8 MB oder 32 MB an DRAM als Stack. Sie kann auch als Universal-Mikrocontroller (MCU) verwendet werden.


 

Teilen

Geben Sie die E-Mail-Adresse, die Sie teilen wollen, ein.*
E-Mail*
Name*
Validierungscode*
Part No. Check Disty Raw NAND I/F, ECC bits NAND Flash, No. of ECC bits CPU Max Speed I Cache D Cache SRAM Stacked SDRAM (bit) SPI Flash I/F SD / SDIO 1.1 Host (12 Mbps) USB 2.0 Host (480 Mbps) Device (FS / HS) 2D GFX JPEG Codec Video Codec RGB Color (bits) Max. Resolution SAR ADC 24-bit Σ-Δ ADC ADC for MIC Input Touch Panel (Wire) Stereo DAC (bits) JTAG Ethernet 10/100 MAC CMOS Sensor1 GPIO (Max) UART I2C SPI RTC PWM TV Output I2S Core Voltage (V) I/O Voltage (V) Package Status I/O I2S/ AC97 ADC Operating Temp. Range (°C ) SDRAM NOR Flash SPI Flash, No. of I/O Pins ATAPI USB 2.0 HS Device 2D Graphics TFT LCD Speed (Samples per second) Touch Screen Controller LVD/LVR External Bus Interface KPI PS2 PCI Master
N32901R1DN Check Disty 15   926 200 MHz 8K 8K 8K 1Mx16 SDR Y 1(one hardware host controller) 1   HS   Y MJPEG Codec(Motion JPEG Codec, VGA 30fps)     Y   Y   16     Y(CCIR601 / CCIR656 I/F, 2M pixel) 34 2 Y 2(Only one hardware SPI controller to support two SPI device with two chip selection signals)   2   Y 1.8 3.3 LQFP-64 (MCP) Mass Production                                    
N32901U1DN Check Disty None 15   926 200 MHz 8K 8K 8K 1Mx16 SDR Y 3(one hardware host controller) 1   HS   Y MJPEG Codec(Motion JPEG Codec, VGA 30fps) 18 QVGA(320x240) Y   Y 4 16 Y   Y(CCIR601 / CCIR656 I/F, 2M pixel) 64 2 Y 2(Only one hardware SPI controller to support two SPI device with two chip selection signals) Y 4   Y 1.8 3.3 LQFP-128 (MCP) Mass Production                                    
N32901U2DN Check Disty None 15   926 200 MHz 8K 8K 8K 1Mx16 SDR Y 2(one hardware host controller) 1   HS   Y MJPEG Codec(Motion JPEG Codec, VGA 30fps) 18 QVGA(320x240) Y   Y 4 16 Y   Y(CCIR601 / CCIR656 I/F, 2M pixel) 59 2   2(Only one hardware SPI controller to support two SPI device with two chip selection signals) Y 4 Y   1.8 3.3 LQFP-128 (MCP) Mass Production                                    
N32903R1DN Check Disty 15   926 200 MHz 8K 8K 8K 4Mx16 DDR Y 1(one hardware host controller) 1   HS   Y MJPEG Codec(Motion JPEG Codec, VGA 30fps)     Y   Y   16     Y(CCIR601 / CCIR656 I/F, 2M pixel) 34 2 Y 2(Only one hardware SPI controller to support two SPI device with two chip selection signals)   2   Y 1.8 3.3 TQFP-64 (MCP) Mass Production                                    
N32903U1DN Check Disty 15   926 200 MHz 8K 8K 8K 4Mx16 DDR Y 3(one hardware host controller) 1   HS   Y MJPEG Codec(Motion JPEG Codec, VGA 30fps) 18 VGA(640x480) Y   Y 4 16 Y   Y(CCIR601 / CCIR656 I/F, 2M pixel) 64 2 Y 2(Only one hardware SPI controller to support two SPI device with two chip selection signals) Y 4   Y 1.8 3.3 LQFP-128 (MCP) Mass Production                                    
N32903U2DN Check Disty 15   926 200 MHz 8K 8K 8K 4Mx16 DDR Y 2(one hardware host controller) 1   HS   Y MJPEG Codec(Motion JPEG Codec, VGA 30fps) 18 VGA(640x480) Y   Y 4 16 Y   Y(CCIR601 / CCIR656 I/F, 2M pixel) 59 2   2(Only one hardware SPI controller to support two SPI device with two chip selection signals) Y 4 Y   1.8 3.3 LQFP-128 (MCP) Mass Production                                    
N32905U1DN Check Disty None 15   926 200 MHz 8K 8K 8K 16Mx16 DDR Y 3(one hardware host controller) 1   HS   Y MJPEG Codec(Motion JPEG Codec, VGA 30fps) 18 VGA(640x480) Y   Y 4 16 Y   Y(CCIR601 / CCIR656 I/F, 2M pixel) 64 2 Y 2(Only one hardware SPI controller to support two SPI device with two chip selection signals) Y 4   Y 1.8 3.3 LQFP-128 (MCP) Mass Production                                    
N32905U2DN Check Disty 15   926 200 MHz 8K 8K 8K 16Mx16 DDR Y 2(one hardware host controller) 1   HS   Y MJPEG Codec(Motion JPEG Codec, VGA 30fps) 18 VGA(640x480) Y   Y 4 16 Y   Y(CCIR601 / CCIR656 I/F, 2M pixel) 59 2   2(Only one hardware SPI controller to support two SPI device with two chip selection signals) Y 4 Y   1.8 3.3 LQFP-128 (MCP) Mass Production                                    

Rückmeldung des Benutzers

Bitte bewerten Sie unsere Website
eMail
Name*
Validierungscode*

微信扫一扫,关注新唐MCU。

Anmelden bei My Nuvoton

So bleiben Sie über Änderungen an Dokumenten, die Sie herunterladen, informiert.
Wollen Sie sich nicht anmelden, schließen Sie einfach diese Seite und gehen direkt zu den Downloads.