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0.6um CDMOS/UHV Process

0.6um CDMOS / UHV Process 

0.6um 5V/40V Dual-Vgs CDMOS Process

This process is a Dual GOX process with Vgs = 5V and Max. Vgs = 40V, Vds voltages 5V/18V/25V/40V, providing low on-resistance devices for Power Converter and LED needs, plus high resistance Poly2, PIP capacitors and Bipolar devices in order to implement analog designs. Other special devices are also available for specific needs including Depletion Devices, Native Devices, Zener Diodes etc. A Poly e-fuse IP is also provided for products requiring OTP. This process supports 3um Top Metal to enable copper wire bonding. For convenience of digital circuit design, a 5V Standard Cell Library is provided.

Device Vth(V) Idsat(uA / um) Rds,on(mohm-mm2) Bvdss(V)
5V / 18V LDNMOS 0.85 330 18 >25
5V / 25V LDNMOS 0.77 380 25 >30
5V / 40V LDNMOS 0.77 340 55 >48

 

0.6um 5V/40V/UHV Process

This unique process uses Nuvoton’s modular process technology that is based on 0.6um 5V/40V Dual-Vgs CDMOS processes. In addition to the devices found in the 0.6um 5V/40V Dual-Vgs CDMOS process, additional devices in this unique process include 700V Ultra High Voltage devices such as Depletion UHV, Low Ron UHV and UHV JFET to support applications ranging from general DC/DC to AC/DC power systems. It is a completely modularized and customized manufacturing process, so any of the devices can be selected to meet specific application needs. This process platform allows customers to serve a wide range of market needs with a single customizable process.

 

0.6um 5V/20V CDMOS Process

For the 20V processes as shown below, Nuvoton offers another option of the 0.6um 5V/20V CDMOS process. This is a Dual GOX process with Vgs = 5V and Max. Vgs = 16V, Vds voltages = 5V/ 12V/16V/20V, providing low on-resistance for Power Converter and LED needs, and with high resistance Poly2, PIP capacitors and Bipolar for analog designs. Other special devices are added to serve specific needs such as Depletion Devices with Zener Diodes. Nuvoton’s Poly e-fuse IP is also available to meet OTP requirements. This process also supports 3um Top Metal for copper wire bonding. For convenience of the digital circuit design, a 5V Standard Cell Library is provided.

Device Vth(V) Idsat(uA / um) Rds,on(mohm-mm2) Bvdss(V)
12V / 12V LDNMOS 1.9 550 7.8 >18
16V / 16V LDNMOS 1.9 760 12 >20
5V / 20V LDNMOS 1.1 365 25 >24

 

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