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0.35um 3.3v 5v process

0.35um 3.3V/5V embedded Logic NVM Process 

0.35um 3.3V/5V embedded Logic NVM Process 

This process is a Dual GOX process with 3.3V and 5V devices for logic products, and high resistance Poly2, PIP capacitors and Bipolar for analog designs. This process combines YMC 3.3V MTP NVM IP to minimize mask costs. YMC NVM IP consists of three forms of memory type- (1) EEPROM (2) Flash (3) MTP, and provides IP for memory density from 256x8 bits to 16Kx16 bits. This process has been widely used in Microcontroller(MCU) products. For convenience of digital circuit design, a 3.3V and 5V Standard Cell Library and 3.3V SRAM compiler service are also provided.

Design Kits

Design Kits Vender Tools / Version
SPICE - HSIPCE BSIM3V3 (L49)
Spectre SPICE
DRC Mentor Graphics Calibre
LVS Mentor Graphics Calibre
LPE Mentor Graphics Calibre
Cell Library -

0.35um 3.3V Standard Cell / IO Cell Library

NVM IP

YMC

(MTP, Flash, EEPROM)

Density 256 X 8 bits ~ 16K X 16 bits

Byte Write / Byte Read

Extra Low Read Voltage ~1.2V

Endurance >100K

SRAM -

0.35um 3.3V SRAM compiler

(64 x 2bits ~ 4K x 8 bits)

Mismatch Report - 0.35um 3.3V mismatch report

 

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