CM2053 Series
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Flash Memory/
SRAM (Kbytes)
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|---|---|
| 128 / 16 | |
| Packages | LQFP48 (7 x 7 mm) Pitch 0.5 mm |
The NuMicro® CM2053 series is 32-bit microcontroller based on Arm® Cortex®-M23 core using Armv8-M architecture. The CM2053 runs up to 48 MHz and features up to 128 Kbytes Flash Memory, 16 Kbytes SRAM, 1.75V ~ 5.5V wide operating voltage, and -40°C to +105°C operating temperature. It includes a crystal-less USB 2.0 full speed device and one set of CAN FD interface for industrial automation and automotive related applications.
The USB interface supports up to 17 configurable endpoints, equivalent to 5 VCOMs for configurable Isochronous, Bulk, Interrupt and Control transfer types, and maximum 1 Kbytes buffer size.
The CM2053 series integrates a rich suite of peripherals, including Timers, Watchdog Timers, PDMA, up to 5 sets of UART, 2 sets of I2C, 1 set of SPI / I2S and Universal Serial Control Interface (USCI). Notably, all 5 sets of UART support flow control and PDMA mode, with 4 of them further equipped with 16-byte FIFOs for both data reception and transmission. It also includes high performance analog front-end circuit, such as 12 channels of 12-bit 730 ksps ADC, 6 channels of 16-bit PWM, and a temperature sensor to reduce form factor simultaneously.
There is one type of package provided: LQFP48 (7 mm x 7 mm). It is pin-compatible with the M251 / M252, M031, and M480 series, facilitating easy system design and component replacement during functional enhancement.
For the development platform, Nuvoton provides the NuMaker® CM2053 evaluation boards and Nu-Link, Nu-Link-2-Pro debugger, and the 3rd Party IDEs such as Keil MDK, IAR EWARM and Eclipse IDE with GNU GCC compilers are also supported.
Target Application:
- USB Bridge for serial ports
- Data Collector
- Battery Management System
- Automotive Related Module
Key Features:
| • | Operating Characteristics | |||||
| - | Voltage range: 1.75V ~ 5.5V | |||||
| - | Temperature range: -40°C ~ +105°C | |||||
| - | EFT 4.4 kV | |||||
| - | ESD HBM 7 kV | |||||
| • | Core | |||||
| - | Arm® Cortex®-M23 core using Armv8-M architecture, running up to 48 MHz, without TrustZone® | |||||
| - | 32-bit hardware multiplier/divider | |||||
| • | Memories | |||||
| - | Up to 128 KB Flash | |||||
| - | 16 KB SRAM | |||||
| - | 4 KB LDROM | |||||
| - | ISP / ICP / IAP programming | |||||
| • | Clocks | |||||
| - | 4 ~ 32 MHz external high speed crystal oscillator (HXT) for precise timing operation | |||||
| - | 32.768 kHz external low speed crystal oscillator (LXT) for RTC function and low-power system operation | |||||
| - | 48 MHz internal high speed RC oscillator (HIRC) for system operation (Factory pre-trimmed to ±0.25% and frequency deviation ±2.5% over entire temperature from -40°C ~ +105°C) | |||||
| - | 4.032 MHz internal high speed RC oscillator (MIRC) for system operation | |||||
| - | 38.4 kHz internal low speed RC oscillator (LIRC) for Watchdog Timer and wake-up operation. | |||||
| • | Power management | |||||
| - | Integrated with Power-on Reset, Brown-out Reset and Low Voltage Reset | |||||
| - | Built-in LDO | |||||
| • | Low Power Consumption | |||||
| - | 130 μA/MHz in operating mode | |||||
| - | 35 μA/MHz in idle mode | |||||
| - | 1.7 μA in Power-down mode (RTC off, RAM retention) | |||||
| • | Timers | |||||
| - | Up to 4 32-bit timers | |||||
| - | One 24-bit SysTick timer | |||||
| - | One independent watchdog | |||||
| - | One window watchdog | |||||
| - | RTC with Calendar and Alarm | |||||
| • | PDMA | |||||
| - | 5 channels | |||||
| - | Channel can be operated by – software trigger, SPI / I2S, UART, I2C, USCI, EADC, PWM capture event and Timer | |||||
| • | Analog | |||||
| - | Up to 12 channels of 12-bit 730 ksps ADC | |||||
| • | Communication interfaces | |||||
| - | 5 sets of UART interfaces | |||||
| - | 2 sets of I²C interfaces | |||||
| - | 1 set of SPI / I2S | |||||
| - | 1 set of USCI (configured as UART, SPI or I²C) | |||||
| • | CAN FD | |||||
| - | 1 set of CAN FD controller with up to 64 data bytes per message | |||||
| - | Compliant with CAN protocol version 2.0 part A, B and ISO 11898-1: 2015 | |||||
| - | Programmable receive and transmit FIFO. | |||||
| - | Accessible 1-Kbyte RAM memory to allocate up to 256 words | |||||
| • | USB | |||||
| - | Supports 17 endpoints for configurable Control / Bulk / Interrupt / Isochronous transfer types and maximum 1024 bytes’ buffer size | |||||
| - | Compliant with USB 2.0 Full-Speed specification | |||||
| - | Provides 1 interrupt vector with 4 different interrupt events (NEVWK, VBUSDET, USB and BUS) | |||||
| • | 96-bit Unique ID (UID) | |||||
| • | 128-bit Unique Customer ID (UCID) | |||||
| • | Packages | |||||
| - | LQFP48 (7 mm x 7 mm) | |||||
| • | Evaluation Board | |||||
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