Q: Why can’t the clock source of HCLK be switched to PLL when the system clock source is initialized with the following commands?
CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLKSEL_Msk);
CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_PLL;

A: In the execution of the first command line,
CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLKSEL_Msk);

HCLKSEL (CLKSEL0 [2: 0]) is set to 0x00. When HCLKSEL is set to 0x00, as shown below, the clock source of HCLK is switched to external crystal.

If the external crystal is not stable or enabled at this time, the switching clock source will fail and the HCLKSEL will be remain its default setting (initialized as 0x07, clock source as HIRC).

Therefore, in the execution of the second command line,

CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_PLL;

HCLKSEL cannot be correctly set to PLL and HCLK cannot be switched to PLL.

To switch the clock source, user needs to make sure that the clock source to be switched is stable. It is recommended to switch the clock source using the following methods:

1. Write a value directly

CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLKSEL_Msk) | CLK_CLKSEL0_HCLKSEL_PLL;

2. Call function

CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV_HCLK(2));

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Applications:
Function:	Peripherals,ARM,Cortex-M0,Cortex-M4,Clock Control,HIRC,HXT,PLL

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FAQ

Why can’t the clock source of HCLK be switched to PLL when the system clock source is initialized with the following commands? CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLKSEL_Msk); CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_PLL; Issue Date：2016-11-29

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