M471M/R1/S BSP V3.01.000
The Board Support Package for M4521
spi.c
Go to the documentation of this file.
1/**************************************************************************/
8#include "NuMicro.h"
41uint32_t SPI_Open(SPI_T *spi,
42 uint32_t u32MasterSlave,
43 uint32_t u32SPIMode,
44 uint32_t u32DataWidth,
45 uint32_t u32BusClock)
46{
47 uint32_t u32ClkSrc = 0, u32Div, u32HCLKFreq;
48
49 if(spi == SPI1)
50 /* Disable I2S mode */
51 spi->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk;
52
53 if(u32DataWidth == 32)
54 u32DataWidth = 0;
55
56 /* Get system clock frequency */
57 u32HCLKFreq = CLK_GetHCLKFreq();
58
59 if(u32MasterSlave == SPI_MASTER)
60 {
61 /* Default setting: slave selection signal is active low; disable automatic slave selection function. */
63
64 /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
65 spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk;
66
67 if(u32BusClock >= u32HCLKFreq)
68 {
69 /* Select PCLK as the clock source of SPI */
70 if(spi == SPI0)
71 CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK0;
72 else
73 CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK1;
74 }
75
76 /* Check clock source of SPI */
77 if(spi == SPI0)
78 {
80 u32ClkSrc = __HXT; /* Clock source is HXT */
82 u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
84 {
85 /* Clock source is PCLK0 */
87 u32ClkSrc = (u32HCLKFreq / 2);
88 else
89 u32ClkSrc = u32HCLKFreq;
90 }
91 else
92 u32ClkSrc = __HIRC; /* Clock source is HIRC */
93 }
94 else
95 {
97 u32ClkSrc = __HXT; /* Clock source is HXT */
99 u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
101 {
102 /* Clock source is PCLK1 */
104 u32ClkSrc = (u32HCLKFreq / 2);
105 else
106 u32ClkSrc = u32HCLKFreq;
107 }
108 else
109 u32ClkSrc = __HIRC; /* Clock source is HIRC */
110 }
111
112 if(u32BusClock >= u32HCLKFreq)
113 {
114 /* Set DIVIDER = 0 */
115 spi->CLKDIV = 0;
116 /* Return master peripheral clock rate */
117 return u32ClkSrc;
118 }
119 else if(u32BusClock >= u32ClkSrc)
120 {
121 /* Set DIVIDER = 0 */
122 spi->CLKDIV = 0;
123 /* Return master peripheral clock rate */
124 return u32ClkSrc;
125 }
126 else if(u32BusClock == 0)
127 {
128 /* Set DIVIDER to the maximum value 0xFF. f_spi = f_spi_clk_src / (DIVIDER + 1) */
130 /* Return master peripheral clock rate */
131 return (u32ClkSrc / (0xFF + 1));
132 }
133 else
134 {
135 u32Div = (((u32ClkSrc * 10) / u32BusClock + 5) / 10) - 1; /* Round to the nearest integer */
136 if(u32Div > 0xFF)
137 {
138 u32Div = 0xFF;
140 /* Return master peripheral clock rate */
141 return (u32ClkSrc / (0xFF + 1));
142 }
143 else
144 {
145 spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos);
146 /* Return master peripheral clock rate */
147 return (u32ClkSrc / (u32Div + 1));
148 }
149 }
150 }
151 else /* For slave mode, force the SPI peripheral clock rate to equal APB clock rate. */
152 {
153 /* Default setting: slave selection signal is low level active. */
155
156 /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */
157 spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk;
158
159 /* Set DIVIDER = 0 */
160 spi->CLKDIV = 0;
161
162 /* Select PCLK as the clock source of SPI */
163 if(spi == SPI0)
164 {
165 CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK0;
166 /* Return slave peripheral clock rate */
168 return (u32HCLKFreq / 2);
169 else
170 return u32HCLKFreq;
171 }
172 else
173 {
174 CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK1;
175 /* Return slave peripheral clock rate */
177 return (u32HCLKFreq / 2);
178 else
179 return u32HCLKFreq;
180 }
181 }
182}
183
190void SPI_Close(SPI_T *spi)
191{
192 if(spi == SPI0)
193 {
194 /* Reset SPI */
195 SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk;
196 SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk;
197 }
198 else
199 {
200 /* Reset SPI */
201 SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk;
202 SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk;
203 }
204}
205
213{
215}
216
225{
227}
228
236{
238}
239
249void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
250{
251 spi->SSCTL = (spi->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | SPI_SSCTL_AUTOSS_Msk);
252}
253
266uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
267{
268 uint32_t u32ClkSrc, u32HCLKFreq;
269 uint32_t u32Div;
270
271 /* Get system clock frequency */
272 u32HCLKFreq = CLK_GetHCLKFreq();
273
274 if(u32BusClock >= u32HCLKFreq)
275 {
276 /* Select PCLK as the clock source of SPI */
277 if(spi == SPI0)
278 CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK0;
279 else
280 CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK1;
281 }
282
283 /* Check clock source of SPI */
284 if(spi == SPI0)
285 {
287 u32ClkSrc = __HXT; /* Clock source is HXT */
289 u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
291 {
292 /* Clock source is PCLK0 */
294 u32ClkSrc = (u32HCLKFreq / 2);
295 else
296 u32ClkSrc = u32HCLKFreq;
297 }
298 else
299 u32ClkSrc = __HIRC; /* Clock source is HIRC */
300 }
301 else
302 {
304 u32ClkSrc = __HXT; /* Clock source is HXT */
306 u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
308 {
309 /* Clock source is PCLK1 */
311 u32ClkSrc = (u32HCLKFreq / 2);
312 else
313 u32ClkSrc = u32HCLKFreq;
314 }
315 else
316 u32ClkSrc = __HIRC; /* Clock source is HIRC */
317 }
318
319 if(u32BusClock >= u32HCLKFreq)
320 {
321 /* Set DIVIDER = 0 */
322 spi->CLKDIV = 0;
323 /* Return master peripheral clock rate */
324 return u32ClkSrc;
325 }
326 else if(u32BusClock >= u32ClkSrc)
327 {
328 /* Set DIVIDER = 0 */
329 spi->CLKDIV = 0;
330 /* Return master peripheral clock rate */
331 return u32ClkSrc;
332 }
333 else if(u32BusClock == 0)
334 {
335 /* Set DIVIDER to the maximum value 0xFF. f_spi = f_spi_clk_src / (DIVIDER + 1) */
337 /* Return master peripheral clock rate */
338 return (u32ClkSrc / (0xFF + 1));
339 }
340 else
341 {
342 u32Div = (((u32ClkSrc * 10) / u32BusClock + 5) / 10) - 1; /* Round to the nearest integer */
343 if(u32Div > 0xFF)
344 {
345 u32Div = 0xFF;
347 /* Return master peripheral clock rate */
348 return (u32ClkSrc / (0xFF + 1));
349 }
350 else
351 {
352 spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos);
353 /* Return master peripheral clock rate */
354 return (u32ClkSrc / (u32Div + 1));
355 }
356 }
357}
358
367void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
368{
370 (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) |
371 (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos));
372}
373
380uint32_t SPI_GetBusClock(SPI_T *spi)
381{
382 uint32_t u32Div;
383 uint32_t u32ClkSrc, u32HCLKFreq;
384
385 /* Get DIVIDER setting */
387
388 /* Get system clock frequency */
389 u32HCLKFreq = CLK_GetHCLKFreq();
390
391 /* Check clock source of SPI */
392 if(spi == SPI0)
393 {
395 u32ClkSrc = __HXT; /* Clock source is HXT */
397 u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
399 {
400 /* Clock source is PCLK0 */
402 u32ClkSrc = (u32HCLKFreq / 2);
403 else
404 u32ClkSrc = u32HCLKFreq;
405 }
406 else
407 u32ClkSrc = __HIRC; /* Clock source is HIRC */
408 }
409 else
410 {
412 u32ClkSrc = __HXT; /* Clock source is HXT */
414 u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
416 {
417 /* Clock source is PCLK1 */
419 u32ClkSrc = (u32HCLKFreq / 2);
420 else
421 u32ClkSrc = u32HCLKFreq;
422 }
423 else
424 u32ClkSrc = __HIRC; /* Clock source is HIRC */
425 }
426
427 /* Return SPI bus clock rate */
428 return (u32ClkSrc / (u32Div + 1));
429}
430
452void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
453{
454 /* Enable unit transfer interrupt flag */
455 if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK)
456 spi->CTL |= SPI_CTL_UNITIEN_Msk;
457
458 /* Enable slave selection signal active interrupt flag */
459 if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK)
461
462 /* Enable slave selection signal inactive interrupt flag */
465
466 /* Enable slave TX under run interrupt flag */
467 if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK)
469
470 /* Enable slave bit count error interrupt flag */
471 if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK)
473
474 /* Enable slave time-out interrupt flag */
475 if((u32Mask & SPI_SLVTO_INT_MASK) == SPI_SLVTO_INT_MASK)
477
478 /* Enable slave TX underflow interrupt flag */
479 if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK)
481
482 /* Enable TX threshold interrupt flag */
485
486 /* Enable RX threshold interrupt flag */
489
490 /* Enable RX overrun interrupt flag */
493
494 /* Enable RX time-out interrupt flag */
497}
498
520void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
521{
522 /* Disable unit transfer interrupt flag */
523 if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK)
524 spi->CTL &= ~SPI_CTL_UNITIEN_Msk;
525
526 /* Disable slave selection signal active interrupt flag */
527 if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK)
528 spi->SSCTL &= ~SPI_SSCTL_SSACTIEN_Msk;
529
530 /* Disable slave selection signal inactive interrupt flag */
532 spi->SSCTL &= ~SPI_SSCTL_SSINAIEN_Msk;
533
534 /* Disable slave TX under run interrupt flag */
535 if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK)
536 spi->SSCTL &= ~SPI_SSCTL_SLVURIEN_Msk;
537
538 /* Disable slave bit count error interrupt flag */
539 if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK)
540 spi->SSCTL &= ~SPI_SSCTL_SLVBEIEN_Msk;
541
542 /* Disable slave time-out interrupt flag */
543 if((u32Mask & SPI_SLVTO_INT_MASK) == SPI_SLVTO_INT_MASK)
544 spi->SSCTL &= ~SPI_SSCTL_SLVTOIEN_Msk;
545
546 /* Disable slave TX underflow interrupt flag */
547 if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK)
548 spi->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk;
549
550 /* Disable TX threshold interrupt flag */
552 spi->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;
553
554 /* Disable RX threshold interrupt flag */
556 spi->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;
557
558 /* Disable RX overrun interrupt flag */
560 spi->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;
561
562 /* Disable RX time-out interrupt flag */
564 spi->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;
565}
566
588uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask)
589{
590 uint32_t u32IntFlag = 0;
591
592 /* Check unit transfer interrupt flag */
593 if((u32Mask & SPI_UNIT_INT_MASK) && (spi->STATUS & SPI_STATUS_UNITIF_Msk))
594 u32IntFlag |= SPI_UNIT_INT_MASK;
595
596 /* Check slave selection signal active interrupt flag */
597 if((u32Mask & SPI_SSACT_INT_MASK) && (spi->STATUS & SPI_STATUS_SSACTIF_Msk))
598 u32IntFlag |= SPI_SSACT_INT_MASK;
599
600 /* Check slave selection signal inactive interrupt flag */
601 if((u32Mask & SPI_SSINACT_INT_MASK) && (spi->STATUS & SPI_STATUS_SSINAIF_Msk))
602 u32IntFlag |= SPI_SSINACT_INT_MASK;
603
604 /* Check slave TX under run interrupt flag */
605 if((u32Mask & SPI_SLVUR_INT_MASK) && (spi->STATUS & SPI_STATUS_SLVURIF_Msk))
606 u32IntFlag |= SPI_SLVUR_INT_MASK;
607
608 /* Check slave bit count error interrupt flag */
609 if((u32Mask & SPI_SLVBE_INT_MASK) && (spi->STATUS & SPI_STATUS_SLVBEIF_Msk))
610 u32IntFlag |= SPI_SLVBE_INT_MASK;
611
612 /* Check slave time-out interrupt flag */
613 if((u32Mask & SPI_SLVTO_INT_MASK) && (spi->STATUS & SPI_STATUS_SLVTOIF_Msk))
614 u32IntFlag |= SPI_SLVTO_INT_MASK;
615
616 /* Check slave TX underflow interrupt flag */
617 if((u32Mask & SPI_TXUF_INT_MASK) && (spi->STATUS & SPI_STATUS_TXUFIF_Msk))
618 u32IntFlag |= SPI_TXUF_INT_MASK;
619
620 /* Check TX threshold interrupt flag */
621 if((u32Mask & SPI_FIFO_TXTH_INT_MASK) && (spi->STATUS & SPI_STATUS_TXTHIF_Msk))
622 u32IntFlag |= SPI_FIFO_TXTH_INT_MASK;
623
624 /* Check RX threshold interrupt flag */
625 if((u32Mask & SPI_FIFO_RXTH_INT_MASK) && (spi->STATUS & SPI_STATUS_RXTHIF_Msk))
626 u32IntFlag |= SPI_FIFO_RXTH_INT_MASK;
627
628 /* Check RX overrun interrupt flag */
629 if((u32Mask & SPI_FIFO_RXOV_INT_MASK) && (spi->STATUS & SPI_STATUS_RXOVIF_Msk))
630 u32IntFlag |= SPI_FIFO_RXOV_INT_MASK;
631
632 /* Check RX time-out interrupt flag */
633 if((u32Mask & SPI_FIFO_RXTO_INT_MASK) && (spi->STATUS & SPI_STATUS_RXTOIF_Msk))
634 u32IntFlag |= SPI_FIFO_RXTO_INT_MASK;
635
636 return u32IntFlag;
637}
638
658void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask)
659{
660 if(u32Mask & SPI_UNIT_INT_MASK)
661 spi->STATUS = SPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */
662
663 if(u32Mask & SPI_SSACT_INT_MASK)
664 spi->STATUS = SPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */
665
666 if(u32Mask & SPI_SSINACT_INT_MASK)
667 spi->STATUS = SPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */
668
669 if(u32Mask & SPI_SLVUR_INT_MASK)
670 spi->STATUS = SPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */
671
672 if(u32Mask & SPI_SLVBE_INT_MASK)
673 spi->STATUS = SPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */
674
675 if(u32Mask & SPI_SLVTO_INT_MASK)
676 spi->STATUS = SPI_STATUS_SLVTOIF_Msk; /* Clear slave time-out interrupt flag */
677
678 if(u32Mask & SPI_TXUF_INT_MASK)
679 spi->STATUS = SPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */
680
681 if(u32Mask & SPI_FIFO_RXOV_INT_MASK)
682 spi->STATUS = SPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */
683
684 if(u32Mask & SPI_FIFO_RXTO_INT_MASK)
685 spi->STATUS = SPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */
686}
687
706uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask)
707{
708 uint32_t u32Flag = 0;
709
710 /* Check busy status */
711 if((u32Mask & SPI_BUSY_MASK) && (spi->STATUS & SPI_STATUS_BUSY_Msk))
712 u32Flag |= SPI_BUSY_MASK;
713
714 /* Check RX empty flag */
715 if((u32Mask & SPI_RX_EMPTY_MASK) && (spi->STATUS & SPI_STATUS_RXEMPTY_Msk))
716 u32Flag |= SPI_RX_EMPTY_MASK;
717
718 /* Check RX full flag */
719 if((u32Mask & SPI_RX_FULL_MASK) && (spi->STATUS & SPI_STATUS_RXFULL_Msk))
720 u32Flag |= SPI_RX_FULL_MASK;
721
722 /* Check TX empty flag */
723 if((u32Mask & SPI_TX_EMPTY_MASK) && (spi->STATUS & SPI_STATUS_TXEMPTY_Msk))
724 u32Flag |= SPI_TX_EMPTY_MASK;
725
726 /* Check TX full flag */
727 if((u32Mask & SPI_TX_FULL_MASK) && (spi->STATUS & SPI_STATUS_TXFULL_Msk))
728 u32Flag |= SPI_TX_FULL_MASK;
729
730 /* Check TX/RX reset flag */
731 if((u32Mask & SPI_TXRX_RESET_MASK) && (spi->STATUS & SPI_STATUS_TXRXRST_Msk))
732 u32Flag |= SPI_TXRX_RESET_MASK;
733
734 /* Check SPIEN flag */
735 if((u32Mask & SPI_SPIEN_STS_MASK) && (spi->STATUS & SPI_STATUS_SPIENSTS_Msk))
736 u32Flag |= SPI_SPIEN_STS_MASK;
737
738 /* Check SPIn_SS line status */
739 if((u32Mask & SPI_SSLINE_STS_MASK) && (spi->STATUS & SPI_STATUS_SSLINE_Msk))
740 u32Flag |= SPI_SSLINE_STS_MASK;
741
742 return u32Flag;
743}
744
745
746 /* end of group SPI_EXPORTED_FUNCTIONS */
748 /* end of group SPI_Driver */
750 /* end of group Standard_Driver */
752
#define SPI_STATUS_TXFULL_Msk
Definition: M471M_R1_S.h:9498
#define SPI_SSCTL_SSACTPOL_Msk
Definition: M471M_R1_S.h:9378
#define SPI_FIFOCTL_RXOVIEN_Msk
Definition: M471M_R1_S.h:9432
#define SPI_STATUS_SSACTIF_Msk
Definition: M471M_R1_S.h:9459
#define SPI_SSCTL_SS_Msk
Definition: M471M_R1_S.h:9375
#define SPI_CTL_UNITIEN_Msk
Definition: M471M_R1_S.h:9354
#define SPI_FIFOCTL_RXTH_Pos
Definition: M471M_R1_S.h:9446
#define SPI_FIFOCTL_TXTH_Msk
Definition: M471M_R1_S.h:9450
#define SPI_CTL_DWIDTH_Pos
Definition: M471M_R1_S.h:9344
#define SPI_STATUS_TXRXRST_Msk
Definition: M471M_R1_S.h:9507
#define SPI_STATUS_TXTHIF_Msk
Definition: M471M_R1_S.h:9501
#define SPI_STATUS_RXTHIF_Msk
Definition: M471M_R1_S.h:9483
#define SPI_SSCTL_SLVTOIEN_Msk
Definition: M471M_R1_S.h:9387
#define SPI_STATUS_UNITIF_Msk
Definition: M471M_R1_S.h:9456
#define SPI_SSCTL_SSACTIEN_Msk
Definition: M471M_R1_S.h:9399
#define SPI_CLKDIV_DIVIDER_Pos
Definition: M471M_R1_S.h:9371
#define SYS_IPRST1_SPI1RST_Msk
Definition: M471M_R1_S.h:10423
#define SPI_STATUS_SSINAIF_Msk
Definition: M471M_R1_S.h:9462
#define SYS_IPRST1_SPI0RST_Msk
Definition: M471M_R1_S.h:10420
#define SPI_FIFOCTL_TXUFIEN_Msk
Definition: M471M_R1_S.h:9438
#define SPI_STATUS_SLVTOIF_Msk
Definition: M471M_R1_S.h:9468
#define SPI_CLKDIV_DIVIDER_Msk
Definition: M471M_R1_S.h:9372
#define SPI_FIFOCTL_TXTH_Pos
Definition: M471M_R1_S.h:9449
#define SPI_CTL_SPIEN_Msk
Definition: M471M_R1_S.h:9330
#define SPI_SSCTL_SLVBEIEN_Msk
Definition: M471M_R1_S.h:9393
#define SPI_STATUS_TXEMPTY_Msk
Definition: M471M_R1_S.h:9495
#define SPI_SSCTL_SSINAIEN_Msk
Definition: M471M_R1_S.h:9402
#define SPI_STATUS_RXOVIF_Msk
Definition: M471M_R1_S.h:9486
#define SPI_FIFOCTL_RXTOIEN_Msk
Definition: M471M_R1_S.h:9429
#define SPI_FIFOCTL_RXTHIEN_Msk
Definition: M471M_R1_S.h:9423
#define SPI_STATUS_RXFULL_Msk
Definition: M471M_R1_S.h:9480
#define SPI_FIFOCTL_RXTH_Msk
Definition: M471M_R1_S.h:9447
#define SPI_STATUS_SLVBEIF_Msk
Definition: M471M_R1_S.h:9471
#define SPI_STATUS_RXTOIF_Msk
Definition: M471M_R1_S.h:9489
#define SPI_STATUS_RXEMPTY_Msk
Definition: M471M_R1_S.h:9477
#define SPI_STATUS_SSLINE_Msk
Definition: M471M_R1_S.h:9465
#define SPI_SSCTL_SLVURIEN_Msk
Definition: M471M_R1_S.h:9396
#define SPI_STATUS_TXUFIF_Msk
Definition: M471M_R1_S.h:9504
#define SPI_STATUS_SLVURIF_Msk
Definition: M471M_R1_S.h:9474
#define SPI_FIFOCTL_TXFBCLR_Msk
Definition: M471M_R1_S.h:9444
#define SPI_FIFOCTL_TXTHIEN_Msk
Definition: M471M_R1_S.h:9426
#define SPI_STATUS_SPIENSTS_Msk
Definition: M471M_R1_S.h:9492
#define SPI_FIFOCTL_RXFBCLR_Msk
Definition: M471M_R1_S.h:9441
#define SPI_SSCTL_AUTOSS_Msk
Definition: M471M_R1_S.h:9381
#define SPI_STATUS_BUSY_Msk
Definition: M471M_R1_S.h:9453
NuMicro peripheral access layer header file.
#define CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2
Definition: clk.h:55
#define CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2
Definition: clk.h:58
#define CLK_CLKSEL2_SPI0SEL_HXT
Definition: clk.h:119
#define CLK_CLKSEL2_SPI0SEL_PLL
Definition: clk.h:120
#define CLK_CLKSEL2_SPI1SEL_PCLK1
Definition: clk.h:126
#define CLK_CLKSEL2_SPI1SEL_PLL
Definition: clk.h:125
#define CLK_CLKSEL2_SPI0SEL_PCLK0
Definition: clk.h:121
#define CLK_CLKSEL2_SPI1SEL_HXT
Definition: clk.h:124
uint32_t CLK_GetHCLKFreq(void)
Get HCLK frequency.
Definition: clk.c:169
__STATIC_INLINE uint32_t CLK_GetPLLClockFreq(void)
Get PLL clock frequency.
Definition: clk.h:326
#define CLK_CLKSEL2_SPI1SEL_Msk
Definition: M471M_R1_S.h:1610
#define CLK_CLKSEL0_PCLK1SEL_Msk
Definition: M471M_R1_S.h:1571
#define CLK_CLKSEL2_SPI0SEL_Msk
Definition: M471M_R1_S.h:1607
#define CLK_CLKSEL0_PCLK0SEL_Msk
Definition: M471M_R1_S.h:1568
__IO uint32_t I2SCTL
Definition: M471M_R1_S.h:9316
__IO uint32_t FIFOCTL
Definition: M471M_R1_S.h:9309
__IO uint32_t STATUS
Definition: M471M_R1_S.h:9310
__IO uint32_t CTL
Definition: M471M_R1_S.h:9305
#define CLK
Definition: M471M_R1_S.h:13818
__IO uint32_t SSCTL
Definition: M471M_R1_S.h:9307
__IO uint32_t CLKDIV
Definition: M471M_R1_S.h:9306
#define SPI1
Definition: M471M_R1_S.h:13845
#define SYS
Definition: M471M_R1_S.h:13816
#define SPI0
Definition: M471M_R1_S.h:13844
#define SPI_FIFO_RXTO_INT_MASK
Definition: spi.h:57
#define SPI_RX_EMPTY_MASK
Definition: spi.h:61
#define SPI_FIFO_RXTH_INT_MASK
Definition: spi.h:55
#define SPI_SLVBE_INT_MASK
Definition: spi.h:51
#define SPI_SSACT_INT_MASK
Definition: spi.h:48
#define SPI_SSLINE_STS_MASK
Definition: spi.h:67
#define SPI_SSINACT_INT_MASK
Definition: spi.h:49
#define SPI_SS_ACTIVE_LOW
Definition: spi.h:44
#define SPI_UNIT_INT_MASK
Definition: spi.h:47
#define SPI_FIFO_TXTH_INT_MASK
Definition: spi.h:54
#define SPI_SLVTO_INT_MASK
Definition: spi.h:52
#define SPI_TX_EMPTY_MASK
Definition: spi.h:63
#define SPI_TXRX_RESET_MASK
Definition: spi.h:65
#define SPI_TXUF_INT_MASK
Definition: spi.h:53
#define SPI_FIFO_RXOV_INT_MASK
Definition: spi.h:56
#define SPI_SLVUR_INT_MASK
Definition: spi.h:50
#define SPI_SPIEN_STS_MASK
Definition: spi.h:66
#define SPI_BUSY_MASK
Definition: spi.h:60
#define SPI_MASTER
Definition: spi.h:40
#define SPI_TX_FULL_MASK
Definition: spi.h:64
#define SPI_RX_FULL_MASK
Definition: spi.h:62
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
Disable interrupt function.
Definition: spi.c:520
uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask)
Get interrupt flag.
Definition: spi.c:588
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
Enable interrupt function.
Definition: spi.c:452
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
Enable the automatic slave selection function.
Definition: spi.c:249
void SPI_DisableAutoSS(SPI_T *spi)
Disable the automatic slave selection function.
Definition: spi.c:235
void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask)
Clear interrupt flag.
Definition: spi.c:658
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
Set the SPI bus clock.
Definition: spi.c:266
void SPI_Close(SPI_T *spi)
Disable SPI controller.
Definition: spi.c:190
void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
Configure FIFO threshold setting.
Definition: spi.c:367
uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask)
Get SPI status.
Definition: spi.c:706
void SPI_ClearTxFIFO(SPI_T *spi)
Clear TX FIFO buffer.
Definition: spi.c:224
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
This function make SPI module be ready to transfer.
Definition: spi.c:41
uint32_t SPI_GetBusClock(SPI_T *spi)
Get the actual frequency of SPI bus clock. Only available in Master mode.
Definition: spi.c:380
void SPI_ClearRxFIFO(SPI_T *spi)
Clear RX FIFO buffer.
Definition: spi.c:212
#define __HIRC
#define __HXT