M471M/R1/S BSP V3.01.000
The Board Support Package for M4521
ohci.h
Go to the documentation of this file.
1/**************************************************************************/
9#ifndef _USBH_OHCI_H_
10#define _USBH_OHCI_H_
11
13
14struct utr_t;
15struct udev_t;
16
17/* OHCI CONTROL AND STATUS REGISTER MASKS */
18
19/*
20 * Host controller functional state.
21 * for HCFS(HcControl[7:6])
22 */
23#define HCFS_RESET (0UL << USBH_HcControl_HCFS_Pos)
24#define HCFS_RESUME (1UL << USBH_HcControl_HCFS_Pos)
25#define HCFS_OPER (2UL << USBH_HcControl_HCFS_Pos)
26#define HCFS_SUSPEND (3UL << USBH_HcControl_HCFS_Pos)
27
28
29/*----------------------------------------------------------------------------------------*/
30/* Endpoint descriptor */
31/*----------------------------------------------------------------------------------------*/
32typedef struct ed_t {
33 /* OHCI spec. Endpoint descriptor */
34 uint32_t Info;
35 uint32_t TailP;
36 uint32_t HeadP;
37 uint32_t NextED;
38 /* The following members are used by USB Host libary. */
39 uint8_t bInterval;
40 uint16_t next_sf; /* for isochronous transfer, recording the next SF */
41 struct ed_t * next; /* point to the next ED in remove list */
42} ED_T;
43
44#define ED_CTRL_FA_Pos 0 /* Info[6:0] - Function address */
45#define ED_CTRL_EN_Pos 7 /* Info[10:7] - Endpoint number */
46#define ED_CTRL_DIR_Pos 11 /* Info[12:11] - Direction */
47#define ED_CTRL_MPS_Pos 16 /* Info[26:16] - Maximum packet size */
48
49#define ED_FUNC_ADDR_Msk (0x7f)
50#define ED_EP_ADDR_Msk (0xf<<7)
51#define ED_DIR_Msk (0x3<<11)
52#define ED_SPEED_Msk (1<<13)
53#define ED_MAX_PK_SIZE_Msk (0x7ff<<16)
54
55#define ED_DIR_BY_TD (0<<ED_CTRL_DIR_Pos)
56#define ED_DIR_OUT (1<<ED_CTRL_DIR_Pos)
57#define ED_DIR_IN (2<<ED_CTRL_DIR_Pos)
58#define ED_SPEED_FULL (0<<13) /* Info[13] - 0: is full speed device */
59#define ED_SPEED_LOW (1<<13) /* Info[13] - 1: is low speed device */
60#define ED_SKIP (1<<14) /* Info[14] - 1: HC skip this ED */
61#define ED_FORMAT_GENERAL (0<<15) /* Info[15] - 0: is a general TD */
62#define ED_FORMAT_ISO (1<<15) /* Info[15] - 1: is an isochronous TD */
63#define ED_HEADP_HALT (1<<0) /* HeadP[0] - 1: Halt; 0: Not */
64
65
66/*----------------------------------------------------------------------------------------*/
67/* Transfer descriptor */
68/*----------------------------------------------------------------------------------------*/
69/* general transfer descriptor */
70typedef struct td_t {
71 uint32_t Info;
72 uint32_t CBP; /* Current Buffer Pointer */
73 uint32_t NextTD; /* Next TD */
74 uint32_t BE; /* Buffer End */
75 uint32_t PSW[4]; /* PSW 0~7 */
76 /* The following members are used by USB Host libary. */
77 uint32_t buff_start; /* Buffer Start */
78 ED_T *ed; /* The ED that this TD belong to. */
79 struct utr_t *utr; /* associated UTR */
80 struct td_t *next; /* point to next TD of the same UTR */
81} TD_T;
82
83#define TD_ADDR_MASK 0xFFFFFFFC
84
85/* Completion codes */
86enum OCHI_CC_CODE {
87 /* mapping of the OHCI CC status to error codes */
88 CC_NOERROR, /* No Error */
89 CC_CRC, /* CRC Error */
90 CC_BITSTUFF, /* Bit Stuff */
91 CC_DATA_TOGGLE, /* Data Toggle */
92 CC_STALL, /* Stall */
93 CC_NOTRESPONSE, /* DevNotResp */
94 CC_PID_CHECK, /* PIDCheck */
95 CC_UNEXPECTED_PID, /* UnExpPID */
96 CC_DATA_OVERRUN, /* DataOver */
97 CC_DATA_UNDERRUN, /* DataUnder */
98 CC_RESERVED1, /* reserved */
99 CC_RESERVED2, /* reserved */
100 CC_BUFFER_OVERRUN, /* BufferOver */
101 CC_BUFFER_UNDERRUN, /* BuffUnder */
102 CC_NOT_ACCESS /* Not Access */
103};
104
105/* TD control field */
106#define TD_CC 0xF0000000
107#define TD_CC_GET(td) ((td >>28) & 0x0F)
108#define TD_CC_SET(td, cc) (td) = ((td) & 0x0FFFFFFF) | (((cc) & 0x0F) << 28)
109#define TD_T_DATA0 0x02000000
110#define TD_T_DATA1 0x03000000
111#define TD_R 0x00040000
112#define TD_DP 0x00180000
113#define TD_DP_IN 0x00100000
114#define TD_DP_OUT 0x00080000
115#define MAXPSW 8
116/* steel TD reserved bits to keep driver data */
117#define TD_TYPE_Msk (0x3<<16)
118#define TD_TYPE_CTRL (0x0<<16)
119#define TD_TYPE_BULK (0x1<<16)
120#define TD_TYPE_INT (0x2<<16)
121#define TD_TYPE_ISO (0x3<<16)
122#define TD_CTRL_Msk (0x7<<15)
123#define TD_CTRL_DATA (1<<15)
124
125
126/*
127 * The HCCA (Host Controller Communications Area) is a 256 byte
128 * structure defined in the OHCI spec. that the host controller is
129 * told the base address of. It must be 256-byte aligned.
130 */
131typedef struct {
132 uint32_t int_table[32]; /* Interrupt ED table */
133 uint16_t frame_no; /* current frame number */
134 uint16_t pad1; /* set to 0 on each frame_no change */
135 uint32_t done_head; /* info returned for an interrupt */
136 uint8_t reserved_for_hc[116];
137} HCCA_T;
138
139
141
142#endif /* _USBH_OHCI_H_ */