42 uint32_t u32MasterSlave,
44 uint32_t u32DataWidth,
47 uint32_t u32ClkSrc = 0, u32Div, u32HCLKFreq;
51 spi->
I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk;
53 if(u32DataWidth == 32)
67 if(u32BusClock >= u32HCLKFreq)
87 u32ClkSrc = (u32HCLKFreq / 2);
89 u32ClkSrc = u32HCLKFreq;
104 u32ClkSrc = (u32HCLKFreq / 2);
106 u32ClkSrc = u32HCLKFreq;
112 if(u32BusClock >= u32HCLKFreq)
119 else if(u32BusClock >= u32ClkSrc)
126 else if(u32BusClock == 0)
131 return (u32ClkSrc / (0xFF + 1));
135 u32Div = (((u32ClkSrc * 10) / u32BusClock + 5) / 10) - 1;
141 return (u32ClkSrc / (0xFF + 1));
147 return (u32ClkSrc / (u32Div + 1));
168 return (u32HCLKFreq / 2);
177 return (u32HCLKFreq / 2);
196 SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk;
202 SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk;
268 uint32_t u32ClkSrc, u32HCLKFreq;
274 if(u32BusClock >= u32HCLKFreq)
294 u32ClkSrc = (u32HCLKFreq / 2);
296 u32ClkSrc = u32HCLKFreq;
311 u32ClkSrc = (u32HCLKFreq / 2);
313 u32ClkSrc = u32HCLKFreq;
319 if(u32BusClock >= u32HCLKFreq)
326 else if(u32BusClock >= u32ClkSrc)
333 else if(u32BusClock == 0)
338 return (u32ClkSrc / (0xFF + 1));
342 u32Div = (((u32ClkSrc * 10) / u32BusClock + 5) / 10) - 1;
348 return (u32ClkSrc / (0xFF + 1));
354 return (u32ClkSrc / (u32Div + 1));
383 uint32_t u32ClkSrc, u32HCLKFreq;
402 u32ClkSrc = (u32HCLKFreq / 2);
404 u32ClkSrc = u32HCLKFreq;
419 u32ClkSrc = (u32HCLKFreq / 2);
421 u32ClkSrc = u32HCLKFreq;
428 return (u32ClkSrc / (u32Div + 1));
524 spi->
CTL &= ~SPI_CTL_UNITIEN_Msk;
528 spi->
SSCTL &= ~SPI_SSCTL_SSACTIEN_Msk;
532 spi->
SSCTL &= ~SPI_SSCTL_SSINAIEN_Msk;
536 spi->
SSCTL &= ~SPI_SSCTL_SLVURIEN_Msk;
540 spi->
SSCTL &= ~SPI_SSCTL_SLVBEIEN_Msk;
544 spi->
SSCTL &= ~SPI_SSCTL_SLVTOIEN_Msk;
548 spi->
FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk;
552 spi->
FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;
556 spi->
FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;
560 spi->
FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;
564 spi->
FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;
590 uint32_t u32IntFlag = 0;
708 uint32_t u32Flag = 0;
#define SPI_STATUS_TXFULL_Msk
#define SPI_SSCTL_SSACTPOL_Msk
#define SPI_FIFOCTL_RXOVIEN_Msk
#define SPI_STATUS_SSACTIF_Msk
#define SPI_CTL_UNITIEN_Msk
#define SPI_FIFOCTL_RXTH_Pos
#define SPI_FIFOCTL_TXTH_Msk
#define SPI_CTL_DWIDTH_Pos
#define SPI_STATUS_TXRXRST_Msk
#define SPI_STATUS_TXTHIF_Msk
#define SPI_STATUS_RXTHIF_Msk
#define SPI_SSCTL_SLVTOIEN_Msk
#define SPI_STATUS_UNITIF_Msk
#define SPI_SSCTL_SSACTIEN_Msk
#define SPI_CLKDIV_DIVIDER_Pos
#define SYS_IPRST1_SPI1RST_Msk
#define SPI_STATUS_SSINAIF_Msk
#define SYS_IPRST1_SPI0RST_Msk
#define SPI_FIFOCTL_TXUFIEN_Msk
#define SPI_STATUS_SLVTOIF_Msk
#define SPI_CLKDIV_DIVIDER_Msk
#define SPI_FIFOCTL_TXTH_Pos
#define SPI_CTL_SPIEN_Msk
#define SPI_SSCTL_SLVBEIEN_Msk
#define SPI_STATUS_TXEMPTY_Msk
#define SPI_SSCTL_SSINAIEN_Msk
#define SPI_STATUS_RXOVIF_Msk
#define SPI_FIFOCTL_RXTOIEN_Msk
#define SPI_FIFOCTL_RXTHIEN_Msk
#define SPI_STATUS_RXFULL_Msk
#define SPI_FIFOCTL_RXTH_Msk
#define SPI_STATUS_SLVBEIF_Msk
#define SPI_STATUS_RXTOIF_Msk
#define SPI_STATUS_RXEMPTY_Msk
#define SPI_STATUS_SSLINE_Msk
#define SPI_SSCTL_SLVURIEN_Msk
#define SPI_STATUS_TXUFIF_Msk
#define SPI_STATUS_SLVURIF_Msk
#define SPI_FIFOCTL_TXFBCLR_Msk
#define SPI_FIFOCTL_TXTHIEN_Msk
#define SPI_STATUS_SPIENSTS_Msk
#define SPI_FIFOCTL_RXFBCLR_Msk
#define SPI_SSCTL_AUTOSS_Msk
#define SPI_STATUS_BUSY_Msk
NuMicro peripheral access layer header file.
#define CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2
#define CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2
#define CLK_CLKSEL2_SPI0SEL_HXT
#define CLK_CLKSEL2_SPI0SEL_PLL
#define CLK_CLKSEL2_SPI1SEL_PCLK1
#define CLK_CLKSEL2_SPI1SEL_PLL
#define CLK_CLKSEL2_SPI0SEL_PCLK0
#define CLK_CLKSEL2_SPI1SEL_HXT
uint32_t CLK_GetHCLKFreq(void)
Get HCLK frequency.
__STATIC_INLINE uint32_t CLK_GetPLLClockFreq(void)
Get PLL clock frequency.
#define CLK_CLKSEL2_SPI1SEL_Msk
#define CLK_CLKSEL0_PCLK1SEL_Msk
#define CLK_CLKSEL2_SPI0SEL_Msk
#define CLK_CLKSEL0_PCLK0SEL_Msk
#define SPI_FIFO_RXTO_INT_MASK
#define SPI_RX_EMPTY_MASK
#define SPI_FIFO_RXTH_INT_MASK
#define SPI_SLVBE_INT_MASK
#define SPI_SSACT_INT_MASK
#define SPI_SSLINE_STS_MASK
#define SPI_SSINACT_INT_MASK
#define SPI_SS_ACTIVE_LOW
#define SPI_UNIT_INT_MASK
#define SPI_FIFO_TXTH_INT_MASK
#define SPI_SLVTO_INT_MASK
#define SPI_TX_EMPTY_MASK
#define SPI_TXRX_RESET_MASK
#define SPI_TXUF_INT_MASK
#define SPI_FIFO_RXOV_INT_MASK
#define SPI_SLVUR_INT_MASK
#define SPI_SPIEN_STS_MASK
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
Disable interrupt function.
uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask)
Get interrupt flag.
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
Enable interrupt function.
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
Enable the automatic slave selection function.
void SPI_DisableAutoSS(SPI_T *spi)
Disable the automatic slave selection function.
void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask)
Clear interrupt flag.
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
Set the SPI bus clock.
void SPI_Close(SPI_T *spi)
Disable SPI controller.
void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
Configure FIFO threshold setting.
uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask)
Get SPI status.
void SPI_ClearTxFIFO(SPI_T *spi)
Clear TX FIFO buffer.
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
This function make SPI module be ready to transfer.
uint32_t SPI_GetBusClock(SPI_T *spi)
Get the actual frequency of SPI bus clock. Only available in Master mode.
void SPI_ClearRxFIFO(SPI_T *spi)
Clear RX FIFO buffer.