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M471M/R1/S BSP V3.01.000
The Board Support Package for M4521
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Macros | |
#define | EADC_CONV_RESET(eadc) ((eadc)->CTL |= EADC_CTL_ADRST_Msk) |
A/D Converter Control Circuits Reset. More... | |
#define | EADC_ENABLE_PDMA(eadc) ((eadc)->CTL |= EADC_CTL_PDMAEN_Msk) |
Enable PDMA transfer. More... | |
#define | EADC_DISABLE_PDMA(eadc) ((eadc)->CTL &= (~EADC_CTL_PDMAEN_Msk)) |
Disable PDMA transfer. More... | |
#define | EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk) |
Enable double buffer mode. More... | |
#define | EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk) |
Disable double buffer mode. More... | |
#define | EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk) |
Set ADIFn at A/D end of conversion. More... | |
#define | EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk) |
Set ADIFn at A/D start of conversion. More... | |
#define | EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos)) |
Enable the interrupt. More... | |
#define | EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos)) |
Disable the interrupt. More... | |
#define | EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask)) |
Enable the sample module interrupt. More... | |
#define | EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= ~(u32ModuleMask)) |
Disable the sample module interrupt. More... | |
#define | EADC_SET_DMOF(eadc, u32Format) ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format)) |
Set the input mode output format. More... | |
#define | EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask)) |
Start the A/D conversion. More... | |
#define | EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask)) |
Cancel the conversion for sample module. More... | |
#define | EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS) |
Get the conversion pending flag. More... | |
#define | EADC_GET_CONV_DATA(eadc, u32ModuleNum) ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk) |
Get the conversion data of the user-specified sample module. More... | |
#define | EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask)) |
Get the data overrun flag of the user-specified sample module. More... | |
#define | EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask)) |
Get the data valid flag of the user-specified sample module. More... | |
#define | EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT_RESULT_Msk) |
Get the double data of the user-specified sample module. More... | |
#define | EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask)) |
Get the user-specified interrupt flags. More... | |
#define | EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask)) |
Get the user-specified sample module overrun flags. More... | |
#define | EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask)) |
Clear the selected interrupt status bits. More... | |
#define | EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask)) |
Clear the selected sample module overrun status bits. More... | |
#define | EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos) |
Check all sample module A/D result data register overrun flags. More... | |
#define | EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos) |
Check all sample module A/D result data register valid flags. More... | |
#define | EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos) |
Check all A/D sample module start of conversion overrun flags. More... | |
#define | EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos) |
Check all A/D interrupt flag overrun bits. More... | |
#define | EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos) |
Get the busy state of EADC. More... | |
#define | EADC_ENABLE_CMP0(eadc, u32ModuleNum, u32Condition, u16CMPData, u32MatchCount) |
Configure the comparator 0 and enable it. More... | |
#define | EADC_ENABLE_CMP1(eadc, u32ModuleNum, u32Condition, u16CMPData, u32MatchCount) |
Configure the comparator 1 and enable it. More... | |
#define | EADC_ENABLE_CMP2(eadc, u32ModuleNum, u32Condition, u16CMPData, u32MatchCount) |
Configure the comparator 2 and enable it. More... | |
#define | EADC_ENABLE_CMP3(eadc, u32ModuleNum, u32Condition, u16CMPData, u32MatchCount) |
Configure the comparator 3 and enable it. More... | |
#define | EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk) |
Enable the compare window mode. More... | |
#define | EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk) |
Disable the compare window mode. More... | |
#define | EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk) |
Enable the compare interrupt. More... | |
#define | EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk) |
Disable the compare interrupt. More... | |
#define | EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0) |
Disable comparator 0. More... | |
#define | EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0) |
Disable comparator 1. More... | |
#define | EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] = 0) |
Disable comparator 2. More... | |
#define | EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] = 0) |
Disable comparator 3. More... | |
Functions | |
void | EADC_Open (EADC_T *eadc, uint32_t u32InputMode) |
This function make EADC_module be ready to convert. More... | |
void | EADC_Close (EADC_T *eadc) |
Disable EADC_module. More... | |
void | EADC_ConfigSampleModule (EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSrc, uint32_t u32Channel) |
Configure the sample control logic module. More... | |
void | EADC_SetTriggerDelayTime (EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider) |
Set trigger delay time. More... | |
void | EADC_SetInternalSampleTime (EADC_T *eadc, uint32_t u32SampleTime) |
Set ADC internal sample time. More... | |
void | EADC_SetExtendSampleTime (EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime) |
Set ADC extend sample time. More... | |
#define EADC_CLR_INT_FLAG | ( | eadc, | |
u32Mask | |||
) | ((eadc)->STATUS2 = (u32Mask)) |
Clear the selected interrupt status bits.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32Mask | The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status. Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. |
This macro is used to clear clear the selected interrupt status bits.
#define EADC_CLR_SAMPLE_MODULE_OV_FLAG | ( | eadc, | |
u32ModuleMask | |||
) | ((eadc)->OVSTS = (u32ModuleMask)) |
Clear the selected sample module overrun status bits.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32ModuleMask | The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status. Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 18 is SPOVF18. |
This macro is used to clear the selected sample module overrun status bits.
#define EADC_CONV_RESET | ( | eadc | ) | ((eadc)->CTL |= EADC_CTL_ADRST_Msk) |
#define EADC_DISABLE_CMP0 | ( | eadc | ) | ((eadc)->CMP[0] = 0) |
#define EADC_DISABLE_CMP1 | ( | eadc | ) | ((eadc)->CMP[1] = 0) |
#define EADC_DISABLE_CMP2 | ( | eadc | ) | ((eadc)->CMP[2] = 0) |
#define EADC_DISABLE_CMP3 | ( | eadc | ) | ((eadc)->CMP[3] = 0) |
#define EADC_DISABLE_CMP_INT | ( | eadc, | |
u32CMP | |||
) | ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk) |
#define EADC_DISABLE_CMP_WINDOW_MODE | ( | eadc, | |
u32CMP | |||
) | ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk) |
Disable the compare window mode.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32CMP | Specifies the compare register, valid value are 0 and 2. |
ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.
#define EADC_DISABLE_DOUBLE_BUFFER | ( | eadc, | |
u32ModuleNum | |||
) | ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk) |
#define EADC_DISABLE_INT | ( | eadc, | |
u32Mask | |||
) | ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos)) |
Disable the interrupt.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32Mask | Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. |
Specific sample module A/D ADINT0 interrupt function Disabled.
#define EADC_DISABLE_INT_POSITION | ( | eadc, | |
u32ModuleNum | |||
) | ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk) |
Set ADIFn at A/D start of conversion.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32ModuleNum | Decides the sample module number, valid value are from 0 to 15. |
The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the end of conversion.
#define EADC_DISABLE_PDMA | ( | eadc | ) | ((eadc)->CTL &= (~EADC_CTL_PDMAEN_Msk)) |
#define EADC_DISABLE_SAMPLE_MODULE_INT | ( | eadc, | |
u32IntSel, | |||
u32ModuleMask | |||
) | ((eadc)->INTSRC[(u32IntSel)] &= ~(u32ModuleMask)) |
Disable the sample module interrupt.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32IntSel | Decides which interrupt source will be used, valid value are from 0 to 3. |
[in] | u32ModuleMask | the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. |
There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
#define EADC_ENABLE_CMP0 | ( | eadc, | |
u32ModuleNum, | |||
u32Condition, | |||
u16CMPData, | |||
u32MatchCount | |||
) |
Configure the comparator 0 and enable it.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32ModuleNum | specifies the compare sample module, valid value are from 0 to 18. |
[in] | u32Condition | specifies the compare condition. Valid values are:
|
[in] | u16CMPData | specifies the compare value, valid range are between 0~0xFFF. |
[in] | u32MatchCount | specifies the match count setting, valid range are between 0~0xF. |
For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
#define EADC_ENABLE_CMP1 | ( | eadc, | |
u32ModuleNum, | |||
u32Condition, | |||
u16CMPData, | |||
u32MatchCount | |||
) |
Configure the comparator 1 and enable it.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32ModuleNum | specifies the compare sample module, valid value are from 0 to 18. |
[in] | u32Condition | specifies the compare condition. Valid values are:
|
[in] | u16CMPData | specifies the compare value, valid range are between 0~0xFFF. |
[in] | u32MatchCount | specifies the match count setting, valid range are between 0~0xF. |
For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
#define EADC_ENABLE_CMP2 | ( | eadc, | |
u32ModuleNum, | |||
u32Condition, | |||
u16CMPData, | |||
u32MatchCount | |||
) |
Configure the comparator 2 and enable it.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32ModuleNum | specifies the compare sample module, valid value are from 0 to 18. |
[in] | u32Condition | specifies the compare condition. Valid values are:
|
[in] | u16CMPData | specifies the compare value, valid range are between 0~0xFFF. |
[in] | u32MatchCount | specifies the match count setting, valid range are between 0~0xF. |
For example, ADC_ENABLE_CMP2(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
#define EADC_ENABLE_CMP3 | ( | eadc, | |
u32ModuleNum, | |||
u32Condition, | |||
u16CMPData, | |||
u32MatchCount | |||
) |
Configure the comparator 3 and enable it.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32ModuleNum | specifies the compare sample module, valid value are from 0 to 18. |
[in] | u32Condition | specifies the compare condition. Valid values are:
|
[in] | u16CMPData | specifies the compare value, valid range are between 0~0xFFF. |
[in] | u32MatchCount | specifies the match count setting, valid range are between 1~0xF. |
For example, ADC_ENABLE_CMP3(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
#define EADC_ENABLE_CMP_INT | ( | eadc, | |
u32CMP | |||
) | ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk) |
Enable the compare interrupt.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32CMP | Specifies the compare register, valid value are from 0 to 3. |
If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated.
#define EADC_ENABLE_CMP_WINDOW_MODE | ( | eadc, | |
u32CMP | |||
) | ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk) |
Enable the compare window mode.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32CMP | Specifies the compare register, valid value are 0 and 2. |
ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched.
#define EADC_ENABLE_DOUBLE_BUFFER | ( | eadc, | |
u32ModuleNum | |||
) | ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk) |
Enable double buffer mode.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32ModuleNum | Decides the sample module number, valid value are from 0 to 3. |
The ADC controller supports a double buffer mode in sample module 0~3. If user enable DBMEN (EADC_SCTLn[23], n=0~3), the double buffer mode will enable.
#define EADC_ENABLE_INT | ( | eadc, | |
u32Mask | |||
) | ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos)) |
Enable the interrupt.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32Mask | Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. |
The A/D converter generates a conversion end ADIFn (EADC_STATUS2[n]) upon the end of specific sample module A/D conversion. If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3).
#define EADC_ENABLE_INT_POSITION | ( | eadc, | |
u32ModuleNum | |||
) | ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk) |
Set ADIFn at A/D end of conversion.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32ModuleNum | Decides the sample module number, valid value are from 0 to 15. |
The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the start of conversion.
#define EADC_ENABLE_PDMA | ( | eadc | ) | ((eadc)->CTL |= EADC_CTL_PDMAEN_Msk) |
Enable PDMA transfer.
[in] | eadc | The pointer of the specified EADC module. |
When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request.
#define EADC_ENABLE_SAMPLE_MODULE_INT | ( | eadc, | |
u32IntSel, | |||
u32ModuleMask | |||
) | ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask)) |
Enable the sample module interrupt.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32IntSel | Decides which interrupt source will be used, valid value are from 0 to 3. |
[in] | u32ModuleMask | the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFF. |
There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
#define EADC_GET_CONV_DATA | ( | eadc, | |
u32ModuleNum | |||
) | ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk) |
Get the conversion data of the user-specified sample module.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32ModuleNum | Decides the sample module number, valid value are from 0 to 18. |
This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data.
#define EADC_GET_DATA_OVERRUN_FLAG | ( | eadc, | |
u32ModuleMask | |||
) | ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask)) |
Get the data overrun flag of the user-specified sample module.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32ModuleMask | The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF. |
This macro is used to read OV bit (EADC_STATUS0[31:16], EADC_STATUS1[18:16]) field to get data overrun status.
#define EADC_GET_DATA_VALID_FLAG | ( | eadc, | |
u32ModuleMask | |||
) | ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask)) |
Get the data valid flag of the user-specified sample module.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32ModuleMask | The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF. |
This macro is used to read VALID bit (EADC_STATUS0[15:0], EADC_STATUS1[1:0]) field to get data overrun status.
#define EADC_GET_DOUBLE_DATA | ( | eadc, | |
u32ModuleNum | |||
) | ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT_RESULT_Msk) |
Get the double data of the user-specified sample module.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32ModuleNum | Decides the sample module number, valid value are from 0 to 18. |
This macro is used to read RESULT bit (EADC_DDATn[15:0], n=0~3) field to get conversion data.
#define EADC_GET_INT_FLAG | ( | eadc, | |
u32Mask | |||
) | ((eadc)->STATUS2 & (u32Mask)) |
Get the user-specified interrupt flags.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32Mask | The combination of interrupt status bits. Each bit corresponds to a interrupt status. Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. |
This macro is used to get the user-specified interrupt flags.
#define EADC_GET_PENDING_CONV | ( | eadc | ) | ((eadc)->PENDSTS) |
Get the conversion pending flag.
[in] | eadc | The pointer of the specified EADC module. |
This STPFn(EADC_PENDSTS[18:0]) bit remains 1 during pending state, when the respective ADC conversion is end, the STPFn (n=0~18) bit is automatically cleared to 0.
#define EADC_GET_SAMPLE_MODULE_OV_FLAG | ( | eadc, | |
u32ModuleMask | |||
) | ((eadc)->OVSTS & (u32ModuleMask)) |
Get the user-specified sample module overrun flags.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32ModuleMask | The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFF. |
This macro is used to get the user-specified sample module overrun flags.
#define EADC_IS_BUSY | ( | eadc | ) | (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos) |
#define EADC_IS_DATA_OV | ( | eadc | ) | (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos) |
Check all sample module A/D result data register overrun flags.
[in] | eadc | The pointer of the specified EADC module. |
0 | None of sample module data register overrun flag is set to 1. |
1 | Any one of sample module data register overrun flag is set to 1. |
The AOV bit (EADC_STATUS2[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
#define EADC_IS_DATA_VALID | ( | eadc | ) | (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos) |
Check all sample module A/D result data register valid flags.
[in] | eadc | The pointer of the specified EADC module. |
0 | None of sample module data register valid flag is set to 1. |
1 | Any one of sample module data register valid flag is set to 1. |
The AVALID bit (EADC_STATUS2[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
#define EADC_IS_INT_FLAG_OV | ( | eadc | ) | (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos) |
Check all A/D interrupt flag overrun bits.
[in] | eadc | The pointer of the specified EADC module. |
0 | None of ADINT interrupt flag is overwritten to 1. |
1 | Any one of ADINT interrupt flag is overwritten to 1. |
The ADOVIF bit (EADC_STATUS2[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
#define EADC_IS_SAMPLE_MODULE_OV | ( | eadc | ) | (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos) |
Check all A/D sample module start of conversion overrun flags.
[in] | eadc | The pointer of the specified EADC module. |
0 | None of sample module event overrun flag is set to 1. |
1 | Any one of sample module event overrun flag is set to 1. |
The STOVF bit (EADC_STATUS2[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
#define EADC_SET_DMOF | ( | eadc, | |
u32Format | |||
) | ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format)) |
Set the input mode output format.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32Format | Decides the output format. Valid values are:
|
The macro is used to set A/D input mode output format.
#define EADC_START_CONV | ( | eadc, | |
u32ModuleMask | |||
) | ((eadc)->SWTRG = (u32ModuleMask)) |
Start the A/D conversion.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32ModuleMask | The combination of sample module. Each bit corresponds to a sample module. This parameter decides which sample module will be conversion, valid range are between 1~0x7FFFF. Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18. |
After write EADC_SWTRG register to start ADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion.
#define EADC_STOP_CONV | ( | eadc, | |
u32ModuleMask | |||
) | ((eadc)->PENDSTS = (u32ModuleMask)) |
Cancel the conversion for sample module.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32ModuleMask | The combination of sample module. Each bit corresponds to a sample module. This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFF. Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module18. |
If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
void EADC_Close | ( | EADC_T * | eadc | ) |
void EADC_ConfigSampleModule | ( | EADC_T * | eadc, |
uint32_t | u32ModuleNum, | ||
uint32_t | u32TriggerSrc, | ||
uint32_t | u32Channel | ||
) |
Configure the sample control logic module.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32ModuleNum | Decides the sample module number, valid value are from 0 to 15. |
[in] | u32TriggerSrc | Decides the trigger source. Valid values are:
|
[in] | u32Channel | Specifies the sample module channel, valid value are from 0 to 15. |
Each of ADC control logic modules 0~15 which is configurable for ADC converter channel EADC_CH0~15 and trigger source. sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap voltage, temperature sensor, and battery power (VBAT).
void EADC_Open | ( | EADC_T * | eadc, |
uint32_t | u32InputMode | ||
) |
This function make EADC_module be ready to convert.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32InputMode | Decides the input mode.
|
This function is used to set analog input mode and enable A/D Converter. Before starting A/D conversion function, ADCEN bit (EADC_CTL[0]) should be set to 1.
void EADC_SetExtendSampleTime | ( | EADC_T * | eadc, |
uint32_t | u32ModuleNum, | ||
uint32_t | u32ExtendSampleTime | ||
) |
Set ADC extend sample time.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32ModuleNum | Decides the sample module number, valid value are from 0 to 18. |
[in] | u32ExtendSampleTime | Decides the extend sampling time, the range is from 0~255 ADC clock. Valid value are from 0 to 0xFF. |
When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend A/D sampling time after trigger source is coming to get enough sampling time.
void EADC_SetInternalSampleTime | ( | EADC_T * | eadc, |
uint32_t | u32SampleTime | ||
) |
Set ADC internal sample time.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32SampleTime | Decides the internal sampling time, the range is from 1~8 ADC clock. Valid value are from 1 to 8. |
When A/D operation at high ADC clock rate, the sampling time of analog input voltage may not enough if the analog channel has heavy loading to cause fully charge time is longer. User can set SMPTSEL (EADC_CTL[18:16]) to select the sampling cycle in ADC.
void EADC_SetTriggerDelayTime | ( | EADC_T * | eadc, |
uint32_t | u32ModuleNum, | ||
uint32_t | u32TriggerDelayTime, | ||
uint32_t | u32DelayClockDivider | ||
) |
Set trigger delay time.
[in] | eadc | The pointer of the specified EADC module. |
[in] | u32ModuleNum | Decides the sample module number, valid value are from 0 to 15. |
[in] | u32TriggerDelayTime | Decides the trigger delay time, valid range are between 0~0xFF. |
[in] | u32DelayClockDivider | Decides the trigger delay clock divider. Valid values are:
|
User can configure the trigger delay time by setting TRGDLYCNT (EADC_SCTLn[15:8], n=0~15) and TRGDLYDIV (EADC_SCTLn[7:6], n=0~15). Trigger delay time = (u32TriggerDelayTime) x Trigger delay clock period.