M471M/R1/S BSP V3.01.000
The Board Support Package for M4521
Modules | Macros
CLK Exported Constants
Collaboration diagram for CLK Exported Constants:

Modules

 CLK Exported Functions
 

Macros

#define FREQ_25MHZ   25000000
 
#define FREQ_50MHZ   50000000
 
#define FREQ_72MHZ   72000000
 
#define FREQ_125MHZ   125000000
 
#define FREQ_200MHZ   200000000
 
#define FREQ_250MHZ   250000000
 
#define FREQ_500MHZ   500000000
 
#define CLK_CLKSEL0_HCLKSEL_HXT   (0x00UL<<CLK_CLKSEL0_HCLKSEL_Pos)
 
#define CLK_CLKSEL0_HCLKSEL_LXT   (0x01UL<<CLK_CLKSEL0_HCLKSEL_Pos)
 
#define CLK_CLKSEL0_HCLKSEL_PLL   (0x02UL<<CLK_CLKSEL0_HCLKSEL_Pos)
 
#define CLK_CLKSEL0_HCLKSEL_LIRC   (0x03UL<<CLK_CLKSEL0_HCLKSEL_Pos)
 
#define CLK_CLKSEL0_HCLKSEL_HIRC   (0x07UL<<CLK_CLKSEL0_HCLKSEL_Pos)
 
#define CLK_CLKSEL0_STCLKSEL_HXT   (0x00UL<<CLK_CLKSEL0_STCLKSEL_Pos)
 
#define CLK_CLKSEL0_STCLKSEL_LXT   (0x01UL<<CLK_CLKSEL0_STCLKSEL_Pos)
 
#define CLK_CLKSEL0_STCLKSEL_HXT_DIV2   (0x02UL<<CLK_CLKSEL0_STCLKSEL_Pos)
 
#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2   (0x03UL<<CLK_CLKSEL0_STCLKSEL_Pos)
 
#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2   (0x07UL<<CLK_CLKSEL0_STCLKSEL_Pos)
 
#define CLK_CLKSEL0_STCLKSEL_HCLK   (0x01UL<<SysTick_CTRL_CLKSOURCE_Pos)
 
#define CLK_CLKSEL0_PCLK0SEL_HCLK   (0x00UL<<CLK_CLKSEL0_PCLK0SEL_Pos)
 
#define CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2   (0x01UL<<CLK_CLKSEL0_PCLK0SEL_Pos)
 
#define CLK_CLKSEL0_PCLK1SEL_HCLK   (0x00UL<<CLK_CLKSEL0_PCLK1SEL_Pos)
 
#define CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2   (0x01UL<<CLK_CLKSEL0_PCLK1SEL_Pos)
 
#define CLK_CLKSEL1_WDTSEL_LXT   (0x1UL<<CLK_CLKSEL1_WDTSEL_Pos)
 
#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048   (0x2UL<<CLK_CLKSEL1_WDTSEL_Pos)
 
#define CLK_CLKSEL1_WDTSEL_LIRC   (0x3UL<<CLK_CLKSEL1_WDTSEL_Pos)
 
#define CLK_CLKSEL1_TMR0SEL_HXT   (0x0UL<<CLK_CLKSEL1_TMR0SEL_Pos)
 
#define CLK_CLKSEL1_TMR0SEL_LXT   (0x1UL<<CLK_CLKSEL1_TMR0SEL_Pos)
 
#define CLK_CLKSEL1_TMR0SEL_PCLK0   (0x2UL<<CLK_CLKSEL1_TMR0SEL_Pos)
 
#define CLK_CLKSEL1_TMR0SEL_EXT_TRG   (0x3UL<<CLK_CLKSEL1_TMR0SEL_Pos)
 
#define CLK_CLKSEL1_TMR0SEL_LIRC   (0x5UL<<CLK_CLKSEL1_TMR0SEL_Pos)
 
#define CLK_CLKSEL1_TMR0SEL_HIRC   (0x7UL<<CLK_CLKSEL1_TMR0SEL_Pos)
 
#define CLK_CLKSEL1_TMR1SEL_HXT   (0x0UL<<CLK_CLKSEL1_TMR1SEL_Pos)
 
#define CLK_CLKSEL1_TMR1SEL_LXT   (0x1UL<<CLK_CLKSEL1_TMR1SEL_Pos)
 
#define CLK_CLKSEL1_TMR1SEL_PCLK0   (0x2UL<<CLK_CLKSEL1_TMR1SEL_Pos)
 
#define CLK_CLKSEL1_TMR1SEL_EXT_TRG   (0x3UL<<CLK_CLKSEL1_TMR1SEL_Pos)
 
#define CLK_CLKSEL1_TMR1SEL_LIRC   (0x5UL<<CLK_CLKSEL1_TMR1SEL_Pos)
 
#define CLK_CLKSEL1_TMR1SEL_HIRC   (0x7UL<<CLK_CLKSEL1_TMR1SEL_Pos)
 
#define CLK_CLKSEL1_TMR2SEL_HXT   (0x0UL<<CLK_CLKSEL1_TMR2SEL_Pos)
 
#define CLK_CLKSEL1_TMR2SEL_LXT   (0x1UL<<CLK_CLKSEL1_TMR2SEL_Pos)
 
#define CLK_CLKSEL1_TMR2SEL_PCLK1   (0x2UL<<CLK_CLKSEL1_TMR2SEL_Pos)
 
#define CLK_CLKSEL1_TMR2SEL_EXT_TRG   (0x3UL<<CLK_CLKSEL1_TMR2SEL_Pos)
 
#define CLK_CLKSEL1_TMR2SEL_LIRC   (0x5UL<<CLK_CLKSEL1_TMR2SEL_Pos)
 
#define CLK_CLKSEL1_TMR2SEL_HIRC   (0x7UL<<CLK_CLKSEL1_TMR2SEL_Pos)
 
#define CLK_CLKSEL1_TMR3SEL_HXT   (0x0UL<<CLK_CLKSEL1_TMR3SEL_Pos)
 
#define CLK_CLKSEL1_TMR3SEL_LXT   (0x1UL<<CLK_CLKSEL1_TMR3SEL_Pos)
 
#define CLK_CLKSEL1_TMR3SEL_PCLK1   (0x2UL<<CLK_CLKSEL1_TMR3SEL_Pos)
 
#define CLK_CLKSEL1_TMR3SEL_EXT_TRG   (0x3UL<<CLK_CLKSEL1_TMR3SEL_Pos)
 
#define CLK_CLKSEL1_TMR3SEL_LIRC   (0x5UL<<CLK_CLKSEL1_TMR3SEL_Pos)
 
#define CLK_CLKSEL1_TMR3SEL_HIRC   (0x7UL<<CLK_CLKSEL1_TMR3SEL_Pos)
 
#define CLK_CLKSEL1_UARTSEL_HXT   (0x0UL<<CLK_CLKSEL1_UARTSEL_Pos)
 
#define CLK_CLKSEL1_UARTSEL_PLL   (0x1UL<<CLK_CLKSEL1_UARTSEL_Pos)
 
#define CLK_CLKSEL1_UARTSEL_LXT   (0x2UL<<CLK_CLKSEL1_UARTSEL_Pos)
 
#define CLK_CLKSEL1_UARTSEL_HIRC   (0x3UL<<CLK_CLKSEL1_UARTSEL_Pos)
 
#define CLK_CLKSEL1_CLKOSEL_HXT   (0x0UL<<CLK_CLKSEL1_CLKOSEL_Pos)
 
#define CLK_CLKSEL1_CLKOSEL_LXT   (0x1UL<<CLK_CLKSEL1_CLKOSEL_Pos)
 
#define CLK_CLKSEL1_CLKOSEL_HCLK   (0x2UL<<CLK_CLKSEL1_CLKOSEL_Pos)
 
#define CLK_CLKSEL1_CLKOSEL_HIRC   (0x3UL<<CLK_CLKSEL1_CLKOSEL_Pos)
 
#define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048   (0x2UL<<CLK_CLKSEL1_WWDTSEL_Pos)
 
#define CLK_CLKSEL1_WWDTSEL_LIRC   (0x3UL<<CLK_CLKSEL1_WWDTSEL_Pos)
 
#define CLK_CLKSEL2_PWM0SEL_PLL   (0x0UL<<CLK_CLKSEL2_PWM0SEL_Pos)
 
#define CLK_CLKSEL2_PWM0SEL_PCLK0   (0x1UL<<CLK_CLKSEL2_PWM0SEL_Pos)
 
#define CLK_CLKSEL2_PWM1SEL_PLL   (0x0UL<<CLK_CLKSEL2_PWM1SEL_Pos)
 
#define CLK_CLKSEL2_PWM1SEL_PCLK1   (0x1UL<<CLK_CLKSEL2_PWM1SEL_Pos)
 
#define CLK_CLKSEL2_SPI0SEL_HXT   (0x0UL<<CLK_CLKSEL2_SPI0SEL_Pos)
 
#define CLK_CLKSEL2_SPI0SEL_PLL   (0x1UL<<CLK_CLKSEL2_SPI0SEL_Pos)
 
#define CLK_CLKSEL2_SPI0SEL_PCLK0   (0x2UL<<CLK_CLKSEL2_SPI0SEL_Pos)
 
#define CLK_CLKSEL2_SPI0SEL_HIRC   (0x3UL<<CLK_CLKSEL2_SPI0SEL_Pos)
 
#define CLK_CLKSEL2_SPI1SEL_HXT   (0x0UL<<CLK_CLKSEL2_SPI1SEL_Pos)
 
#define CLK_CLKSEL2_SPI1SEL_PLL   (0x1UL<<CLK_CLKSEL2_SPI1SEL_Pos)
 
#define CLK_CLKSEL2_SPI1SEL_PCLK1   (0x2UL<<CLK_CLKSEL2_SPI1SEL_Pos)
 
#define CLK_CLKSEL2_SPI1SEL_HIRC   (0x3UL<<CLK_CLKSEL2_SPI1SEL_Pos)
 
#define CLK_CLKSEL3_SC0SEL_HXT   (0x0UL<<CLK_CLKSEL3_SC0SEL_Pos)
 
#define CLK_CLKSEL3_SC0SEL_PLL   (0x1UL<<CLK_CLKSEL3_SC0SEL_Pos)
 
#define CLK_CLKSEL3_SC0SEL_PCLK0   (0x2UL<<CLK_CLKSEL3_SC0SEL_Pos)
 
#define CLK_CLKSEL3_SC0SEL_HIRC   (0x3UL<<CLK_CLKSEL3_SC0SEL_Pos)
 
#define CLK_CLKSEL3_RTCSEL_LXT   (0x0UL<<CLK_CLKSEL3_RTCSEL_Pos)
 
#define CLK_CLKSEL3_RTCSEL_LIRC   (0x1UL<<CLK_CLKSEL3_RTCSEL_Pos)
 
#define CLK_CLKDIV0_HCLK(x)   (((x)-1) << CLK_CLKDIV0_HCLKDIV_Pos)
 
#define CLK_CLKDIV0_USB(x)   (((x)-1) << CLK_CLKDIV0_USBDIV_Pos)
 
#define CLK_CLKDIV0_UART(x)   (((x)-1) << CLK_CLKDIV0_UARTDIV_Pos)
 
#define CLK_CLKDIV0_EADC(x)   (((x)-1) << CLK_CLKDIV0_EADCDIV_Pos)
 
#define CLK_CLKDIV1_SC0(x)   (((x)-1) << CLK_CLKDIV1_SC0DIV_Pos)
 
#define CLK_PLLCTL_PLLSRC_HXT   0x00000000UL
 
#define CLK_PLLCTL_PLLSRC_HIRC   0x00080000UL
 
#define CLK_PLLCTL_NF(x)   ((x)-2)
 
#define CLK_PLLCTL_NR(x)   (((x)-2)<<9)
 
#define CLK_PLLCTL_NO_1   0x0000UL
 
#define CLK_PLLCTL_NO_2   0x4000UL
 
#define CLK_PLLCTL_NO_4   0xC000UL
 
#define CLK_PLLCTL_72MHz_HXT   (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 48) | CLK_PLLCTL_NO_4)
 
#define CLK_PLLCTL_144MHz_HXT   (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 48) | CLK_PLLCTL_NO_2)
 
#define CLK_PLLCTL_72MHz_HIRC   (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 52) | CLK_PLLCTL_NO_4)
 
#define MODULE_APBCLK(x)   (((x) >>30) & 0x3)
 
#define MODULE_CLKSEL(x)   (((x) >>28) & 0x3)
 
#define MODULE_CLKSEL_Msk(x)   (((x) >>25) & 0x7)
 
#define MODULE_CLKSEL_Pos(x)   (((x) >>20) & 0x1f)
 
#define MODULE_CLKDIV(x)   (((x) >>18) & 0x3)
 
#define MODULE_CLKDIV_Msk(x)   (((x) >>10) & 0xff)
 
#define MODULE_CLKDIV_Pos(x)   (((x) >>5 ) & 0x1f)
 
#define MODULE_IP_EN_Pos(x)   (((x) >>0 ) & 0x1f)
 
#define MODULE_NoMsk   0x0
 
#define NA   MODULE_NoMsk
 
#define MODULE_APBCLK_ENC(x)   (((x) & 0x03) << 30)
 
#define MODULE_CLKSEL_ENC(x)   (((x) & 0x03) << 28)
 
#define MODULE_CLKSEL_Msk_ENC(x)   (((x) & 0x07) << 25)
 
#define MODULE_CLKSEL_Pos_ENC(x)   (((x) & 0x1f) << 20)
 
#define MODULE_CLKDIV_ENC(x)   (((x) & 0x03) << 18)
 
#define MODULE_CLKDIV_Msk_ENC(x)   (((x) & 0xff) << 10)
 
#define MODULE_CLKDIV_Pos_ENC(x)   (((x) & 0x1f) << 5)
 
#define MODULE_IP_EN_Pos_ENC(x)   (((x) & 0x1f) << 0)
 
#define PDMA_MODULE
 
#define ISP_MODULE
 
#define EBI_MODULE
 
#define USBH_MODULE
 
#define CRC_MODULE
 
#define WDT_MODULE
 
#define WWDT_MODULE
 
#define RTC_MODULE
 
#define TMR0_MODULE
 
#define TMR1_MODULE
 
#define TMR2_MODULE
 
#define TMR3_MODULE
 
#define CLKO_MODULE
 
#define I2C0_MODULE
 
#define I2C1_MODULE
 
#define SPI0_MODULE
 
#define SPI1_MODULE
 
#define UART0_MODULE
 
#define UART1_MODULE
 
#define UART2_MODULE
 
#define UART3_MODULE
 
#define USBD_MODULE
 
#define EADC_MODULE
 
#define SC0_MODULE
 
#define PWM0_MODULE
 
#define PWM1_MODULE
 

Detailed Description

Macro Definition Documentation

◆ CLK_CLKDIV0_EADC

#define CLK_CLKDIV0_EADC (   x)    (((x)-1) << CLK_CLKDIV0_EADCDIV_Pos)

CLKDIV0 Setting for EADC clock divider. It could be 1~256

Definition at line 148 of file clk.h.

◆ CLK_CLKDIV0_HCLK

#define CLK_CLKDIV0_HCLK (   x)    (((x)-1) << CLK_CLKDIV0_HCLKDIV_Pos)

CLKDIV0 Setting for HCLK clock divider. It could be 1~16

Definition at line 145 of file clk.h.

◆ CLK_CLKDIV0_UART

#define CLK_CLKDIV0_UART (   x)    (((x)-1) << CLK_CLKDIV0_UARTDIV_Pos)

CLKDIV0 Setting for UART clock divider. It could be 1~16

Definition at line 147 of file clk.h.

◆ CLK_CLKDIV0_USB

#define CLK_CLKDIV0_USB (   x)    (((x)-1) << CLK_CLKDIV0_USBDIV_Pos)

CLKDIV0 Setting for USB clock divider. It could be 1~16

Definition at line 146 of file clk.h.

◆ CLK_CLKDIV1_SC0

#define CLK_CLKDIV1_SC0 (   x)    (((x)-1) << CLK_CLKDIV1_SC0DIV_Pos)

CLKDIV1 Setting for SC0 clock divider. It could be 1~256

Definition at line 154 of file clk.h.

◆ CLK_CLKSEL0_HCLKSEL_HIRC

#define CLK_CLKSEL0_HCLKSEL_HIRC   (0x07UL<<CLK_CLKSEL0_HCLKSEL_Pos)

Setting HCLK clock source as HIRC

Definition at line 45 of file clk.h.

◆ CLK_CLKSEL0_HCLKSEL_HXT

#define CLK_CLKSEL0_HCLKSEL_HXT   (0x00UL<<CLK_CLKSEL0_HCLKSEL_Pos)

Setting HCLK clock source as HXT

Definition at line 41 of file clk.h.

◆ CLK_CLKSEL0_HCLKSEL_LIRC

#define CLK_CLKSEL0_HCLKSEL_LIRC   (0x03UL<<CLK_CLKSEL0_HCLKSEL_Pos)

Setting HCLK clock source as LIRC

Definition at line 44 of file clk.h.

◆ CLK_CLKSEL0_HCLKSEL_LXT

#define CLK_CLKSEL0_HCLKSEL_LXT   (0x01UL<<CLK_CLKSEL0_HCLKSEL_Pos)

Setting HCLK clock source as LXT

Definition at line 42 of file clk.h.

◆ CLK_CLKSEL0_HCLKSEL_PLL

#define CLK_CLKSEL0_HCLKSEL_PLL   (0x02UL<<CLK_CLKSEL0_HCLKSEL_Pos)

Setting HCLK clock source as PLL

Definition at line 43 of file clk.h.

◆ CLK_CLKSEL0_PCLK0SEL_HCLK

#define CLK_CLKSEL0_PCLK0SEL_HCLK   (0x00UL<<CLK_CLKSEL0_PCLK0SEL_Pos)

Setting PCLK0 clock source as HCLK

Definition at line 54 of file clk.h.

◆ CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2

#define CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2   (0x01UL<<CLK_CLKSEL0_PCLK0SEL_Pos)

Setting PCLK0 clock source as HCLK/2

Definition at line 55 of file clk.h.

◆ CLK_CLKSEL0_PCLK1SEL_HCLK

#define CLK_CLKSEL0_PCLK1SEL_HCLK   (0x00UL<<CLK_CLKSEL0_PCLK1SEL_Pos)

Setting PCLK1 clock source as HCLK

Definition at line 57 of file clk.h.

◆ CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2

#define CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2   (0x01UL<<CLK_CLKSEL0_PCLK1SEL_Pos)

Setting PCLK1 clock source as HCLK/2

Definition at line 58 of file clk.h.

◆ CLK_CLKSEL0_STCLKSEL_HCLK

#define CLK_CLKSEL0_STCLKSEL_HCLK   (0x01UL<<SysTick_CTRL_CLKSOURCE_Pos)

Setting SysTick clock source as HCLK

Definition at line 52 of file clk.h.

◆ CLK_CLKSEL0_STCLKSEL_HCLK_DIV2

#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2   (0x03UL<<CLK_CLKSEL0_STCLKSEL_Pos)

Setting SysTick clock source as HCLK/2

Definition at line 50 of file clk.h.

◆ CLK_CLKSEL0_STCLKSEL_HIRC_DIV2

#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2   (0x07UL<<CLK_CLKSEL0_STCLKSEL_Pos)

Setting SysTick clock source as HIRC/2

Definition at line 51 of file clk.h.

◆ CLK_CLKSEL0_STCLKSEL_HXT

#define CLK_CLKSEL0_STCLKSEL_HXT   (0x00UL<<CLK_CLKSEL0_STCLKSEL_Pos)

Setting SysTick clock source as HXT

Definition at line 47 of file clk.h.

◆ CLK_CLKSEL0_STCLKSEL_HXT_DIV2

#define CLK_CLKSEL0_STCLKSEL_HXT_DIV2   (0x02UL<<CLK_CLKSEL0_STCLKSEL_Pos)

Setting SysTick clock source as HXT

Definition at line 49 of file clk.h.

◆ CLK_CLKSEL0_STCLKSEL_LXT

#define CLK_CLKSEL0_STCLKSEL_LXT   (0x01UL<<CLK_CLKSEL0_STCLKSEL_Pos)

Setting SysTick clock source as LXT

Definition at line 48 of file clk.h.

◆ CLK_CLKSEL1_CLKOSEL_HCLK

#define CLK_CLKSEL1_CLKOSEL_HCLK   (0x2UL<<CLK_CLKSEL1_CLKOSEL_Pos)

Setting CLKO clock source as HCLK

Definition at line 103 of file clk.h.

◆ CLK_CLKSEL1_CLKOSEL_HIRC

#define CLK_CLKSEL1_CLKOSEL_HIRC   (0x3UL<<CLK_CLKSEL1_CLKOSEL_Pos)

Setting CLKO clock source as HIRC

Definition at line 104 of file clk.h.

◆ CLK_CLKSEL1_CLKOSEL_HXT

#define CLK_CLKSEL1_CLKOSEL_HXT   (0x0UL<<CLK_CLKSEL1_CLKOSEL_Pos)

Setting CLKO clock source as HXT

Definition at line 101 of file clk.h.

◆ CLK_CLKSEL1_CLKOSEL_LXT

#define CLK_CLKSEL1_CLKOSEL_LXT   (0x1UL<<CLK_CLKSEL1_CLKOSEL_Pos)

Setting CLKO clock source as LXT

Definition at line 102 of file clk.h.

◆ CLK_CLKSEL1_TMR0SEL_EXT_TRG

#define CLK_CLKSEL1_TMR0SEL_EXT_TRG   (0x3UL<<CLK_CLKSEL1_TMR0SEL_Pos)

Setting Timer 0 clock source as external trigger

Definition at line 71 of file clk.h.

◆ CLK_CLKSEL1_TMR0SEL_HIRC

#define CLK_CLKSEL1_TMR0SEL_HIRC   (0x7UL<<CLK_CLKSEL1_TMR0SEL_Pos)

Setting Timer 0 clock source as HIRC

Definition at line 73 of file clk.h.

◆ CLK_CLKSEL1_TMR0SEL_HXT

#define CLK_CLKSEL1_TMR0SEL_HXT   (0x0UL<<CLK_CLKSEL1_TMR0SEL_Pos)

Setting Timer 0 clock source as HXT

Definition at line 68 of file clk.h.

◆ CLK_CLKSEL1_TMR0SEL_LIRC

#define CLK_CLKSEL1_TMR0SEL_LIRC   (0x5UL<<CLK_CLKSEL1_TMR0SEL_Pos)

Setting Timer 0 clock source as LIRC

Definition at line 72 of file clk.h.

◆ CLK_CLKSEL1_TMR0SEL_LXT

#define CLK_CLKSEL1_TMR0SEL_LXT   (0x1UL<<CLK_CLKSEL1_TMR0SEL_Pos)

Setting Timer 0 clock source as LXT

Definition at line 69 of file clk.h.

◆ CLK_CLKSEL1_TMR0SEL_PCLK0

#define CLK_CLKSEL1_TMR0SEL_PCLK0   (0x2UL<<CLK_CLKSEL1_TMR0SEL_Pos)

Setting Timer 0 clock source as PCLK0

Definition at line 70 of file clk.h.

◆ CLK_CLKSEL1_TMR1SEL_EXT_TRG

#define CLK_CLKSEL1_TMR1SEL_EXT_TRG   (0x3UL<<CLK_CLKSEL1_TMR1SEL_Pos)

Setting Timer 1 clock source as external trigger

Definition at line 78 of file clk.h.

◆ CLK_CLKSEL1_TMR1SEL_HIRC

#define CLK_CLKSEL1_TMR1SEL_HIRC   (0x7UL<<CLK_CLKSEL1_TMR1SEL_Pos)

Setting Timer 1 clock source as HIRC

Definition at line 80 of file clk.h.

◆ CLK_CLKSEL1_TMR1SEL_HXT

#define CLK_CLKSEL1_TMR1SEL_HXT   (0x0UL<<CLK_CLKSEL1_TMR1SEL_Pos)

Setting Timer 1 clock source as HXT

Definition at line 75 of file clk.h.

◆ CLK_CLKSEL1_TMR1SEL_LIRC

#define CLK_CLKSEL1_TMR1SEL_LIRC   (0x5UL<<CLK_CLKSEL1_TMR1SEL_Pos)

Setting Timer 1 clock source as LIRC

Definition at line 79 of file clk.h.

◆ CLK_CLKSEL1_TMR1SEL_LXT

#define CLK_CLKSEL1_TMR1SEL_LXT   (0x1UL<<CLK_CLKSEL1_TMR1SEL_Pos)

Setting Timer 1 clock source as LXT

Definition at line 76 of file clk.h.

◆ CLK_CLKSEL1_TMR1SEL_PCLK0

#define CLK_CLKSEL1_TMR1SEL_PCLK0   (0x2UL<<CLK_CLKSEL1_TMR1SEL_Pos)

Setting Timer 1 clock source as PCLK0

Definition at line 77 of file clk.h.

◆ CLK_CLKSEL1_TMR2SEL_EXT_TRG

#define CLK_CLKSEL1_TMR2SEL_EXT_TRG   (0x3UL<<CLK_CLKSEL1_TMR2SEL_Pos)

Setting Timer 2 clock source as external trigger

Definition at line 85 of file clk.h.

◆ CLK_CLKSEL1_TMR2SEL_HIRC

#define CLK_CLKSEL1_TMR2SEL_HIRC   (0x7UL<<CLK_CLKSEL1_TMR2SEL_Pos)

Setting Timer 2 clock source as HIRC

Definition at line 87 of file clk.h.

◆ CLK_CLKSEL1_TMR2SEL_HXT

#define CLK_CLKSEL1_TMR2SEL_HXT   (0x0UL<<CLK_CLKSEL1_TMR2SEL_Pos)

Setting Timer 2 clock source as HXT

Definition at line 82 of file clk.h.

◆ CLK_CLKSEL1_TMR2SEL_LIRC

#define CLK_CLKSEL1_TMR2SEL_LIRC   (0x5UL<<CLK_CLKSEL1_TMR2SEL_Pos)

Setting Timer 2 clock source as LIRC

Definition at line 86 of file clk.h.

◆ CLK_CLKSEL1_TMR2SEL_LXT

#define CLK_CLKSEL1_TMR2SEL_LXT   (0x1UL<<CLK_CLKSEL1_TMR2SEL_Pos)

Setting Timer 2 clock source as LXT

Definition at line 83 of file clk.h.

◆ CLK_CLKSEL1_TMR2SEL_PCLK1

#define CLK_CLKSEL1_TMR2SEL_PCLK1   (0x2UL<<CLK_CLKSEL1_TMR2SEL_Pos)

Setting Timer 2 clock source as PCLK1

Definition at line 84 of file clk.h.

◆ CLK_CLKSEL1_TMR3SEL_EXT_TRG

#define CLK_CLKSEL1_TMR3SEL_EXT_TRG   (0x3UL<<CLK_CLKSEL1_TMR3SEL_Pos)

Setting Timer 3 clock source as external trigger

Definition at line 92 of file clk.h.

◆ CLK_CLKSEL1_TMR3SEL_HIRC

#define CLK_CLKSEL1_TMR3SEL_HIRC   (0x7UL<<CLK_CLKSEL1_TMR3SEL_Pos)

Setting Timer 3 clock source as HIRC

Definition at line 94 of file clk.h.

◆ CLK_CLKSEL1_TMR3SEL_HXT

#define CLK_CLKSEL1_TMR3SEL_HXT   (0x0UL<<CLK_CLKSEL1_TMR3SEL_Pos)

Setting Timer 3 clock source as HXT

Definition at line 89 of file clk.h.

◆ CLK_CLKSEL1_TMR3SEL_LIRC

#define CLK_CLKSEL1_TMR3SEL_LIRC   (0x5UL<<CLK_CLKSEL1_TMR3SEL_Pos)

Setting Timer 3 clock source as LIRC

Definition at line 93 of file clk.h.

◆ CLK_CLKSEL1_TMR3SEL_LXT

#define CLK_CLKSEL1_TMR3SEL_LXT   (0x1UL<<CLK_CLKSEL1_TMR3SEL_Pos)

Setting Timer 3 clock source as LXT

Definition at line 90 of file clk.h.

◆ CLK_CLKSEL1_TMR3SEL_PCLK1

#define CLK_CLKSEL1_TMR3SEL_PCLK1   (0x2UL<<CLK_CLKSEL1_TMR3SEL_Pos)

Setting Timer 3 clock source as PCLK1

Definition at line 91 of file clk.h.

◆ CLK_CLKSEL1_UARTSEL_HIRC

#define CLK_CLKSEL1_UARTSEL_HIRC   (0x3UL<<CLK_CLKSEL1_UARTSEL_Pos)

Setting UART clock source as HIRC

Definition at line 99 of file clk.h.

◆ CLK_CLKSEL1_UARTSEL_HXT

#define CLK_CLKSEL1_UARTSEL_HXT   (0x0UL<<CLK_CLKSEL1_UARTSEL_Pos)

Setting UART clock source as HXT

Definition at line 96 of file clk.h.

◆ CLK_CLKSEL1_UARTSEL_LXT

#define CLK_CLKSEL1_UARTSEL_LXT   (0x2UL<<CLK_CLKSEL1_UARTSEL_Pos)

Setting UART clock source as LXT

Definition at line 98 of file clk.h.

◆ CLK_CLKSEL1_UARTSEL_PLL

#define CLK_CLKSEL1_UARTSEL_PLL   (0x1UL<<CLK_CLKSEL1_UARTSEL_Pos)

Setting UART clock source as PLL

Definition at line 97 of file clk.h.

◆ CLK_CLKSEL1_WDTSEL_HCLK_DIV2048

#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048   (0x2UL<<CLK_CLKSEL1_WDTSEL_Pos)

Setting WDT clock source as HCLK/2048

Definition at line 65 of file clk.h.

◆ CLK_CLKSEL1_WDTSEL_LIRC

#define CLK_CLKSEL1_WDTSEL_LIRC   (0x3UL<<CLK_CLKSEL1_WDTSEL_Pos)

Setting WDT clock source as LIRC

Definition at line 66 of file clk.h.

◆ CLK_CLKSEL1_WDTSEL_LXT

#define CLK_CLKSEL1_WDTSEL_LXT   (0x1UL<<CLK_CLKSEL1_WDTSEL_Pos)

Setting WDT clock source as LXT

Definition at line 64 of file clk.h.

◆ CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048

#define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048   (0x2UL<<CLK_CLKSEL1_WWDTSEL_Pos)

Setting WWDT clock source as HCLK/2048

Definition at line 106 of file clk.h.

◆ CLK_CLKSEL1_WWDTSEL_LIRC

#define CLK_CLKSEL1_WWDTSEL_LIRC   (0x3UL<<CLK_CLKSEL1_WWDTSEL_Pos)

Setting WWDT clock source as LIRC

Definition at line 107 of file clk.h.

◆ CLK_CLKSEL2_PWM0SEL_PCLK0

#define CLK_CLKSEL2_PWM0SEL_PCLK0   (0x1UL<<CLK_CLKSEL2_PWM0SEL_Pos)

Setting PWM0 clock source as PCLK0

Definition at line 114 of file clk.h.

◆ CLK_CLKSEL2_PWM0SEL_PLL

#define CLK_CLKSEL2_PWM0SEL_PLL   (0x0UL<<CLK_CLKSEL2_PWM0SEL_Pos)

Setting PWM0 clock source as PLL

Definition at line 113 of file clk.h.

◆ CLK_CLKSEL2_PWM1SEL_PCLK1

#define CLK_CLKSEL2_PWM1SEL_PCLK1   (0x1UL<<CLK_CLKSEL2_PWM1SEL_Pos)

Setting PWM1 clock source as PCLK1

Definition at line 117 of file clk.h.

◆ CLK_CLKSEL2_PWM1SEL_PLL

#define CLK_CLKSEL2_PWM1SEL_PLL   (0x0UL<<CLK_CLKSEL2_PWM1SEL_Pos)

Setting PWM1 clock source as PLL

Definition at line 116 of file clk.h.

◆ CLK_CLKSEL2_SPI0SEL_HIRC

#define CLK_CLKSEL2_SPI0SEL_HIRC   (0x3UL<<CLK_CLKSEL2_SPI0SEL_Pos)

Setting SPI0 clock source as HIRC

Definition at line 122 of file clk.h.

◆ CLK_CLKSEL2_SPI0SEL_HXT

#define CLK_CLKSEL2_SPI0SEL_HXT   (0x0UL<<CLK_CLKSEL2_SPI0SEL_Pos)

Setting SPI0 clock source as HXT

Definition at line 119 of file clk.h.

◆ CLK_CLKSEL2_SPI0SEL_PCLK0

#define CLK_CLKSEL2_SPI0SEL_PCLK0   (0x2UL<<CLK_CLKSEL2_SPI0SEL_Pos)

Setting SPI0 clock source as PCLK0

Definition at line 121 of file clk.h.

◆ CLK_CLKSEL2_SPI0SEL_PLL

#define CLK_CLKSEL2_SPI0SEL_PLL   (0x1UL<<CLK_CLKSEL2_SPI0SEL_Pos)

Setting SPI0 clock source as PLL

Definition at line 120 of file clk.h.

◆ CLK_CLKSEL2_SPI1SEL_HIRC

#define CLK_CLKSEL2_SPI1SEL_HIRC   (0x3UL<<CLK_CLKSEL2_SPI1SEL_Pos)

Setting SPI1 clock source as HIRC

Definition at line 127 of file clk.h.

◆ CLK_CLKSEL2_SPI1SEL_HXT

#define CLK_CLKSEL2_SPI1SEL_HXT   (0x0UL<<CLK_CLKSEL2_SPI1SEL_Pos)

Setting SPI1 clock source as HXT

Definition at line 124 of file clk.h.

◆ CLK_CLKSEL2_SPI1SEL_PCLK1

#define CLK_CLKSEL2_SPI1SEL_PCLK1   (0x2UL<<CLK_CLKSEL2_SPI1SEL_Pos)

Setting SPI1 clock source as PCLK1

Definition at line 126 of file clk.h.

◆ CLK_CLKSEL2_SPI1SEL_PLL

#define CLK_CLKSEL2_SPI1SEL_PLL   (0x1UL<<CLK_CLKSEL2_SPI1SEL_Pos)

Setting SPI1 clock source as PLL

Definition at line 125 of file clk.h.

◆ CLK_CLKSEL3_RTCSEL_LIRC

#define CLK_CLKSEL3_RTCSEL_LIRC   (0x1UL<<CLK_CLKSEL3_RTCSEL_Pos)

Setting RTC clock source as LIRC

Definition at line 139 of file clk.h.

◆ CLK_CLKSEL3_RTCSEL_LXT

#define CLK_CLKSEL3_RTCSEL_LXT   (0x0UL<<CLK_CLKSEL3_RTCSEL_Pos)

Setting RTC clock source as LXT

Definition at line 138 of file clk.h.

◆ CLK_CLKSEL3_SC0SEL_HIRC

#define CLK_CLKSEL3_SC0SEL_HIRC   (0x3UL<<CLK_CLKSEL3_SC0SEL_Pos)

Setting SC0 clock source as HIRC

Definition at line 136 of file clk.h.

◆ CLK_CLKSEL3_SC0SEL_HXT

#define CLK_CLKSEL3_SC0SEL_HXT   (0x0UL<<CLK_CLKSEL3_SC0SEL_Pos)

Setting SC0 clock source as HXT

Definition at line 133 of file clk.h.

◆ CLK_CLKSEL3_SC0SEL_PCLK0

#define CLK_CLKSEL3_SC0SEL_PCLK0   (0x2UL<<CLK_CLKSEL3_SC0SEL_Pos)

Setting SC0 clock source as PCLK0

Definition at line 135 of file clk.h.

◆ CLK_CLKSEL3_SC0SEL_PLL

#define CLK_CLKSEL3_SC0SEL_PLL   (0x1UL<<CLK_CLKSEL3_SC0SEL_Pos)

Setting SC0 clock source as PLL

Definition at line 134 of file clk.h.

◆ CLK_PLLCTL_144MHz_HXT

#define CLK_PLLCTL_144MHz_HXT   (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 48) | CLK_PLLCTL_NO_2)

Predefined PLLCTL setting for 144MHz PLL output with HXT(12MHz X'tal)

Definition at line 171 of file clk.h.

◆ CLK_PLLCTL_72MHz_HIRC

#define CLK_PLLCTL_72MHz_HIRC   (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 52) | CLK_PLLCTL_NO_4)

Predefined PLLCTL setting for 71.8848MHz PLL output with HIRC(22.1184MHz IRC)

Definition at line 172 of file clk.h.

◆ CLK_PLLCTL_72MHz_HXT

#define CLK_PLLCTL_72MHz_HXT   (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 48) | CLK_PLLCTL_NO_4)

Predefined PLLCTL setting for 72MHz PLL output with HXT(12MHz X'tal)

Definition at line 170 of file clk.h.

◆ CLK_PLLCTL_NF

#define CLK_PLLCTL_NF (   x)    ((x)-2)

x must be constant and 2 <= x <= 513. 200MHz < FIN*NF/NR < 500MHz. (FIN*NF/NR > 250MHz is preferred.)

Definition at line 163 of file clk.h.

◆ CLK_PLLCTL_NO_1

#define CLK_PLLCTL_NO_1   0x0000UL

For output divider is 1

Definition at line 166 of file clk.h.

◆ CLK_PLLCTL_NO_2

#define CLK_PLLCTL_NO_2   0x4000UL

For output divider is 2

Definition at line 167 of file clk.h.

◆ CLK_PLLCTL_NO_4

#define CLK_PLLCTL_NO_4   0xC000UL

For output divider is 4

Definition at line 168 of file clk.h.

◆ CLK_PLLCTL_NR

#define CLK_PLLCTL_NR (   x)    (((x)-2)<<9)

x must be constant and 2 <= x <= 33. 1.6MHz < FIN/NR < 16MHz

Definition at line 164 of file clk.h.

◆ CLK_PLLCTL_PLLSRC_HIRC

#define CLK_PLLCTL_PLLSRC_HIRC   0x00080000UL

For PLL clock source is HIRC. 3.2MHz < FIN < 150MHz

Definition at line 161 of file clk.h.

◆ CLK_PLLCTL_PLLSRC_HXT

#define CLK_PLLCTL_PLLSRC_HXT   0x00000000UL

For PLL clock source is HXT. 3.2MHz < FIN < 150MHz

Definition at line 160 of file clk.h.

◆ CLKO_MODULE

#define CLKO_MODULE
Value:
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(28)|\
#define MODULE_APBCLK_ENC(x)
Definition: clk.h:192
#define MODULE_CLKDIV_Pos_ENC(x)
Definition: clk.h:198
#define NA
Definition: clk.h:190
#define MODULE_CLKSEL_Msk_ENC(x)
Definition: clk.h:194
#define MODULE_CLKSEL_Pos_ENC(x)
Definition: clk.h:195
#define MODULE_CLKDIV_Msk_ENC(x)
Definition: clk.h:197
#define MODULE_IP_EN_Pos_ENC(x)
Definition: clk.h:199
#define CLK_APBCLK0_CLKOCKEN_Pos
Definition: M471M_R1_S.h:1516

CLKO Module

Definition at line 255 of file clk.h.

◆ CRC_MODULE

#define CRC_MODULE
Value:

CRC Module

Definition at line 221 of file clk.h.

◆ EADC_MODULE

#define EADC_MODULE
Value:

EADC Module

Definition at line 295 of file clk.h.

◆ EBI_MODULE

#define EBI_MODULE
Value:

EBI Module

Definition at line 213 of file clk.h.

◆ FREQ_125MHZ

#define FREQ_125MHZ   125000000

Definition at line 32 of file clk.h.

◆ FREQ_200MHZ

#define FREQ_200MHZ   200000000

Definition at line 33 of file clk.h.

◆ FREQ_250MHZ

#define FREQ_250MHZ   250000000

Definition at line 34 of file clk.h.

◆ FREQ_25MHZ

#define FREQ_25MHZ   25000000

Definition at line 29 of file clk.h.

◆ FREQ_500MHZ

#define FREQ_500MHZ   500000000

Definition at line 35 of file clk.h.

◆ FREQ_50MHZ

#define FREQ_50MHZ   50000000

Definition at line 30 of file clk.h.

◆ FREQ_72MHZ

#define FREQ_72MHZ   72000000

Definition at line 31 of file clk.h.

◆ I2C0_MODULE

#define I2C0_MODULE
Value:

I2C0 Module

Definition at line 259 of file clk.h.

◆ I2C1_MODULE

#define I2C1_MODULE
Value:

I2C1 Module

Definition at line 263 of file clk.h.

◆ ISP_MODULE

#define ISP_MODULE
Value:

ISP Module

Definition at line 209 of file clk.h.

◆ MODULE_APBCLK

#define MODULE_APBCLK (   x)    (((x) >>30) & 0x3)

Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1

Definition at line 181 of file clk.h.

◆ MODULE_APBCLK_ENC

#define MODULE_APBCLK_ENC (   x)    (((x) & 0x03) << 30)

MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1

Definition at line 192 of file clk.h.

◆ MODULE_CLKDIV

#define MODULE_CLKDIV (   x)    (((x) >>18) & 0x3)

Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV, 0x1:CLKDIV1

Definition at line 185 of file clk.h.

◆ MODULE_CLKDIV_ENC

#define MODULE_CLKDIV_ENC (   x)    (((x) & 0x03) << 18)

APBCLK CLKDIV on MODULE index, 0x0:CLKDIV, 0x1:CLKDIV1

Definition at line 196 of file clk.h.

◆ MODULE_CLKDIV_Msk

#define MODULE_CLKDIV_Msk (   x)    (((x) >>10) & 0xff)

Calculate CLKDIV mask offset on MODULE index

Definition at line 186 of file clk.h.

◆ MODULE_CLKDIV_Msk_ENC

#define MODULE_CLKDIV_Msk_ENC (   x)    (((x) & 0xff) << 10)

CLKDIV mask offset on MODULE index

Definition at line 197 of file clk.h.

◆ MODULE_CLKDIV_Pos

#define MODULE_CLKDIV_Pos (   x)    (((x) >>5 ) & 0x1f)

Calculate CLKDIV position offset on MODULE index

Definition at line 187 of file clk.h.

◆ MODULE_CLKDIV_Pos_ENC

#define MODULE_CLKDIV_Pos_ENC (   x)    (((x) & 0x1f) << 5)

CLKDIV position offset on MODULE index

Definition at line 198 of file clk.h.

◆ MODULE_CLKSEL

#define MODULE_CLKSEL (   x)    (((x) >>28) & 0x3)

Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3

Definition at line 182 of file clk.h.

◆ MODULE_CLKSEL_ENC

#define MODULE_CLKSEL_ENC (   x)    (((x) & 0x03) << 28)

CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3

Definition at line 193 of file clk.h.

◆ MODULE_CLKSEL_Msk

#define MODULE_CLKSEL_Msk (   x)    (((x) >>25) & 0x7)

Calculate CLKSEL mask offset on MODULE index

Definition at line 183 of file clk.h.

◆ MODULE_CLKSEL_Msk_ENC

#define MODULE_CLKSEL_Msk_ENC (   x)    (((x) & 0x07) << 25)

CLKSEL mask offset on MODULE index

Definition at line 194 of file clk.h.

◆ MODULE_CLKSEL_Pos

#define MODULE_CLKSEL_Pos (   x)    (((x) >>20) & 0x1f)

Calculate CLKSEL position offset on MODULE index

Definition at line 184 of file clk.h.

◆ MODULE_CLKSEL_Pos_ENC

#define MODULE_CLKSEL_Pos_ENC (   x)    (((x) & 0x1f) << 20)

CLKSEL position offset on MODULE index

Definition at line 195 of file clk.h.

◆ MODULE_IP_EN_Pos

#define MODULE_IP_EN_Pos (   x)    (((x) >>0 ) & 0x1f)

Calculate APBCLK offset on MODULE index

Definition at line 188 of file clk.h.

◆ MODULE_IP_EN_Pos_ENC

#define MODULE_IP_EN_Pos_ENC (   x)    (((x) & 0x1f) << 0)

AHBCLK/APBCLK offset on MODULE index

Definition at line 199 of file clk.h.

◆ MODULE_NoMsk

#define MODULE_NoMsk   0x0

Not mask on MODULE index

Definition at line 189 of file clk.h.

◆ NA

#define NA   MODULE_NoMsk

Not Available

Definition at line 190 of file clk.h.

◆ PDMA_MODULE

#define PDMA_MODULE
Value:

PDMA Module

Definition at line 205 of file clk.h.

◆ PWM0_MODULE

#define PWM0_MODULE
Value:

PWM0 Module

Definition at line 305 of file clk.h.

◆ PWM1_MODULE

#define PWM1_MODULE
Value:

PWM1 Module

Definition at line 309 of file clk.h.

◆ RTC_MODULE

#define RTC_MODULE
Value:

RTC Module

Definition at line 235 of file clk.h.

◆ SC0_MODULE

#define SC0_MODULE
Value:
MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 0)|\
MODULE_CLKDIV_ENC( 1)|MODULE_CLKDIV_Msk_ENC(0xFF)|MODULE_CLKDIV_Pos_ENC( 0))
#define CLK_APBCLK1_SC0CKEN_Pos
Definition: M471M_R1_S.h:1549

SC0 Module

Definition at line 301 of file clk.h.

◆ SPI0_MODULE

#define SPI0_MODULE
Value:

SPI0 Module

Definition at line 267 of file clk.h.

◆ SPI1_MODULE

#define SPI1_MODULE
Value:

SPI1 Module

Definition at line 271 of file clk.h.

◆ TMR0_MODULE

#define TMR0_MODULE
Value:

TMR0 Module

Definition at line 239 of file clk.h.

◆ TMR1_MODULE

#define TMR1_MODULE
Value:

TMR1 Module

Definition at line 243 of file clk.h.

◆ TMR2_MODULE

#define TMR2_MODULE
Value:

TMR2 Module

Definition at line 247 of file clk.h.

◆ TMR3_MODULE

#define TMR3_MODULE
Value:

TMR3 Module

Definition at line 251 of file clk.h.

◆ UART0_MODULE

#define UART0_MODULE
Value:
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(24)|\
MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 8))
#define CLK_APBCLK0_UART0CKEN_Pos
Definition: M471M_R1_S.h:1531

UART0 Module

Definition at line 275 of file clk.h.

◆ UART1_MODULE

#define UART1_MODULE
Value:
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(24)|\
MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 8))
#define CLK_APBCLK0_UART1CKEN_Pos
Definition: M471M_R1_S.h:1534

UART1 Module

Definition at line 279 of file clk.h.

◆ UART2_MODULE

#define UART2_MODULE
Value:
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(24)|\
MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 8))
#define CLK_APBCLK0_UART2CKEN_Pos
Definition: M471M_R1_S.h:1537

UART2 Module

Definition at line 283 of file clk.h.

◆ UART3_MODULE

#define UART3_MODULE
Value:
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(24)|\
MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 8))
#define CLK_APBCLK0_UART3CKEN_Pos
Definition: M471M_R1_S.h:1540

UART3 Module

Definition at line 287 of file clk.h.

◆ USBD_MODULE

#define USBD_MODULE
Value:

USBD Module

Definition at line 291 of file clk.h.

◆ USBH_MODULE

#define USBH_MODULE
Value:

USBH Module

Definition at line 217 of file clk.h.

◆ WDT_MODULE

#define WDT_MODULE
Value:

WDT Module

Definition at line 227 of file clk.h.

◆ WWDT_MODULE

#define WWDT_MODULE
Value:

WWDT Module

Definition at line 231 of file clk.h.