M471M/R1/S BSP V3.01.000
The Board Support Package for M4521
spi.h
Go to the documentation of this file.
1/**************************************************************************/
8#ifndef __SPI_H__
9#define __SPI_H__
10
11/*---------------------------------------------------------------------------------------------------------*/
12/* Include related headers */
13/*---------------------------------------------------------------------------------------------------------*/
14#include "NuMicro.h"
15
16#ifdef __cplusplus
17extern "C"
18{
19#endif
20
21
34#define SPI_MODE_0 (SPI_CTL_TXNEG_Msk)
35#define SPI_MODE_1 (SPI_CTL_RXNEG_Msk)
36#define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk)
37#define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk)
39#define SPI_SLAVE (SPI_CTL_SLAVE_Msk)
40#define SPI_MASTER (0x0)
42#define SPI_SS (SPI_SSCTL_SS_Msk)
43#define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk)
44#define SPI_SS_ACTIVE_LOW (0x0)
46/* SPI Interrupt Mask */
47#define SPI_UNIT_INT_MASK (0x001)
48#define SPI_SSACT_INT_MASK (0x002)
49#define SPI_SSINACT_INT_MASK (0x004)
50#define SPI_SLVUR_INT_MASK (0x008)
51#define SPI_SLVBE_INT_MASK (0x010)
52#define SPI_SLVTO_INT_MASK (0x020)
53#define SPI_TXUF_INT_MASK (0x040)
54#define SPI_FIFO_TXTH_INT_MASK (0x080)
55#define SPI_FIFO_RXTH_INT_MASK (0x100)
56#define SPI_FIFO_RXOV_INT_MASK (0x200)
57#define SPI_FIFO_RXTO_INT_MASK (0x400)
59/* SPI Status Mask */
60#define SPI_BUSY_MASK (0x01)
61#define SPI_RX_EMPTY_MASK (0x02)
62#define SPI_RX_FULL_MASK (0x04)
63#define SPI_TX_EMPTY_MASK (0x08)
64#define SPI_TX_FULL_MASK (0x10)
65#define SPI_TXRX_RESET_MASK (0x20)
66#define SPI_SPIEN_STS_MASK (0x40)
67#define SPI_SSLINE_STS_MASK (0x80) /* end of group SPI_EXPORTED_CONSTANTS */
72
73
84#define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ((spi)->STATUS = SPI_STATUS_UNITIF_Msk)
85
92#define SPI_DISABLE_2BIT_MODE(spi) ((spi)->CTL &= ~SPI_CTL_TWOBIT_Msk)
93
100#define SPI_DISABLE_3WIRE_MODE(spi) ((spi)->SSCTL &= ~SPI_SSCTL_SLV3WIRE_Msk)
101
108#define SPI_DISABLE_DUAL_MODE(spi) ((spi)->CTL &= ~SPI_CTL_DUALIOEN_Msk)
109
116#define SPI_DISABLE_QUAD_MODE(spi) ((spi)->CTL &= ~SPI_CTL_QUADIOEN_Msk)
117
124#define SPI_ENABLE_2BIT_MODE(spi) ((spi)->CTL |= SPI_CTL_TWOBIT_Msk)
125
132#define SPI_ENABLE_3WIRE_MODE(spi) ((spi)->SSCTL |= SPI_SSCTL_SLV3WIRE_Msk)
133
140#define SPI_ENABLE_DUAL_INPUT_MODE(spi) ((spi)->CTL = ((spi)->CTL & (~SPI_CTL_QDIODIR_Msk)) | SPI_CTL_DUALIOEN_Msk)
141
148#define SPI_ENABLE_DUAL_OUTPUT_MODE(spi) ((spi)->CTL |= (SPI_CTL_QDIODIR_Msk | SPI_CTL_DUALIOEN_Msk))
149
156#define SPI_ENABLE_QUAD_INPUT_MODE(spi) ((spi)->CTL = ((spi)->CTL & (~SPI_CTL_QDIODIR_Msk)) | SPI_CTL_QUADIOEN_Msk)
157
164#define SPI_ENABLE_QUAD_OUTPUT_MODE(spi) ((spi)->CTL |= (SPI_CTL_QDIODIR_Msk | SPI_CTL_QUADIOEN_Msk))
165
172#define SPI_TRIGGER_RX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk)
173
180#define SPI_TRIGGER_TX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk)
181
188#define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
189
196#define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
197
204#define SPI_GET_RX_FIFO_COUNT(spi) (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos)
205
213#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk)>>SPI_STATUS_RXEMPTY_Pos)
214
222#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk)>>SPI_STATUS_TXEMPTY_Pos)
223
231#define SPI_GET_TX_FIFO_FULL_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXFULL_Msk)>>SPI_STATUS_TXFULL_Pos)
232
239#define SPI_READ_RX(spi) ((spi)->RX)
240
248#define SPI_WRITE_TX(spi, u32TxData) ((spi)->TX = (u32TxData))
249
256#define SPI_SET_SS_HIGH(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))
257
264#define SPI_SET_SS_LOW(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk)
265
272#define SPI_ENABLE_BYTE_REORDER(spi) ((spi)->CTL |= SPI_CTL_REORDER_Msk)
273
280#define SPI_DISABLE_BYTE_REORDER(spi) ((spi)->CTL &= ~SPI_CTL_REORDER_Msk)
281
290#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos))
291
298#define SPI_SET_LSB_FIRST(spi) ((spi)->CTL |= SPI_CTL_LSB_Msk)
299
306#define SPI_SET_MSB_FIRST(spi) ((spi)->CTL &= ~SPI_CTL_LSB_Msk)
307
315#define SPI_SET_DATA_WIDTH(spi, u32Width) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << SPI_CTL_DWIDTH_Pos))
316
324#define SPI_IS_BUSY(spi) ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk)>>SPI_STATUS_BUSY_Pos )
325
332#define SPI_ENABLE(spi) ((spi)->CTL |= SPI_CTL_SPIEN_Msk)
333
340#define SPI_DISABLE(spi) ((spi)->CTL &= ~SPI_CTL_SPIEN_Msk)
341
342
343/* Function prototype declaration */
344uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
345void SPI_Close(SPI_T *spi);
346void SPI_ClearRxFIFO(SPI_T *spi);
347void SPI_ClearTxFIFO(SPI_T *spi);
348void SPI_DisableAutoSS(SPI_T *spi);
349void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
350uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
351void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
352uint32_t SPI_GetBusClock(SPI_T *spi);
353void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
354void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
355uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask);
356void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask);
357uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask);
358
359 /* end of group SPI_EXPORTED_FUNCTIONS */
361 /* end of group SPI_Driver */
363 /* end of group Standard_Driver */
365
366#ifdef __cplusplus
367}
368#endif
369
370#endif //__SPI_H__
371
NuMicro peripheral access layer header file.
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
Disable interrupt function.
Definition: spi.c:520
uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask)
Get interrupt flag.
Definition: spi.c:588
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
Enable interrupt function.
Definition: spi.c:452
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
Enable the automatic slave selection function.
Definition: spi.c:249
void SPI_DisableAutoSS(SPI_T *spi)
Disable the automatic slave selection function.
Definition: spi.c:235
void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask)
Clear interrupt flag.
Definition: spi.c:658
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
Set the SPI bus clock.
Definition: spi.c:266
void SPI_Close(SPI_T *spi)
Disable SPI controller.
Definition: spi.c:190
void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
Configure FIFO threshold setting.
Definition: spi.c:367
uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask)
Get SPI status.
Definition: spi.c:706
void SPI_ClearTxFIFO(SPI_T *spi)
Clear TX FIFO buffer.
Definition: spi.c:224
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
This function make SPI module be ready to transfer.
Definition: spi.c:41
uint32_t SPI_GetBusClock(SPI_T *spi)
Get the actual frequency of SPI bus clock. Only available in Master mode.
Definition: spi.c:380
void SPI_ClearRxFIFO(SPI_T *spi)
Clear RX FIFO buffer.
Definition: spi.c:212