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M471M/R1/S BSP V3.01.000
The Board Support Package for M4521
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Modules | |
Peripheral Declaration | |
#define AHBPERIPH_BASE PERIPH_BASE |
Definition at line 13762 of file M471M_R1_S.h.
#define APBPERIPH_BASE (PERIPH_BASE + 0x00040000) |
AHB peripherals
Definition at line 13765 of file M471M_R1_S.h.
#define CLK_BASE (AHBPERIPH_BASE + 0x00200) |
Definition at line 13767 of file M471M_R1_S.h.
#define CRC_BASE (AHBPERIPH_BASE + 0x31000) |
APB0 peripherals
Definition at line 13784 of file M471M_R1_S.h.
#define EADC0_BASE (APBPERIPH_BASE + 0x03000) |
Definition at line 13798 of file M471M_R1_S.h.
#define EBI_BASE (AHBPERIPH_BASE + 0x10000) |
Definition at line 13781 of file M471M_R1_S.h.
#define FMC_BASE (AHBPERIPH_BASE + 0x0C000) |
Definition at line 13780 of file M471M_R1_S.h.
#define GCR_BASE (AHBPERIPH_BASE + 0x00000) |
Definition at line 13766 of file M471M_R1_S.h.
#define GPIO_BASE (AHBPERIPH_BASE + 0x04000) |
Definition at line 13769 of file M471M_R1_S.h.
#define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440) |
Definition at line 13776 of file M471M_R1_S.h.
#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800) |
Definition at line 13777 of file M471M_R1_S.h.
#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000) |
Definition at line 13770 of file M471M_R1_S.h.
#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040) |
Definition at line 13771 of file M471M_R1_S.h.
#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080) |
Definition at line 13772 of file M471M_R1_S.h.
#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0) |
Definition at line 13773 of file M471M_R1_S.h.
#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100) |
Definition at line 13774 of file M471M_R1_S.h.
#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140) |
Definition at line 13775 of file M471M_R1_S.h.
#define I2C0_BASE (APBPERIPH_BASE + 0x40000) |
Definition at line 13792 of file M471M_R1_S.h.
#define I2C1_BASE (APBPERIPH_BASE + 0x41000) |
Definition at line 13804 of file M471M_R1_S.h.
#define INT_BASE (AHBPERIPH_BASE + 0x00300) |
Definition at line 13768 of file M471M_R1_S.h.
#define PDMA_BASE (AHBPERIPH_BASE + 0x08000) |
Definition at line 13778 of file M471M_R1_S.h.
#define PERIPH_BASE (0x40000000UL) |
(Peripheral) Base Address
Definition at line 13758 of file M471M_R1_S.h.
#define PWM0_BASE (APBPERIPH_BASE + 0x18000) |
Definition at line 13788 of file M471M_R1_S.h.
#define PWM1_BASE (APBPERIPH_BASE + 0x19000) |
Definition at line 13800 of file M471M_R1_S.h.
#define RTC_BASE (APBPERIPH_BASE + 0x01000) |
Definition at line 13797 of file M471M_R1_S.h.
#define SC0_BASE (APBPERIPH_BASE + 0x50000) |
Definition at line 13793 of file M471M_R1_S.h.
#define SPI0_BASE (APBPERIPH_BASE + 0x20000) |
Definition at line 13789 of file M471M_R1_S.h.
#define SPI1_BASE (APBPERIPH_BASE + 0x21000) |
Definition at line 13801 of file M471M_R1_S.h.
#define SRAM_BASE (0x20000000UL) |
(SRAM ) Base Address
Definition at line 13757 of file M471M_R1_S.h.
#define TMR01_BASE (APBPERIPH_BASE + 0x10000) |
Definition at line 13787 of file M471M_R1_S.h.
#define TMR23_BASE (APBPERIPH_BASE + 0x11000) |
Definition at line 13799 of file M471M_R1_S.h.
#define UART0_BASE (APBPERIPH_BASE + 0x30000) |
Definition at line 13790 of file M471M_R1_S.h.
#define UART1_BASE (APBPERIPH_BASE + 0x31000) |
Definition at line 13802 of file M471M_R1_S.h.
#define UART2_BASE (APBPERIPH_BASE + 0x32000) |
Definition at line 13791 of file M471M_R1_S.h.
#define UART3_BASE (APBPERIPH_BASE + 0x33000) |
Definition at line 13803 of file M471M_R1_S.h.
#define USBD_BASE (APBPERIPH_BASE + 0x80000) |
APB1 peripherals
Definition at line 13796 of file M471M_R1_S.h.
#define USBH_BASE (AHBPERIPH_BASE + 0x09000) |
Definition at line 13779 of file M471M_R1_S.h.
#define WDT_BASE (APBPERIPH_BASE + 0x00000) |
Definition at line 13785 of file M471M_R1_S.h.
#define WWDT_BASE (APBPERIPH_BASE + 0x00100) |
Definition at line 13786 of file M471M_R1_S.h.