M471M/R1/S BSP V3.01.000
The Board Support Package for M4521
Macros | Typedefs | Enumerator | Variables
Peripheral Declaration
Collaboration diagram for Peripheral Declaration:

Macros

#define SYS   ((SYS_T *) GCR_BASE)
 
#define SYSINT   ((SYS_INT_T *) INT_BASE)
 
#define CLK   ((CLK_T *) CLK_BASE)
 
#define PA   ((GPIO_T *) GPIOA_BASE)
 
#define PB   ((GPIO_T *) GPIOB_BASE)
 
#define PC   ((GPIO_T *) GPIOC_BASE)
 
#define PD   ((GPIO_T *) GPIOD_BASE)
 
#define PE   ((GPIO_T *) GPIOE_BASE)
 
#define PF   ((GPIO_T *) GPIOF_BASE)
 
#define GPIO   ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE)
 
#define PDMA   ((PDMA_T *) PDMA_BASE)
 
#define USBH   ((USBH_T *) USBH_BASE)
 
#define FMC   ((FMC_T *) FMC_BASE)
 
#define EBI   ((EBI_T *) EBI_BASE)
 
#define CRC   ((CRC_T *) CRC_BASE)
 
#define WDT   ((WDT_T *) WDT_BASE)
 
#define WWDT   ((WWDT_T *) WWDT_BASE)
 
#define RTC   ((RTC_T *) RTC_BASE)
 
#define EADC   ((EADC_T *) EADC0_BASE)
 
#define USBD   ((USBD_T *) USBD_BASE)
 
#define TIMER0   ((TIMER_T *) TMR01_BASE)
 
#define TIMER1   ((TIMER_T *) (TMR01_BASE + 0x20))
 
#define TIMER2   ((TIMER_T *) TMR23_BASE)
 
#define TIMER3   ((TIMER_T *) (TMR23_BASE + 0x20))
 
#define PWM0   ((PWM_T *) PWM0_BASE)
 
#define PWM1   ((PWM_T *) PWM1_BASE)
 
#define SPI0   ((SPI_T *) SPI0_BASE)
 
#define SPI1   ((SPI_T *) SPI1_BASE)
 
#define UART0   ((UART_T *) UART0_BASE)
 
#define UART1   ((UART_T *) UART1_BASE)
 
#define UART2   ((UART_T *) UART2_BASE)
 
#define UART3   ((UART_T *) UART3_BASE)
 
#define I2C0   ((I2C_T *) I2C0_BASE)
 
#define I2C1   ((I2C_T *) I2C1_BASE)
 
#define SC0   ((SC_T *) SC0_BASE)
 
#define BIT0   0x00000001
 
#define BIT1   0x00000002
 
#define BIT2   0x00000004
 
#define BIT3   0x00000008
 
#define BIT4   0x00000010
 
#define BIT5   0x00000020
 
#define BIT6   0x00000040
 
#define BIT7   0x00000080
 
#define BIT8   0x00000100
 
#define BIT9   0x00000200
 
#define BIT10   0x00000400
 
#define BIT11   0x00000800
 
#define BIT12   0x00001000
 
#define BIT13   0x00002000
 
#define BIT14   0x00004000
 
#define BIT15   0x00008000
 
#define BIT16   0x00010000
 
#define BIT17   0x00020000
 
#define BIT18   0x00040000
 
#define BIT19   0x00080000
 
#define BIT20   0x00100000
 
#define BIT21   0x00200000
 
#define BIT22   0x00400000
 
#define BIT23   0x00800000
 
#define BIT24   0x01000000
 
#define BIT25   0x02000000
 
#define BIT26   0x04000000
 
#define BIT27   0x08000000
 
#define BIT28   0x10000000
 
#define BIT29   0x20000000
 
#define BIT30   0x40000000
 
#define BIT31   0x80000000
 
#define BYTE0_Msk   (0x000000FF)
 
#define BYTE1_Msk   (0x0000FF00)
 
#define BYTE2_Msk   (0x00FF0000)
 
#define BYTE3_Msk   (0xFF000000)
 
#define _GET_BYTE0(u32Param)   (((u32Param) & BYTE0_Msk) )
 
#define _GET_BYTE1(u32Param)   (((u32Param) & BYTE1_Msk) >> 8)
 
#define _GET_BYTE2(u32Param)   (((u32Param) & BYTE2_Msk) >> 16)
 
#define _GET_BYTE3(u32Param)   (((u32Param) & BYTE3_Msk) >> 24)
 
#define TRUE   1
 
#define FALSE   0
 
#define NULL   0
 
#define M8(adr)   (*((vu8 *) (adr)))
 
#define M16(adr)   (*((vu16 *) (adr)))
 
#define M32(adr)   (*((vu32 *) (adr)))
 
#define outpw(port, value)   (*((volatile unsigned int *)(port))=(value))
 
#define inpw(port)   (*((volatile unsigned int *)(port)))
 
#define outpb(port, value)   (*((volatile unsigned char *)(port))=(value))
 
#define inpb(port)   (*((volatile unsigned char *)(port)))
 
#define outps(port, value)   (*((volatile unsigned short *)(port))=(value))
 
#define inps(port)   (*((volatile unsigned short *)(port)))
 
#define outp32(port, value)   (*((volatile unsigned int *)(port))=(value))
 
#define inp32(port)   (*((volatile unsigned int *)(port)))
 
#define outp8(port, value)   (*((volatile unsigned char *)(port))=(value))
 
#define inp8(port)   (*((volatile unsigned char *)(port)))
 
#define outp16(port, value)   (*((volatile unsigned short *)(port))=(value))
 
#define inp16(port)   (*((volatile unsigned short *)(port)))
 

Typedefs

typedef volatile unsigned char vu8
 
typedef volatile unsigned long vu32
 
typedef volatile unsigned short vu16
 

Variables

__I uint32_t EADC_T::DAT [19]
 
__I uint32_t EADC_T::CURDAT
 
__IO uint32_t EADC_T::CTL
 
__O uint32_t EADC_T::SWTRG
 
__IO uint32_t EADC_T::PENDSTS
 
__IO uint32_t EADC_T::OVSTS
 
__I uint32_t EADC_T::RESERVE0 [8]
 
__IO uint32_t EADC_T::SCTL [19]
 
__I uint32_t EADC_T::RESERVE1 [1]
 
__IO uint32_t EADC_T::INTSRC [4]
 
__IO uint32_t EADC_T::CMP [4]
 
__I uint32_t EADC_T::STATUS0
 
__I uint32_t EADC_T::STATUS1
 
__IO uint32_t EADC_T::STATUS2
 
__I uint32_t EADC_T::STATUS3
 
__I uint32_t EADC_T::DDAT [4]
 
__IO uint32_t CLK_T::PWRCTL
 
__IO uint32_t CLK_T::AHBCLK
 
__IO uint32_t CLK_T::APBCLK0
 
__IO uint32_t CLK_T::APBCLK1
 
__IO uint32_t CLK_T::CLKSEL0
 
__IO uint32_t CLK_T::CLKSEL1
 
__IO uint32_t CLK_T::CLKSEL2
 
__IO uint32_t CLK_T::CLKSEL3
 
__IO uint32_t CLK_T::CLKDIV0
 
__IO uint32_t CLK_T::CLKDIV1
 
__I uint32_t CLK_T::RESERVE0 [6]
 
__IO uint32_t CLK_T::PLLCTL
 
__I uint32_t CLK_T::RESERVE1 [3]
 
__I uint32_t CLK_T::STATUS
 
__I uint32_t CLK_T::RESERVE2 [3]
 
__IO uint32_t CLK_T::CLKOCTL
 
__I uint32_t CLK_T::RESERVE3 [3]
 
__IO uint32_t CLK_T::CLKDCTL
 
__IO uint32_t CLK_T::CLKDSTS
 
__IO uint32_t CLK_T::CDUPB
 
__IO uint32_t CLK_T::CDLOWB
 
__IO uint32_t CRC_T::CTL
 
__IO uint32_t CRC_T::DAT
 
__IO uint32_t CRC_T::SEED
 
__I uint32_t CRC_T::CHECKSUM
 
__IO uint32_t EBI_T::CTL0
 
__IO uint32_t EBI_T::TCTL0
 
__I uint32_t EBI_T::RESERVE0 [2]
 
__IO uint32_t EBI_T::CTL1
 
__IO uint32_t EBI_T::TCTL1
 
__IO uint32_t FMC_T::ISPCTL
 
__IO uint32_t FMC_T::ISPADDR
 
__IO uint32_t FMC_T::ISPDAT
 
__IO uint32_t FMC_T::ISPCMD
 
__IO uint32_t FMC_T::ISPTRG
 
__I uint32_t FMC_T::DFBA
 
__IO uint32_t FMC_T::FTCTL
 
__I uint32_t FMC_T::RESERVE0 [9]
 
__I uint32_t FMC_T::ISPSTS
 
__I uint32_t FMC_T::RESERVE1 [15]
 
__IO uint32_t FMC_T::MPDAT0
 
__IO uint32_t FMC_T::MPDAT1
 
__IO uint32_t FMC_T::MPDAT2
 
__IO uint32_t FMC_T::MPDAT3
 
__I uint32_t FMC_T::RESERVE2 [12]
 
__I uint32_t FMC_T::MPSTS
 
__I uint32_t FMC_T::MPADDR
 
__IO uint32_t GPIO_T::MODE
 
__IO uint32_t GPIO_T::DINOFF
 
__IO uint32_t GPIO_T::DOUT
 
__IO uint32_t GPIO_T::DATMSK
 
__I uint32_t GPIO_T::PIN
 
__IO uint32_t GPIO_T::DBEN
 
__IO uint32_t GPIO_T::INTTYPE
 
__IO uint32_t GPIO_T::INTEN
 
__IO uint32_t GPIO_T::INTSRC
 
__IO uint32_t GPIO_T::SMTEN
 
__IO uint32_t GPIO_T::SLEWCTL
 
__IO uint32_t GPIO_T::DRVCTL
 
__IO uint32_t GPIO_DBCTL_T::DBCTL
 
__IO uint32_t I2C_T::CTL
 
__IO uint32_t I2C_T::ADDR0
 
__IO uint32_t I2C_T::DAT
 
__I uint32_t I2C_T::STATUS
 
__IO uint32_t I2C_T::CLKDIV
 
__IO uint32_t I2C_T::TOCTL
 
__IO uint32_t I2C_T::ADDR1
 
__IO uint32_t I2C_T::ADDR2
 
__IO uint32_t I2C_T::ADDR3
 
__IO uint32_t I2C_T::ADDRMSK0
 
__IO uint32_t I2C_T::ADDRMSK1
 
__IO uint32_t I2C_T::ADDRMSK2
 
__IO uint32_t I2C_T::ADDRMSK3
 
__I uint32_t I2C_T::RESERVE0 [2]
 
__IO uint32_t I2C_T::WKCTL
 
__IO uint32_t I2C_T::WKSTS
 
__IO uint32_t I2C_T::BUSCTL
 
__IO uint32_t I2C_T::BUSTCTL
 
__IO uint32_t I2C_T::BUSSTS
 
__IO uint32_t I2C_T::PKTSIZE
 
__I uint32_t I2C_T::PKTCRC
 
__IO uint32_t I2C_T::BUSTOUT
 
__IO uint32_t I2C_T::CLKTOUT
 
__IO uint32_t DSCT_T::CTL
 
__IO uint32_t DSCT_T::SA
 
__IO uint32_t DSCT_T::DA
 
__IO uint32_t DSCT_T::NEXT
 
DSCT_T PDMA_T::DSCT [12]
 
__I uint32_t PDMA_T::CURSCAT [12]
 
__I uint32_t PDMA_T::RESERVE0 [196]
 
__IO uint32_t PDMA_T::CHCTL
 
__O uint32_t PDMA_T::STOP
 
__O uint32_t PDMA_T::SWREQ
 
__I uint32_t PDMA_T::TRGSTS
 
__IO uint32_t PDMA_T::PRISET
 
__O uint32_t PDMA_T::PRICLR
 
__IO uint32_t PDMA_T::INTEN
 
__IO uint32_t PDMA_T::INTSTS
 
__IO uint32_t PDMA_T::ABTSTS
 
__IO uint32_t PDMA_T::TDSTS
 
__IO uint32_t PDMA_T::SCATSTS
 
__I uint32_t PDMA_T::TACTSTS
 
__I uint32_t PDMA_T::RESERVE1 [1]
 
__IO uint32_t PDMA_T::TOUTEN
 
__IO uint32_t PDMA_T::TOUTIEN
 
__IO uint32_t PDMA_T::SCATBA
 
__IO uint32_t PDMA_T::TOC0_1
 
__IO uint32_t PDMA_T::TOC2_3
 
__IO uint32_t PDMA_T::TOC4_5
 
__IO uint32_t PDMA_T::TOC6_7
 
__I uint32_t PDMA_T::RESERVE2 [12]
 
__IO uint32_t PDMA_T::REQSEL0_3
 
__IO uint32_t PDMA_T::REQSEL4_7
 
__IO uint32_t PDMA_T::REQSEL8_11
 
__IO uint32_t PWM_T::CTL0
 
__IO uint32_t PWM_T::CTL1
 
__IO uint32_t PWM_T::SYNC
 
__IO uint32_t PWM_T::SWSYNC
 
__IO uint32_t PWM_T::CLKSRC
 
__IO uint32_t PWM_T::CLKPSC0_1
 
__IO uint32_t PWM_T::CLKPSC2_3
 
__IO uint32_t PWM_T::CLKPSC4_5
 
__IO uint32_t PWM_T::CNTEN
 
__IO uint32_t PWM_T::CNTCLR
 
__IO uint32_t PWM_T::LOAD
 
__I uint32_t PWM_T::RESERVE0 [1]
 
__IO uint32_t PWM_T::PERIOD [6]
 
__I uint32_t PWM_T::RESERVE1 [2]
 
__IO uint32_t PWM_T::CMPDAT [6]
 
__I uint32_t PWM_T::RESERVE2 [2]
 
__IO uint32_t PWM_T::DTCTL0_1
 
__IO uint32_t PWM_T::DTCTL2_3
 
__IO uint32_t PWM_T::DTCTL4_5
 
__I uint32_t PWM_T::RESERVE3 [1]
 
__IO uint32_t PWM_T::PHS0_1
 
__IO uint32_t PWM_T::PHS2_3
 
__IO uint32_t PWM_T::PHS4_5
 
__I uint32_t PWM_T::RESERVE4 [1]
 
__I uint32_t PWM_T::CNT [6]
 
__I uint32_t PWM_T::RESERVE5 [2]
 
__IO uint32_t PWM_T::WGCTL0
 
__IO uint32_t PWM_T::WGCTL1
 
__IO uint32_t PWM_T::MSKEN
 
__IO uint32_t PWM_T::MSK
 
__IO uint32_t PWM_T::BNF
 
__IO uint32_t PWM_T::FAILBRK
 
__IO uint32_t PWM_T::BRKCTL0_1
 
__IO uint32_t PWM_T::BRKCTL2_3
 
__IO uint32_t PWM_T::BRKCTL4_5
 
__IO uint32_t PWM_T::POLCTL
 
__IO uint32_t PWM_T::POEN
 
__O uint32_t PWM_T::SWBRK
 
__IO uint32_t PWM_T::INTEN0
 
__IO uint32_t PWM_T::INTEN1
 
__IO uint32_t PWM_T::INTSTS0
 
__IO uint32_t PWM_T::INTSTS1
 
__IO uint32_t PWM_T::IFA
 
__IO uint32_t PWM_T::RESERVE6 [1]
 
__IO uint32_t PWM_T::EADCTS0
 
__IO uint32_t PWM_T::EADCTS1
 
__IO uint32_t PWM_T::FTCMPDAT0_1
 
__IO uint32_t PWM_T::FTCMPDAT2_3
 
__IO uint32_t PWM_T::FTCMPDAT4_5
 
__I uint32_t PWM_T::RESERVE7 [1]
 
__IO uint32_t PWM_T::SSCTL
 
__O uint32_t PWM_T::SSTRG
 
__I uint32_t PWM_T::RESERVE8 [2]
 
__IO uint32_t PWM_T::STATUS
 
__I uint32_t PWM_T::RESERVE9 [55]
 
__IO uint32_t PWM_T::CAPINEN
 
__IO uint32_t PWM_T::CAPCTL
 
__I uint32_t PWM_T::CAPSTS
 
__I uint32_t PWM_T::RCAPDAT0
 
__I uint32_t PWM_T::FCAPDAT0
 
__I uint32_t PWM_T::RCAPDAT1
 
__I uint32_t PWM_T::FCAPDAT1
 
__I uint32_t PWM_T::RCAPDAT2
 
__I uint32_t PWM_T::FCAPDAT2
 
__I uint32_t PWM_T::RCAPDAT3
 
__I uint32_t PWM_T::FCAPDAT3
 
__I uint32_t PWM_T::RCAPDAT4
 
__I uint32_t PWM_T::FCAPDAT4
 
__I uint32_t PWM_T::RCAPDAT5
 
__I uint32_t PWM_T::FCAPDAT5
 
__IO uint32_t PWM_T::PDMACTL
 
__I uint32_t PWM_T::PDMACAP0_1
 
__I uint32_t PWM_T::PDMACAP2_3
 
__I uint32_t PWM_T::PDMACAP4_5
 
__I uint32_t PWM_T::RESERVE10 [1]
 
__IO uint32_t PWM_T::CAPIEN
 
__IO uint32_t PWM_T::CAPIF
 
__I uint32_t PWM_T::RESERVE11 [43]
 
__I uint32_t PWM_T::PBUF [6]
 
__I uint32_t PWM_T::CMPBUF [6]
 
__I uint32_t PWM_T::RESERVE12 [3]
 
__I uint32_t PWM_T::FTCBUF0_1
 
__I uint32_t PWM_T::FTCBUF2_3
 
__I uint32_t PWM_T::FTCBUF4_5
 
__IO uint32_t PWM_T::FTCI
 
__IO uint32_t RTC_T::INIT
 
__O uint32_t RTC_T::RWEN
 
__IO uint32_t RTC_T::FREQADJ
 
__IO uint32_t RTC_T::TIME
 
__IO uint32_t RTC_T::CAL
 
__IO uint32_t RTC_T::CLKFMT
 
__IO uint32_t RTC_T::WEEKDAY
 
__IO uint32_t RTC_T::TALM
 
__IO uint32_t RTC_T::CALM
 
__I uint32_t RTC_T::LEAPYEAR
 
__IO uint32_t RTC_T::INTEN
 
__IO uint32_t RTC_T::INTSTS
 
__IO uint32_t RTC_T::TICK
 
__IO uint32_t RTC_T::TAMSK
 
__IO uint32_t RTC_T::CAMSK
 
__IO uint32_t RTC_T::SPRCTL
 
__IO uint32_t RTC_T::SPR [20]
 
__I uint32_t RTC_T::RESERVE0 [28]
 
__IO uint32_t RTC_T::LXTCTL
 
__IO uint32_t RTC_T::LXTOCTL
 
__IO uint32_t RTC_T::LXTICTL
 
__IO uint32_t RTC_T::TAMPCTL
 
__IO uint32_t SC_T::DAT
 
__IO uint32_t SC_T::CTL
 
__IO uint32_t SC_T::ALTCTL
 
__IO uint32_t SC_T::EGT
 
__IO uint32_t SC_T::RXTOUT
 
__IO uint32_t SC_T::ETUCTL
 
__IO uint32_t SC_T::INTEN
 
__IO uint32_t SC_T::INTSTS
 
__IO uint32_t SC_T::STATUS
 
__IO uint32_t SC_T::PINCTL
 
__IO uint32_t SC_T::TMRCTL0
 
__IO uint32_t SC_T::TMRCTL1
 
__IO uint32_t SC_T::TMRCTL2
 
__IO uint32_t SC_T::UARTCTL
 
__I uint32_t SC_T::TMRDAT0
 
__I uint32_t SC_T::TMRDAT1_2
 
__IO uint32_t SPI_T::CTL
 
__IO uint32_t SPI_T::CLKDIV
 
__IO uint32_t SPI_T::SSCTL
 
__IO uint32_t SPI_T::PDMACTL
 
__IO uint32_t SPI_T::FIFOCTL
 
__IO uint32_t SPI_T::STATUS
 
__I uint32_t SPI_T::RESERVE0 [2]
 
__O uint32_t SPI_T::TX
 
__I uint32_t SPI_T::RESERVE1 [3]
 
__I uint32_t SPI_T::RX
 
__I uint32_t SPI_T::RESERVE2 [11]
 
__IO uint32_t SPI_T::I2SCTL
 
__IO uint32_t SPI_T::I2SCLK
 
__IO uint32_t SPI_T::I2SSTS
 
__I uint32_t SYS_T::PDID
 
__IO uint32_t SYS_T::RSTSTS
 
__IO uint32_t SYS_T::IPRST0
 
__IO uint32_t SYS_T::IPRST1
 
__IO uint32_t SYS_T::IPRST2
 
__I uint32_t SYS_T::RESERVE0 [1]
 
__IO uint32_t SYS_T::BODCTL
 
__IO uint32_t SYS_T::IVSCTL
 
__I uint32_t SYS_T::RESERVE1 [1]
 
__IO uint32_t SYS_T::PORCTL
 
__IO uint32_t SYS_T::VREFCTL
 
__IO uint32_t SYS_T::USBPHY
 
__IO uint32_t SYS_T::GPA_MFPL
 
__IO uint32_t SYS_T::GPA_MFPH
 
__IO uint32_t SYS_T::GPB_MFPL
 
__IO uint32_t SYS_T::GPB_MFPH
 
__IO uint32_t SYS_T::GPC_MFPL
 
__IO uint32_t SYS_T::GPC_MFPH
 
__IO uint32_t SYS_T::GPD_MFPL
 
__IO uint32_t SYS_T::GPD_MFPH
 
__IO uint32_t SYS_T::GPE_MFPL
 
__IO uint32_t SYS_T::GPE_MFPH
 
__IO uint32_t SYS_T::GPF_MFPL
 
__I uint32_t SYS_T::RESERVE2 [29]
 
__IO uint32_t SYS_T::SRAM_BISTCTL
 
__I uint32_t SYS_T::SRAM_BISTSTS
 
__I uint32_t SYS_T::RESERVE3 [6]
 
__IO uint32_t SYS_T::IRCTCTL
 
__IO uint32_t SYS_T::IRCTIEN
 
__IO uint32_t SYS_T::IRCTISTS
 
__I uint32_t SYS_T::RESERVE4 [1]
 
__IO uint32_t SYS_T::REGLCTL
 
__I uint32_t SYS_T::RESERVE5 [11]
 
__IO uint32_t SYS_T::IRC48MTCTL
 
__IO uint32_t SYS_T::IRC48MTIEN
 
__IO uint32_t SYS_T::IRC48MTISTS
 
__IO uint32_t SYS_INT_T::NMIEN
 
__I uint32_t SYS_INT_T::NMISTS
 
__IO uint32_t TIMER_T::CTL
 
__IO uint32_t TIMER_T::CMP
 
__IO uint32_t TIMER_T::INTSTS
 
__I uint32_t TIMER_T::CNT
 
__I uint32_t TIMER_T::CAP
 
__IO uint32_t TIMER_T::EXTCTL
 
__IO uint32_t TIMER_T::EINTSTS
 
__IO uint32_t UART_T::DAT
 
__IO uint32_t UART_T::INTEN
 
__IO uint32_t UART_T::FIFO
 
__IO uint32_t UART_T::LINE
 
__IO uint32_t UART_T::MODEM
 
__IO uint32_t UART_T::MODEMSTS
 
__IO uint32_t UART_T::FIFOSTS
 
__IO uint32_t UART_T::INTSTS
 
__IO uint32_t UART_T::TOUT
 
__IO uint32_t UART_T::BAUD
 
__IO uint32_t UART_T::IRDA
 
__IO uint32_t UART_T::ALTCTL
 
__IO uint32_t UART_T::FUNCSEL
 
__IO uint32_t USBD_EP_T::BUFSEG
 
__IO uint32_t USBD_EP_T::MXPLD
 
__IO uint32_t USBD_EP_T::CFG
 
__IO uint32_t USBD_EP_T::CFGP
 
__IO uint32_t USBD_T::INTEN
 
__IO uint32_t USBD_T::INTSTS
 
__IO uint32_t USBD_T::FADDR
 
__I uint32_t USBD_T::EPSTS
 
__IO uint32_t USBD_T::ATTR
 
__I uint32_t USBD_T::VBUSDET
 
__IO uint32_t USBD_T::STBUFSEG
 
__I uint32_t USBD_T::RESERVE0 [29]
 
__IO uint32_t USBD_T::SE0
 
__I uint32_t USBD_T::RESERVE1 [283]
 
USBD_EP_T USBD_T::EP [8]
 
__I uint32_t USBH_T::HcRevision
 
__IO uint32_t USBH_T::HcControl
 
__IO uint32_t USBH_T::HcCommandStatus
 
__IO uint32_t USBH_T::HcInterruptStatus
 
__IO uint32_t USBH_T::HcInterruptEnable
 
__IO uint32_t USBH_T::HcInterruptDisable
 
__IO uint32_t USBH_T::HcHCCA
 
__IO uint32_t USBH_T::HcPeriodCurrentED
 
__IO uint32_t USBH_T::HcControlHeadED
 
__IO uint32_t USBH_T::HcControlCurrentED
 
__IO uint32_t USBH_T::HcBulkHeadED
 
__IO uint32_t USBH_T::HcBulkCurrentED
 
__IO uint32_t USBH_T::HcDoneHead
 
__IO uint32_t USBH_T::HcFmInterval
 
__I uint32_t USBH_T::HcFmRemaining
 
__I uint32_t USBH_T::HcFmNumber
 
__IO uint32_t USBH_T::HcPeriodicStart
 
__IO uint32_t USBH_T::HcLSThreshold
 
__IO uint32_t USBH_T::HcRhDescriptorA
 
__IO uint32_t USBH_T::HcRhDescriptorB
 
__IO uint32_t USBH_T::HcRhStatus
 
__IO uint32_t USBH_T::HcRhPortStatus [2]
 
__I uint32_t USBH_T::RESERVE0 [105]
 
__IO uint32_t USBH_T::HcPhyControl
 
__IO uint32_t USBH_T::HcMiscControl
 
__IO uint32_t WDT_T::CTL
 
__IO uint32_t WDT_T::ALTCTL
 
__O uint32_t WWDT_T::RLDCNT
 
__IO uint32_t WWDT_T::CTL
 
__IO uint32_t WWDT_T::STATUS
 
__I uint32_t WWDT_T::CNT
 

Detailed Description

Macro Definition Documentation

◆ _GET_BYTE0

#define _GET_BYTE0 (   u32Param)    (((u32Param) & BYTE0_Msk) )

Extract Byte 0 (Bit 0~ 7) from parameter u32Param

Definition at line 13895 of file M471M_R1_S.h.

◆ _GET_BYTE1

#define _GET_BYTE1 (   u32Param)    (((u32Param) & BYTE1_Msk) >> 8)

Extract Byte 1 (Bit 8~15) from parameter u32Param

Definition at line 13896 of file M471M_R1_S.h.

◆ _GET_BYTE2

#define _GET_BYTE2 (   u32Param)    (((u32Param) & BYTE2_Msk) >> 16)

Extract Byte 2 (Bit 16~23) from parameter u32Param

Definition at line 13897 of file M471M_R1_S.h.

◆ _GET_BYTE3

#define _GET_BYTE3 (   u32Param)    (((u32Param) & BYTE3_Msk) >> 24)

Extract Byte 3 (Bit 24~31) from parameter u32Param

Definition at line 13898 of file M471M_R1_S.h.

◆ BIT0

#define BIT0   0x00000001

Definition at line 13856 of file M471M_R1_S.h.

◆ BIT1

#define BIT1   0x00000002

Definition at line 13857 of file M471M_R1_S.h.

◆ BIT10

#define BIT10   0x00000400

Definition at line 13866 of file M471M_R1_S.h.

◆ BIT11

#define BIT11   0x00000800

Definition at line 13867 of file M471M_R1_S.h.

◆ BIT12

#define BIT12   0x00001000

Definition at line 13868 of file M471M_R1_S.h.

◆ BIT13

#define BIT13   0x00002000

Definition at line 13869 of file M471M_R1_S.h.

◆ BIT14

#define BIT14   0x00004000

Definition at line 13870 of file M471M_R1_S.h.

◆ BIT15

#define BIT15   0x00008000

Definition at line 13871 of file M471M_R1_S.h.

◆ BIT16

#define BIT16   0x00010000

Definition at line 13872 of file M471M_R1_S.h.

◆ BIT17

#define BIT17   0x00020000

Definition at line 13873 of file M471M_R1_S.h.

◆ BIT18

#define BIT18   0x00040000

Definition at line 13874 of file M471M_R1_S.h.

◆ BIT19

#define BIT19   0x00080000

Definition at line 13875 of file M471M_R1_S.h.

◆ BIT2

#define BIT2   0x00000004

Definition at line 13858 of file M471M_R1_S.h.

◆ BIT20

#define BIT20   0x00100000

Definition at line 13876 of file M471M_R1_S.h.

◆ BIT21

#define BIT21   0x00200000

Definition at line 13877 of file M471M_R1_S.h.

◆ BIT22

#define BIT22   0x00400000

Definition at line 13878 of file M471M_R1_S.h.

◆ BIT23

#define BIT23   0x00800000

Definition at line 13879 of file M471M_R1_S.h.

◆ BIT24

#define BIT24   0x01000000

Definition at line 13880 of file M471M_R1_S.h.

◆ BIT25

#define BIT25   0x02000000

Definition at line 13881 of file M471M_R1_S.h.

◆ BIT26

#define BIT26   0x04000000

Definition at line 13882 of file M471M_R1_S.h.

◆ BIT27

#define BIT27   0x08000000

Definition at line 13883 of file M471M_R1_S.h.

◆ BIT28

#define BIT28   0x10000000

Definition at line 13884 of file M471M_R1_S.h.

◆ BIT29

#define BIT29   0x20000000

Definition at line 13885 of file M471M_R1_S.h.

◆ BIT3

#define BIT3   0x00000008

Definition at line 13859 of file M471M_R1_S.h.

◆ BIT30

#define BIT30   0x40000000

Definition at line 13886 of file M471M_R1_S.h.

◆ BIT31

#define BIT31   0x80000000

Definition at line 13887 of file M471M_R1_S.h.

◆ BIT4

#define BIT4   0x00000010

Definition at line 13860 of file M471M_R1_S.h.

◆ BIT5

#define BIT5   0x00000020

Definition at line 13861 of file M471M_R1_S.h.

◆ BIT6

#define BIT6   0x00000040

Definition at line 13862 of file M471M_R1_S.h.

◆ BIT7

#define BIT7   0x00000080

Definition at line 13863 of file M471M_R1_S.h.

◆ BIT8

#define BIT8   0x00000100

Definition at line 13864 of file M471M_R1_S.h.

◆ BIT9

#define BIT9   0x00000200

Definition at line 13865 of file M471M_R1_S.h.

◆ BYTE0_Msk

#define BYTE0_Msk   (0x000000FF)

Definition at line 13890 of file M471M_R1_S.h.

◆ BYTE1_Msk

#define BYTE1_Msk   (0x0000FF00)

Definition at line 13891 of file M471M_R1_S.h.

◆ BYTE2_Msk

#define BYTE2_Msk   (0x00FF0000)

Definition at line 13892 of file M471M_R1_S.h.

◆ BYTE3_Msk

#define BYTE3_Msk   (0xFF000000)

Definition at line 13893 of file M471M_R1_S.h.

◆ CLK

#define CLK   ((CLK_T *) CLK_BASE)

Definition at line 13818 of file M471M_R1_S.h.

◆ CRC

#define CRC   ((CRC_T *) CRC_BASE)

Definition at line 13830 of file M471M_R1_S.h.

◆ EADC

#define EADC   ((EADC_T *) EADC0_BASE)

Definition at line 13835 of file M471M_R1_S.h.

◆ EBI

#define EBI   ((EBI_T *) EBI_BASE)

Definition at line 13829 of file M471M_R1_S.h.

◆ FALSE

#define FALSE   0

Definition at line 13904 of file M471M_R1_S.h.

◆ FMC

#define FMC   ((FMC_T *) FMC_BASE)

Definition at line 13828 of file M471M_R1_S.h.

◆ GPIO

#define GPIO   ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE)

Definition at line 13825 of file M471M_R1_S.h.

◆ I2C0

#define I2C0   ((I2C_T *) I2C0_BASE)

Definition at line 13850 of file M471M_R1_S.h.

◆ I2C1

#define I2C1   ((I2C_T *) I2C1_BASE)

Definition at line 13851 of file M471M_R1_S.h.

◆ inp16

#define inp16 (   port)    (*((volatile unsigned short *)(port)))

Definition at line 13951 of file M471M_R1_S.h.

◆ inp32

#define inp32 (   port)    (*((volatile unsigned int *)(port)))

Definition at line 13947 of file M471M_R1_S.h.

◆ inp8

#define inp8 (   port)    (*((volatile unsigned char *)(port)))

Definition at line 13949 of file M471M_R1_S.h.

◆ inpb

#define inpb (   port)    (*((volatile unsigned char *)(port)))

Definition at line 13942 of file M471M_R1_S.h.

◆ inps

#define inps (   port)    (*((volatile unsigned short *)(port)))

Definition at line 13944 of file M471M_R1_S.h.

◆ inpw

#define inpw (   port)    (*((volatile unsigned int *)(port)))

Definition at line 13940 of file M471M_R1_S.h.

◆ M16

#define M16 (   adr)    (*((vu16 *) (adr)))

Definition at line 13936 of file M471M_R1_S.h.

◆ M32

#define M32 (   adr)    (*((vu32 *) (adr)))

Definition at line 13937 of file M471M_R1_S.h.

◆ M8

#define M8 (   adr)    (*((vu8 *) (adr)))

Definition at line 13935 of file M471M_R1_S.h.

◆ NULL

#define NULL   0

Definition at line 13908 of file M471M_R1_S.h.

◆ outp16

#define outp16 (   port,
  value 
)    (*((volatile unsigned short *)(port))=(value))

Definition at line 13950 of file M471M_R1_S.h.

◆ outp32

#define outp32 (   port,
  value 
)    (*((volatile unsigned int *)(port))=(value))

Definition at line 13946 of file M471M_R1_S.h.

◆ outp8

#define outp8 (   port,
  value 
)    (*((volatile unsigned char *)(port))=(value))

Definition at line 13948 of file M471M_R1_S.h.

◆ outpb

#define outpb (   port,
  value 
)    (*((volatile unsigned char *)(port))=(value))

Definition at line 13941 of file M471M_R1_S.h.

◆ outps

#define outps (   port,
  value 
)    (*((volatile unsigned short *)(port))=(value))

Definition at line 13943 of file M471M_R1_S.h.

◆ outpw

#define outpw (   port,
  value 
)    (*((volatile unsigned int *)(port))=(value))

Definition at line 13939 of file M471M_R1_S.h.

◆ PA

#define PA   ((GPIO_T *) GPIOA_BASE)

Definition at line 13819 of file M471M_R1_S.h.

◆ PB

#define PB   ((GPIO_T *) GPIOB_BASE)

Definition at line 13820 of file M471M_R1_S.h.

◆ PC

#define PC   ((GPIO_T *) GPIOC_BASE)

Definition at line 13821 of file M471M_R1_S.h.

◆ PD

#define PD   ((GPIO_T *) GPIOD_BASE)

Definition at line 13822 of file M471M_R1_S.h.

◆ PDMA

#define PDMA   ((PDMA_T *) PDMA_BASE)

Definition at line 13826 of file M471M_R1_S.h.

◆ PE

#define PE   ((GPIO_T *) GPIOE_BASE)

Definition at line 13823 of file M471M_R1_S.h.

◆ PF

#define PF   ((GPIO_T *) GPIOF_BASE)

Definition at line 13824 of file M471M_R1_S.h.

◆ PWM0

#define PWM0   ((PWM_T *) PWM0_BASE)

Definition at line 13842 of file M471M_R1_S.h.

◆ PWM1

#define PWM1   ((PWM_T *) PWM1_BASE)

Definition at line 13843 of file M471M_R1_S.h.

◆ RTC

#define RTC   ((RTC_T *) RTC_BASE)

Definition at line 13834 of file M471M_R1_S.h.

◆ SC0

#define SC0   ((SC_T *) SC0_BASE)

Definition at line 13852 of file M471M_R1_S.h.

◆ SPI0

#define SPI0   ((SPI_T *) SPI0_BASE)

Definition at line 13844 of file M471M_R1_S.h.

◆ SPI1

#define SPI1   ((SPI_T *) SPI1_BASE)

Definition at line 13845 of file M471M_R1_S.h.

◆ SYS

#define SYS   ((SYS_T *) GCR_BASE)

Definition at line 13816 of file M471M_R1_S.h.

◆ SYSINT

#define SYSINT   ((SYS_INT_T *) INT_BASE)

Definition at line 13817 of file M471M_R1_S.h.

◆ TIMER0

#define TIMER0   ((TIMER_T *) TMR01_BASE)

Definition at line 13838 of file M471M_R1_S.h.

◆ TIMER1

#define TIMER1   ((TIMER_T *) (TMR01_BASE + 0x20))

Definition at line 13839 of file M471M_R1_S.h.

◆ TIMER2

#define TIMER2   ((TIMER_T *) TMR23_BASE)

Definition at line 13840 of file M471M_R1_S.h.

◆ TIMER3

#define TIMER3   ((TIMER_T *) (TMR23_BASE + 0x20))

Definition at line 13841 of file M471M_R1_S.h.

◆ TRUE

#define TRUE   1

Definition at line 13901 of file M471M_R1_S.h.

◆ UART0

#define UART0   ((UART_T *) UART0_BASE)

Definition at line 13846 of file M471M_R1_S.h.

◆ UART1

#define UART1   ((UART_T *) UART1_BASE)

Definition at line 13847 of file M471M_R1_S.h.

◆ UART2

#define UART2   ((UART_T *) UART2_BASE)

Definition at line 13848 of file M471M_R1_S.h.

◆ UART3

#define UART3   ((UART_T *) UART3_BASE)

Definition at line 13849 of file M471M_R1_S.h.

◆ USBD

#define USBD   ((USBD_T *) USBD_BASE)

Definition at line 13837 of file M471M_R1_S.h.

◆ USBH

#define USBH   ((USBH_T *) USBH_BASE)

Definition at line 13827 of file M471M_R1_S.h.

◆ WDT

#define WDT   ((WDT_T *) WDT_BASE)

Definition at line 13832 of file M471M_R1_S.h.

◆ WWDT

#define WWDT   ((WWDT_T *) WWDT_BASE)

Definition at line 13833 of file M471M_R1_S.h.

Typedef Documentation

◆ vu16

typedef volatile unsigned short vu16

Definition at line 13934 of file M471M_R1_S.h.

◆ vu32

typedef volatile unsigned long vu32

Definition at line 13933 of file M471M_R1_S.h.

◆ vu8

typedef volatile unsigned char vu8

Definition at line 13932 of file M471M_R1_S.h.

Variable Documentation

◆ ABTSTS

PDMA_T::ABTSTS

Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register

Bits Field Descriptions
[11:0] ABTIFn PDMA Read/Write Target Abort Interrupt Status Flag
This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits.
0 = No AHB bus ERROR response received when channel n transfer.
1 = AHB bus ERROR response received when channel n transfer.

Definition at line 4333 of file M471M_R1_S.h.

◆ ADDR0

I2C_T::ADDR0

Offset: 0x04 I2C Slave Address Register0

Bits Field Descriptions
[0] GC General Call Function
0 = General Call Function Disabled.
1 = General Call Function Enabled.
[7:1] ADDR I2C Address
The content of this register is irrelevant when I2C is in Master mode.
In the slave mode, the seven most significant bits must be loaded with the chip's own address.
The I2C hardware will react if either of the address is matched.

Definition at line 3702 of file M471M_R1_S.h.

◆ ADDR1

I2C_T::ADDR1

Offset: 0x18 I2C Slave Address Register1

Bits Field Descriptions
[0] GC General Call Function
0 = General Call Function Disabled.
1 = General Call Function Enabled.
[7:1] ADDR I2C Address
The content of this register is irrelevant when I2C is in Master mode.
In the slave mode, the seven most significant bits must be loaded with the chip's own address.
The I2C hardware will react if either of the address is matched.

Definition at line 3707 of file M471M_R1_S.h.

◆ ADDR2

I2C_T::ADDR2

Offset: 0x1C I2C Slave Address Register2

Bits Field Descriptions
[0] GC General Call Function
0 = General Call Function Disabled.
1 = General Call Function Enabled.
[7:1] ADDR I2C Address
The content of this register is irrelevant when I2C is in Master mode.
In the slave mode, the seven most significant bits must be loaded with the chip's own address.
The I2C hardware will react if either of the address is matched.

Definition at line 3708 of file M471M_R1_S.h.

◆ ADDR3

I2C_T::ADDR3

Offset: 0x20 I2C Slave Address Register3

Bits Field Descriptions
[0] GC General Call Function
0 = General Call Function Disabled.
1 = General Call Function Enabled.
[7:1] ADDR I2C Address
The content of this register is irrelevant when I2C is in Master mode.
In the slave mode, the seven most significant bits must be loaded with the chip's own address.
The I2C hardware will react if either of the address is matched.

Definition at line 3709 of file M471M_R1_S.h.

◆ ADDRMSK0

I2C_T::ADDRMSK0

Offset: 0x24 I2C Slave Address Mask Register0

Bits Field Descriptions
[7:1] ADDRMSK I2C Address Mask
0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
1 = Mask Enabled (the received corresponding address bit is don't care.).
I2C bus controllers support multiple address recognition with four address mask register.
When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.

Definition at line 3710 of file M471M_R1_S.h.

◆ ADDRMSK1

I2C_T::ADDRMSK1

Offset: 0x28 I2C Slave Address Mask Register1

Bits Field Descriptions
[7:1] ADDRMSK I2C Address Mask
0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
1 = Mask Enabled (the received corresponding address bit is don't care.).
I2C bus controllers support multiple address recognition with four address mask register.
When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.

Definition at line 3711 of file M471M_R1_S.h.

◆ ADDRMSK2

I2C_T::ADDRMSK2

Offset: 0x2C I2C Slave Address Mask Register2

Bits Field Descriptions
[7:1] ADDRMSK I2C Address Mask
0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
1 = Mask Enabled (the received corresponding address bit is don't care.).
I2C bus controllers support multiple address recognition with four address mask register.
When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.

Definition at line 3712 of file M471M_R1_S.h.

◆ ADDRMSK3

I2C_T::ADDRMSK3

Offset: 0x30 I2C Slave Address Mask Register3

Bits Field Descriptions
[7:1] ADDRMSK I2C Address Mask
0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
1 = Mask Enabled (the received corresponding address bit is don't care.).
I2C bus controllers support multiple address recognition with four address mask register.
When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.

Definition at line 3713 of file M471M_R1_S.h.

◆ AHBCLK

CLK_T::AHBCLK

Offset: 0x04 AHB Devices Clock Enable Control Register

Bits Field Descriptions
[1] PDMACKEN PDMA Controller Clock Enable Bit
0 = PDMA peripheral clock Disabled.
1 = PDMA peripheral clock Enabled.
[2] ISPCKEN Flash ISP Controller Clock Enable Bit
0 = Flash ISP peripheral clock Disabled.
1 = Flash ISP peripheral clock Enabled.
[3] EBICKEN EBI Controller Clock Enable Bit
0 = EBI peripheral clock Disabled.
1 = EBI peripheral clock Enabled.
[4] USBHCKEN USB HOST Controller Clock Enable Bit
0 = USB HOST peripheral clock Disabled.
1 = USB HOST peripheral clock Enabled.
[7] CRCCKEN CRC Generator Controller Clock Enable Bit
0 = CRC peripheral clock Disabled.
1 = CRC peripheral clock Enabled.
[15] FMCIDLE Flash Memory Controller Clock Enable Bit In IDLE Mode
0 = FMC peripheral clock Disabled when chip operating at IDLE mode.
1 = FMC peripheral clock Enabled when chip operating at IDLE mode.

Definition at line 1414 of file M471M_R1_S.h.

◆ ALTCTL [1/3]

SC_T::ALTCTL

Offset: 0x08 SC Alternate Control Register.

Bits Field Descriptions
[0] TXRST TX Software Reset
When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.
0 = No effect.
1 = Reset the TX internal state machine and pointers.
Note:
This bit will be auto cleared after reset is complete.
[1] RXRST Rx Software Reset
When RXRST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.
0 = No effect.
1 = Reset the Rx internal state machine and pointers.
Note:
This bit will be auto cleared after reset is complete.
[2] DACTEN Deactivation Sequence Generator Enable Bit
This bit enables SC controller to initiate the card by deactivation sequence
0 = No effect.
1 = Deactivation sequence generator Enabled.
Note1:
When the deactivation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
Note2:
This field will be cleared by TXRST (SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
So don't fill this bit, TXRST, and RXRST at the same time.
Note3:
If SCEN (SC_CTL[0]) is not enabled, this filed cannot be programmed.
[3] ACTEN Activation Sequence Generator Enable Bit
This bit enables SC controller to initiate the card by activation sequence
0 = No effect.
1 = Activation sequence generator Enabled.
Note1:
When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
Note2:
This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
Note3:
If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
[4] WARSTEN Warm Reset Sequence Generator Enable Bit
This bit enables SC controller to initiate the card by warm reset sequence
0 = No effect.
1 = Warm reset sequence generator Enabled.
Note1:
When the warm reset sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
Note2:
This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST, and RXRST at the same time.
Note3:
If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
[5] CNTEN0 Internal Timer0 Start Enable Bit
This bit enables Timer 0 to start counting.
Software can fill 0 to stop it and set 1 to reload and count.
0 = Stops counting.
1 = Start counting.
Note1:
This field is used for internal 24 bit timer when TMRSEL (SC_CTL[14:13]) = 01.
Note2:
If the operation mode is not in auto-reload mode (SC_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware.
Note3:
This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
So don't fill this bit, TXRST and RXRST at the same time.
Note4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
[6] CNTEN1 Internal Timer1 Start Enable Bit
This bit enables Timer 1 to start counting.
Software can fill 0 to stop it and set 1 to reload and count.
0 = Stops counting.
1 = Start counting.
Note1:
This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 10 or TMRSEL(SC_CTL[14:13]) = 11.
Don't filled CNTEN1 when TMRSEL(SC_CTL[14:13]) = 00 or TMRSEL(SC_CTL[14:13]) = 01.
Note2:
If the operation mode is not in auto-reload mode (SC_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware.
Note3:
This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
Note4:
If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
[7] CNTEN2 Internal Timer2 Start Enable Bit
This bit enables Timer 2 to start counting.
Software can fill 0 to stop it and set 1 to reload and count.
0 = Stops counting.
1 = Start counting.
Note1:
This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 11.
Don't filled CNTEN2 when TMRSEL(SC_CTL[14:13]) = 00 or TMRSEL(SC_CTL[14:13]) = 01 or TMRSEL(SC_CTL[14:13]) = 10.
Note2:
If the operation mode is not in auto-reload mode (SC_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware.
Note3:
This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
So don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
Note4:
If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
[9:8] INITSEL Initial Timing Selection
This fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).
Unit: SC clock
Activation: refer to SC Activation Sequence in Figure 6.17-4
Warm-reset: refer to Warm-Reset Sequence in Figure 6.17-5
Deactivation: refer to Deactivation Sequence in Figure 6.17-6
[12] RXBGTEN Receiver Block Guard Time Function Enable Bit
0 = Receiver block guard time function Disabled.
1 = Receiver block guard time function Enabled.
[13] ACTSTS0 Internal Timer0 Active State (Read Only)
This bit indicates the timer counter status of timer0.
0 = Timer0 is not active.
1 = Timer0 is active.
[14] ACTSTS1 Internal Timer1 Active State (Read Only)
This bit indicates the timer counter status of timer1.
0 = Timer1 is not active.
1 = Timer1 is active.
[15] ACTSTS2 Internal Timer2 Active State (Read Only)
This bit indicates the timer counter status of timer2.
0 = Timer2 is not active.
1 = Timer2 is active.

Definition at line 8494 of file M471M_R1_S.h.

◆ ALTCTL [2/3]

UART_T::ALTCTL

Offset: 0x2C UART Alternate Control/Status Register

Bits Field Descriptions
[3:0] BRKFL UART LIN Break Field Length (Only Available In UART0/UART1 Channel)
This field indicates a 4-bit LIN TX break field count.
Note1: This break field length is BRKFL + 1
Note2: According to LIN spec, the reset value is 0xC (break field length = 13).
[6] LINRXEN LIN RX Enable Bit (Only Available In UART0/UART1 Channel)
0 = LIN RX mode Disabled.
1 = LIN RX mode Enabled.
[7] LINTXEN LIN TX Break Mode Enable Bit (Only Available In UART0/UART1 Channel)
0 = LIN TX Break mode Disabled.
1 = LIN TX Break mode Enabled.
Note: When TX break field transfer operation finished, this bit will be cleared automatically.
[8] RS485NMM RS-485 Normal Multi-Drop Operation Mode (NMM)
0 = RS-485 Normal Multi-drop Operation mode (NMM) Disabled.
1 = RS-485 Normal Multi-drop Operation mode (NMM) Enabled.
Note: It cannot be active with RS-485_AAD operation mode.
[9] RS485AAD RS-485 Auto Address Detection Operation Mode (AAD)
0 = RS-485 Auto Address Detection Operation mode (AAD) Disabled.
1 = RS-485 Auto Address Detection Operation mode (AAD) Enabled.
Note: It cannot be active with RS-485_NMM operation mode.
[10] RS485AUD RS-485 Auto Direction Function (AUD)
0 = RS-485 Auto Direction Operation function (AUD) Disabled.
1 = RS-485 Auto Direction Operation function (AUD) Enabled.
Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
[15] ADDRDEN RS-485 Address Detection Enable Bit
This bit is used to enable RS-485 Address Detection mode.
0 = Address detection mode Disabled.
1 = Address detection mode Enabled.
Note: This bit is used for RS-485 any operation mode.
[17] ABRIF Auto-Baud Rate Interrupt Flag (Read Only)
This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.
Note: This bit is read only, but it can be cleared by writing "1" to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1])
[18] ABRDEN Auto-Baud Rate Detect Enable Bit
0 = Auto-baud rate detect function Disabled.
1 = Auto-baud rate detect function Enabled.
This bit is cleared automatically after auto-baud detection is finished.
[20:19] ABRDBITS Auto-Baud Rate Detect Bit Length
00 = 1-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x01.
01 = 2-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x02.
10 = 4-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x08.
11 = 8-bit time from Start bit to the 1st rising edge. The input pattern shall be 0x80.
Note : The calculation of bit number includes the START bit.
[31:24] ADDRMV Address Match Value
This field contains the RS-485 address match values.
Note: This field is used for RS-485 auto address detection mode.

Definition at line 11894 of file M471M_R1_S.h.

◆ ALTCTL [3/3]

WDT_T::ALTCTL

Offset: 0x04 WDT Alternative Control Register

Bits Field Descriptions
[1:0] RSTDSEL WDT Reset Delay Selection (Write Protect)
When WDT time-out happened, user has a time named WDT Reset Delay Period to clear WDT counter by setting RSTCNT (WDT_CTL[0]) to prevent WDT time-out reset happened.
User can select a suitable setting of RSTDSEL for different WDT Reset Delay Period.
00 = WDT Reset Delay Period is 1026 * WDT_CLK.
01 = WDT Reset Delay Period is 130 * WDT_CLK.
10 = WDT Reset Delay Period is 18 * WDT_CLK.
11 = WDT Reset Delay Period is 3 * WDT_CLK.
Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note2: This register will be reset to 0 if WDT time-out reset happened.

Definition at line 13567 of file M471M_R1_S.h.

◆ APBCLK0

CLK_T::APBCLK0

Offset: 0x08 APB Devices Clock Enable Control Register 0

Bits Field Descriptions
[0] WDTCKEN Watchdog Timer Clock Enable Bit (Write Protect)
0 = Watchdog Timer Clock Disabled.
1 = Watchdog Timer Clock Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[1] RTCCKEN Real-Time-Clock APB Interface Clock Enable Bit
This bit is used to control the RTC APB clock only.
The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8]).
It can be selected to external 32.768 kHz low speed crystal or internal 10 kHz low speed oscillator.
0 = RTC Clock Disabled.
1 = RTC Clock Enabled.
[2] TMR0CKEN Timer0 Clock Enable Bit
0 = Timer0 Clock Disabled.
1 = Timer0 Clock Enabled.
[3] TMR1CKEN Timer1 Clock Enable Bit
0 = Timer1 Clock Disabled.
1 = Timer1 Clock Enabled.
[4] TMR2CKEN Timer2 Clock Enable Bit
0 = Timer2 Clock Disabled.
1 = Timer2 Clock Enabled.
[5] TMR3CKEN Timer3 Clock Enable Bit
0 = Timer3 Clock Disabled.
1 = Timer3 Clock Enabled.
[6] CLKOCKEN CLKO Clock Enable Bit
0 = CLKO Clock Disabled.
1 = CLKO Clock Enabled.
[8] I2C0CKEN I2C0 Clock Enable Bit
0 = I2C0 Clock Disabled.
1 = I2C0 Clock Enabled.
[9] I2C1CKEN I2C1 Clock Enable Bit
0 = I2C1 Clock Disabled.
1 = I2C1 Clock Enabled.
[12] SPI0CKEN SPI0 Clock Enable Bit
0 = SPI0 Clock Disabled.
1 = SPI0 Clock Enabled.
[13] SPI1CKEN SPI1 Clock Enable Bit
0 = SPI1 Clock Disabled.
1 = SPI1 Clock Enabled.
[16] UART0CKEN UART0 Clock Enable Bit
0 = UART0 clock Disabled.
1 = UART0 clock Enabled.
[17] UART1CKEN UART1 Clock Enable Bit
0 = UART1 clock Disabled.
1 = UART1 clock Enabled.
[18] UART2CKEN UART2 Clock Enable Bit
0 = UART2 clock Disabled.
1 = UART2 clock Enabled.
[19] UART3CKEN UART3 Clock Enable Bit
0 = UART3 clock Disabled.
1 = UART3 clock Enabled.
[27] USBDCKEN USB Device Clock Enable Bit
0 = USB Device clock Disabled.
1 = USB Device clock Enabled.
[28] EADCCKEN Enhanced Analog-Digital-Converter (EADC) Clock Enable Bit
0 = EADC clock Disabled.
1 = EADC clock Enabled.

Definition at line 1415 of file M471M_R1_S.h.

◆ APBCLK1

CLK_T::APBCLK1

Offset: 0x0C APB Devices Clock Enable Control Register 1

Bits Field Descriptions
[0] SC0CKEN SC0 Clock Enable Bit
0 = SC0 Clock Disabled.
1 = SC0 Clock Enabled.
[16] PWM0CKEN PWM0 Clock Enable Bit
0 = PWM0 Clock Disabled.
1 = PWM0 Clock Enabled.
[17] PWM1CKEN PWM1 Clock Enable Bit
0 = PWM1 Clock Disabled.
1 = PWM1 Clock Enabled.
[25] TKCKEN Touch Key Clock Enable Bit
0 = Touch Key Clock Disabled.
1 = Touch key Clock Enabled.

Definition at line 1416 of file M471M_R1_S.h.

◆ ATTR

USBD_T::ATTR

Offset: 0x10 USB Bus Status and Attribution Register

Bits Field Descriptions
[0] USBRST USB Reset Status
0 = Bus no reset.
1 = Bus reset when SE0 (single-ended 0) is presented more than 2.5us.
Note: This bit is read only.
[1] SUSPEND Suspend Status
0 = Bus no suspend.
1 = Bus idle more than 3ms, either cable is plugged off or host is sleeping.
Note: This bit is read only.
[2] RESUME Resume Status
0 = No bus resume.
1 = Resume from suspend.
Note: This bit is read only.
[3] TOUT Time-Out Status
0 = No time-out.
1 = No Bus response more than 18 bits time.
Note: This bit is read only.
[4] PHYEN PHY Transceiver Function Enable
0 = PHY transceiver function Disabled.
1 = PHY transceiver function Enabled.
[5] RWAKEUP Remote Wake-Up
0 = Release the USB bus from K state.
1 = Force USB bus to K (USB_D+ low, USB_D- high) state, used for remote wake-up.
[7] USBEN USB Controller Enable
0 = USB Controller Disabled.
1 = USB Controller Enabled.
[8] DPPUEN Pull-Up Resistor On USB_D+ Enable
0 = Pull-up resistor in USB_D+ pin Disabled.
1 = Pull-up resistor in USB_D+ pin Enabled.
[9] PWRDN Power Down PHY Transceiver, Low Active
0 = Power down related circuits of PHY transceiver.
1 = Turn on related circuits of PHY transceiver.
[10] BYTEM CPU Access USB SRAM Size Mode Selection
0 = Word mode: The size of the transfer from CPU to USB SRAM can be Word only.
1 = Byte mode: The size of the transfer from CPU to USB SRAM can be Byte only.

Definition at line 12513 of file M471M_R1_S.h.

◆ BAUD

UART_T::BAUD

Offset: 0x24 UART Baud Rate Divisor Register

Bits Field Descriptions
[15:0] BRD Baud Rate Divider
The field indicates the baud rate divider.
This filed is used in baud rate calculation.
The detail description is shown in Table 6.21-2.
[27:24] EDIVM1 Extra Divider For BAUD Rate Mode 1
This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2.
The detail description is shown in Table 6.21-2.
[28] BAUDM0 BAUD Rate Mode Selection Bit 0
This bit is baud rate mode selection bit 0.
UART provides three baud rate calculation modes.
This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode.
The detail description is shown in Table 6.21-2.
[29] BAUDM1 BAUD Rate Mode Selection Bit 1
This bit is baud rate mode selection bit 1.
UART provides three baud rate calculation modes.
This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode.
The detail description is shown in Table 6.21-2.
Note: In IrDA mode must be operated in mode 0.

Definition at line 11892 of file M471M_R1_S.h.

◆ BNF

PWM_T::BNF

Offset: 0xC0 PWM Brake Noise Filter Register

Bits Field Descriptions
[0] BRK0NFEN PWM Brake 0 Noise Filter Enable
0 = Noise filter of PWM Brake 0 Disabled.
1 = Noise filter of PWM Brake 0 Enabled.
[3:1] BRK0NFSEL Brake 0 Edge Detector Filter Clock Selection
000 = Filter clock = HCLK.
001 = Filter clock = HCLK/2.
010 = Filter clock = HCLK/4.
011 = Filter clock = HCLK/8.
100 = Filter clock = HCLK/16.
101 = Filter clock = HCLK/32.
110 = Filter clock = HCLK/64.
111 = Filter clock = HCLK/128.
[6:4] BRK0FCNT Brake 0 Edge Detector Filter Count
The register bits control the Brake0 filter counter to count from 0 to BRK1FCNT.
[7] BRK0PINV Brake 0 Pin Inverse
0 = The state of pin PWMx_BRAKE0 is passed to the negative edge detector.
1 = The inverted state of pin PWMx_BRAKE10 is passed to the negative edge detector.
[8] BRK1NFEN PWM Brake 1 Noise Filter Enable
0 = Noise filter of PWM Brake 1 Disabled.
1 = Noise filter of PWM Brake 1 Enabled.
[11:9] BRK1NFSEL Brake 1 Edge Detector Filter Clock Selection
000 = Filter clock = HCLK.
001 = Filter clock = HCLK/2.
010 = Filter clock = HCLK/4.
011 = Filter clock = HCLK/8.
100 = Filter clock = HCLK/16.
101 = Filter clock = HCLK/32.
110 = Filter clock = HCLK/64.
111 = Filter clock = HCLK/128.
[14:12] BRK1FCNT Brake 1 Edge Detector Filter Count
The register bits control the Brake1 filter counter to count from 0 to BRK1FCNT.
[15] BRK1PINV Brake 1 Pin Inverse
0 = The state of pin PWMx_BRAKE1 is passed to the negative edge detector.
1 = The inverted state of pin PWMx_BRAKE1 is passed to the negative edge detector.
[16] BK0SRC Brake 0 Pin Source Select
For PWM0 setting:
0 = Brake 0 pin source come from PWM0_BRAKE0.
1 = Brake 0 pin source come from PWM1_BRAKE0.
For PWM1 setting:
0 = Brake 0 pin source come from PWM1_BRAKE0.
1 = Brake 0 pin source come from PWM0_BRAKE0.
[24] BK1SRC Brake 1 Pin Source Select
For PWM0 setting:
0 = Brake 1 pin source come from PWM0_BRAKE1.
1 = Brake 1 pin source come from PWM1_BRAKE1.
For PWM1 setting:
0 = Brake 1 pin source come from PWM1_BRAKE1.
1 = Brake 1 pin source come from PWM0_BRAKE1.

Definition at line 5845 of file M471M_R1_S.h.

◆ BODCTL

SYS_T::BODCTL

Offset: 0x18 Brown-Out Detector Control Register

Bits Field Descriptions
[0] BODEN Brown-Out Detector Enable Bit (Write Protect)
The default value is set by flash controller user configuration register CBODEN (CONFIG0 [23]).
0 = Brown-out Detector function Disabled.
1 = Brown-out Detector function Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[2:1] BODVL Brown-Out Detector Threshold Voltage Selection (Write Protect)
The default value is set by flash controller user configuration register CBOV (CONFIG0 [22:21]).
00 = Brown-Out Detector Threshold Voltage is 2.2V
01 = Brown-Out Detector Threshold Voltage is 2.7V
10 = Brown-Out Detector Threshold Voltage is 3.7V
11 = Brown-Out Detector Threshold Voltage is 4.5V
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[3] BODRSTEN Brown-Out Reset Enable Bit (Write Protect)
The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit .
0 = Brown-out "INTERRUPT" function Enabled.
1 = Brown-out "RESET" function Enabled.
Note1:
While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).
While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high.
BOD interrupt will keep till to the BODEN set to 0.
BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).
Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
[4] BODIF Brown-Out Detector Interrupt Flag
0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting.
1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled.
Note: Write 1 to clear this bit to 0.
[5] BODLPM Brown-Out Detector Low Power Mode (Write Protect)
0 = BOD operate in normal mode (default).
1 = BOD Low Power mode Enabled.
Note1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
[6] BODOUT Brown-Out Detector Output Status
0 = Brown-out Detector output status is 0.
It means the detected voltage is higher than BODVL setting or BODEN is 0.
1 = Brown-out Detector output status is 1.
It means the detected voltage is lower than BODVL setting.
If the BODEN is 0, BOD function disabled , this bit always responds 0000.
[7] LVREN Low Voltage Reset Enable Bit (Write Protect)
The LVR function resets the chip when the input power voltage is lower than LVR circuit setting.
LVR function is enabled by default.
0 = Low Voltage Reset function Disabled.
1 = Low Voltage Reset function Enabled
Note1: After enabling the bit, the LVR function will be active with 100us delay for LVR output stable (default).
Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
[10:8] BODDGSEL Brown-Out Detector Output De-Glitch Time Select (Write Protect)
000 = BOD output is sampled by RC10K clock.
001 = 4 system clock (HCLK).
010 = 8 system clock (HCLK).
011 = 16 system clock (HCLK).
100 = 32 system clock (HCLK).
101 = 64 system clock (HCLK).
110 = 128 system clock (HCLK).
111 = 256 system clock (HCLK).
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[14:12] LVRDGSEL LVR Output De-Glitch Time Select (Write Protect)
000 = Without de-glitch function.
001 = 4 system clock (HCLK).
010 = 8 system clock (HCLK).
011 = 16 system clock (HCLK).
100 = 32 system clock (HCLK).
101 = 64 system clock (HCLK).
110 = 128 system clock (HCLK).
111 = 256 system clock (HCLK).
Note: This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 10314 of file M471M_R1_S.h.

◆ BRKCTL0_1

PWM_T::BRKCTL0_1

Offset: 0xC8 PWM Brake Edge Detect Control Register 0

Bits Field Descriptions
[4] BRKP0EEN Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)
0 = BKP0 pin as edge-detect brake source Disabled.
1 = BKP0 pin as edge-detect brake source Enabled.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[5] BRKP1EEN Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)
0 = BKP1 pin as edge-detect brake source Disabled.
1 = BKP1 pin as edge-detect brake source Enabled.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[7] SYSEBEN Enable System Fail As Edge-Detect Brake Source (Write Protect)
0 = System Fail condition as edge-detect brake source Disabled.
1 = System Fail condition as edge-detect brake source Enabled.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[12] BRKP0LEN Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)
0 = PWMx_BRAKE0 pin as level-detect brake source Disabled.
1 = PWMx_BRAKE0 pin as level-detect brake source Enabled.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[13] BRKP1LEN Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)
0 = PWMx_BRAKE1 pin as level-detect brake source Disabled.
1 = PWMx_BRAKE1 pin as level-detect brake source Enabled.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[15] SYSLBEN Enable System Fail As Level-Detect Brake Source (Write Protect)
0 = System Fail condition as level-detect brake source Disabled.
1 = System Fail condition as level-detect brake source Enabled.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[17:16] BRKAEVEN PWM Brake Action Select For Even Channel (Write Protect)
00 = PWM even channel level-detect brake function not affect channel output.
01 = PWM even channel output tri-state when level-detect brake happened.
10 = PWM even channel output low level when level-detect brake happened.
11 = PWM even channel output high level when level-detect brake happened.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[19:18] BRKAODD PWM Brake Action Select For Odd Channel (Write Protect)
00 = PWM odd channel level-detect brake function not affect channel output.
01 = PWM odd channel output tri-state when level-detect brake happened.
10 = PWM odd channel output low level when level-detect brake happened.
11 = PWM odd channel output high level when level-detect brake happened.
Note: This register is write protected. Refer to SYS_REGLCTL register.

Definition at line 5847 of file M471M_R1_S.h.

◆ BRKCTL2_3

PWM_T::BRKCTL2_3

Offset: 0xCC PWM Brake Edge Detect Control Register 2

Bits Field Descriptions
[4] BRKP0EEN Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)
0 = BKP0 pin as edge-detect brake source Disabled.
1 = BKP0 pin as edge-detect brake source Enabled.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[5] BRKP1EEN Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)
0 = BKP1 pin as edge-detect brake source Disabled.
1 = BKP1 pin as edge-detect brake source Enabled.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[7] SYSEBEN Enable System Fail As Edge-Detect Brake Source (Write Protect)
0 = System Fail condition as edge-detect brake source Disabled.
1 = System Fail condition as edge-detect brake source Enabled.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[12] BRKP0LEN Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)
0 = PWMx_BRAKE0 pin as level-detect brake source Disabled.
1 = PWMx_BRAKE0 pin as level-detect brake source Enabled.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[13] BRKP1LEN Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)
0 = PWMx_BRAKE1 pin as level-detect brake source Disabled.
1 = PWMx_BRAKE1 pin as level-detect brake source Enabled.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[15] SYSLBEN Enable System Fail As Level-Detect Brake Source (Write Protect)
0 = System Fail condition as level-detect brake source Disabled.
1 = System Fail condition as level-detect brake source Enabled.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[17:16] BRKAEVEN PWM Brake Action Select For Even Channel (Write Protect)
00 = PWM even channel level-detect brake function not affect channel output.
01 = PWM even channel output tri-state when level-detect brake happened.
10 = PWM even channel output low level when level-detect brake happened.
11 = PWM even channel output high level when level-detect brake happened.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[19:18] BRKAODD PWM Brake Action Select For Odd Channel (Write Protect)
00 = PWM odd channel level-detect brake function not affect channel output.
01 = PWM odd channel output tri-state when level-detect brake happened.
10 = PWM odd channel output low level when level-detect brake happened.
11 = PWM odd channel output high level when level-detect brake happened.
Note: This register is write protected. Refer to SYS_REGLCTL register.

Definition at line 5848 of file M471M_R1_S.h.

◆ BRKCTL4_5

PWM_T::BRKCTL4_5

Offset: 0xD0 PWM Brake Edge Detect Control Register 4

Bits Field Descriptions
[4] BRKP0EEN Enable PWMx_BRAKE0 Pin As Edge-Detect Brake Source (Write Protect)
0 = BKP0 pin as edge-detect brake source Disabled.
1 = BKP0 pin as edge-detect brake source Enabled.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[5] BRKP1EEN Enable PWMx_BRAKE1 Pin As Edge-Detect Brake Source (Write Protect)
0 = BKP1 pin as edge-detect brake source Disabled.
1 = BKP1 pin as edge-detect brake source Enabled.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[7] SYSEBEN Enable System Fail As Edge-Detect Brake Source (Write Protect)
0 = System Fail condition as edge-detect brake source Disabled.
1 = System Fail condition as edge-detect brake source Enabled.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[12] BRKP0LEN Enable BKP0 Pin As Level-Detect Brake Source (Write Protect)
0 = PWMx_BRAKE0 pin as level-detect brake source Disabled.
1 = PWMx_BRAKE0 pin as level-detect brake source Enabled.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[13] BRKP1LEN Enable BKP1 Pin As Level-Detect Brake Source (Write Protect)
0 = PWMx_BRAKE1 pin as level-detect brake source Disabled.
1 = PWMx_BRAKE1 pin as level-detect brake source Enabled.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[15] SYSLBEN Enable System Fail As Level-Detect Brake Source (Write Protect)
0 = System Fail condition as level-detect brake source Disabled.
1 = System Fail condition as level-detect brake source Enabled.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[17:16] BRKAEVEN PWM Brake Action Select For Even Channel (Write Protect)
00 = PWM even channel level-detect brake function not affect channel output.
01 = PWM even channel output tri-state when level-detect brake happened.
10 = PWM even channel output low level when level-detect brake happened.
11 = PWM even channel output high level when level-detect brake happened.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[19:18] BRKAODD PWM Brake Action Select For Odd Channel (Write Protect)
00 = PWM odd channel level-detect brake function not affect channel output.
01 = PWM odd channel output tri-state when level-detect brake happened.
10 = PWM odd channel output low level when level-detect brake happened.
11 = PWM odd channel output high level when level-detect brake happened.
Note: This register is write protected. Refer to SYS_REGLCTL register.

Definition at line 5849 of file M471M_R1_S.h.

◆ BUFSEG

USBD_EP_T::BUFSEG

Offset: 0x500/0x510/0x520/0x530/0x540/0x550/0x560/0x570 Endpoint 0~7 Buffer Segmentation Register

Bits Field Descriptions
[8:3] BUFSEG Endpoint Buffer Segmentation
It is used to indicate the offset address for each endpoint with the USB SRAM starting address The effective starting address of the endpoint is
USB_SRAM address + { BUFSEG[8:3], 3'b000}
Where the USB_SRAM address = USBD_BA+0x100h.
Refer to the section 5.4.4.7 for the endpoint SRAM structure and its description.

Definition at line 12271 of file M471M_R1_S.h.

◆ BUSCTL

I2C_T::BUSCTL

Offset: 0x44 I2C Bus Management Control Register

Bits Field Descriptions
[0] ACKMEN Acknowledge Control By Manual
In order to allow ACK control in slave reception including the command and data, slave byte control mode must be enabled by setting the ACKMEN bit.
0 = Slave byte control Disabled.
1 = Slave byte control Enabled.
The 9th bit can response the ACK or NACK according the received data by user.
When the byte is received, stretching the SCLK signal low between the 8th and 9th SCLK pulse.
Note: If the BMDEN =1 and this bit is enabled, the information of I2C_STATUS will be fixed as 0xF0 in slave receive condition.
[1] PECEN Packet Error Checking Calculation Enable Bit
0 = Packet Error Checking Calculation Disabled.
1 = Packet Error Checking Calculation Enabled.
[2] BMDEN Bus Management Device Default Address Enable Bit
0 = Device default address Disable.
When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses NACKed.
1 = Device default address Enabled.
When the address 0'b1100001x coming and the both of BMDEN and ACKMEN are enabled, the device responses ACKed.
[3] BMHEN Bus Management Host Enable Bit
0 = Host function Disabled.
1 = Host function Enabled and the SUSCON will be used as CONTROL function.
[4] ALERTEN Bus Management Alert Enable Bit
Device Mode (BMHEN =0).
0 = Release the BM_ALERT pin high and Alert Response Header disabled: 0001100x followed by NACK if both of BMDEN and ACKMEN are enabled.
1 = Drive BM_ALERT pin low and Alert Response Address Header enables: 0001100x followed by ACK if both of BMDEN and ACKMEN are enabled.
Host Mode (BMHEN =1).
0 = BM_ALERT pin not supported.
1 = BM_ALERT pin supported.
[5] SCTLOSTS Suspend/Control Data Output Status
0 = The output of SUSCON pin is low.
1 = The output of SUSCON pin is high.
[6] SCTLOEN Suspend Or Control Pin Output Enable Bit
0 = The SUSCON pin in input.
1 = The output enable is active on the SUSCON pin.
[7] BUSEN BUS Enable Bit
0 = The system management function is Disabled.
1 = The system management function is Enable.
Note: When the bit is enabled, the internal 14-bit counter is used to calculate the time out event of clock low condition.
[8] PECTXEN Packet Error Checking Byte Transmission/Reception
This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address Matched is received
0 = No PEC transfer.
1 = PEC transmission/reception is requested.
Note: 1.This bit has no effect in slave mode when ACKMEN =0.
[9] TIDLE Timer Check In Idle State
The BUSTOUT is used to calculate the time-out of clock low in bus active and the idle period in bus Idle.
This bit is used to define which condition is enabled.
0 = The BUSTOUT is used to calculate the clock low period in bus active.
1 = The BUSTOUT is used to calculate the IDLE period in bus Idle.
Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus state.
[10] PECCLR PEC Clear At Repeat Start
The calculation of PEC starts when PECEN is set to 1 and it is clear when the STA or STO bit is detected.
This PECCLR bit is used to enable the condition of REPEAT START can clear the PEC calculation.
0 = The PEC calculation is cleared by "Repeat Start" function is Disabled.
1 = The PEC calculation is cleared by "Repeat Start" function is Enabled.
[11] ACKM9SI Acknowledge Manual Enable Extra SI Interrupt
0 = There is no SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1.
1 = There is SI interrupt in the 9th clock cycle when the BUSEN =1 and ACKMEN =1.

Definition at line 3717 of file M471M_R1_S.h.

◆ BUSSTS

I2C_T::BUSSTS

Offset: 0x4C I2C Bus Management Status Register

Bits Field Descriptions
[0] BUSY Bus Busy
Indicates that a communication is in progress on the bus.
It is set by hardware when a START condition is detected.
It is cleared by hardware when a STOP condition is detected.
0 = The bus is IDLE (both SCLK and SDA High).
1 = The bus is busy.
[1] BCDONE Byte Count Transmission/Receive Done
0 = Indicates the transmission/ receive is not finished when the PECEN is set.
1 = Indicates the transmission/ receive is finished when the PECEN is set.
Note: Software can write 1 to clear this bit.
[2] PECERR PEC Error In Reception
0 = Indicates the PEC value equal the received PEC data packet.
1 = Indicates the PEC value doesn't match the receive PEC data packet.
Note: Software can write 1 to clear this bit.
[3] ALERT SMBus Alert Status
Device Mode (BMHEN =0).
0 = Indicates SMALERT pin state is low.
1 = Indicates SMALERT pin state is high
Host Mode (BMHEN =1).
0 = No SMBALERT event.
1 = Indicates there is SMBALERT event (falling edge) is detected in SMALERT pin when the BMHEN = 1 (SMBus host configuration) and the ALERTEN = 1.
Note: 1.
The SMALERT pin is an open-drain pin, the pull-high resistor is must in the system.
2.
Software can write 1 to clear this bit.
[4] SCTLDIN Bus Suspend Or Control Signal Input Status
0 = The input status of SUSCON pin is 0.
1 = The input status of SUSCON pin is 1.
[5] BUSTO Bus Time-out Status
0 = Indicates that there is no any time-out or external clock time-out.
1 = Indicates that a time-out or external clock time-out occurred.
In bus busy, the bit indicates the total clock low time-out event occurred otherwise, it indicates the bus idle time-out event occurred.
Note: Software can write 1 to clear this bit.
[6] CLKTO Clock Low Cumulate Time-out Status
0 = Indicates that the cumulative clock low is no any time-out.
1 = Indicates that the cumulative clock low time-out occurred.
Note: Software can write 1 to clear this bit.

Definition at line 3719 of file M471M_R1_S.h.

◆ BUSTCTL

I2C_T::BUSTCTL

Offset: 0x48 I2C Bus Management Timer Control Register

Bits Field Descriptions
[0] BUSTOEN Bus Time Out Enable Bit
0 = Indicates the bus clock low time-out detection is Disabled.
1 = Indicates the bus clock low time-out detection is Enabled
bus clock is low for more than Time-out (in BIDLE=0) or high more than Time-out(in BIDLE =1),
[1] CLKTOEN Cumulative Clock Low Time Out Enable Bit
0 = Indicates the cumulative clock low time-out detection is Disabled.
1 = Indicates the cumulative clock low time-out detection is Enabled.
For Master, it calculates the period from START to ACK
For Slave, it calculates the period from START to STOP
[2] BUSTOIEN Time-Out Interrupt Enable Bit
BUSY =1.
0 = Indicates the SCLK low time-out interrupt is Disabled.
1 = Indicates the SCLK low time-out interrupt is Enabled.
BUSY =0.
0 = Indicates the bus IDLE time-out interrupt is Disabled.
1 = Indicates the bus IDLE time-out interrupt is Enabled.
[3] CLKTOIEN Extended Clock Time Out Interrupt Enable Bit
0 = Indicates the time extended interrupt is Disabled.
1 = Indicates the time extended interrupt is Enabled.
[4] TORSTEN Time Out Reset Enable Bit
0 = Indicates the I2C state machine reset is Disable.
1 = Indicates the I2C state machine reset is Enable. (The clock and data bus will be released to high)
[5] PECIEN Packet Error Checking Byte Count Done Interrupt Enable Bit
0 = Indicates the byte count done interrupt is Disabled.
1 = Indicates the byte count done interrupt is Enabled.
Note: This bit is used in PECEN =1.

Definition at line 3718 of file M471M_R1_S.h.

◆ BUSTOUT

I2C_T::BUSTOUT

Offset: 0x58 I2C Bus Management Timer Register

Bits Field Descriptions
[7:0] BUSTO Bus Management Time-out Value
Indicate the bus time-out value in bus is IDLE or SCLK low.
Note: If the user wants to revise the value of BUSTOUT, the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and clear to 0 first in the BUSEN(I2C_BUSCTL[7]) is set.

Definition at line 3722 of file M471M_R1_S.h.

◆ CAL

RTC_T::CAL

Offset: 0x10 RTC Calendar Loading Register

Bits Field Descriptions
[3:0] DAY 1-Day Calendar Digit (0~9)
[5:4] TENDAY 10-Day Calendar Digit (0~3)
[11:8] MON 1-Month Calendar Digit (0~9)
[12] TENMON 10-Month Calendar Digit (0~1)
[19:16] YEAR 1-Year Calendar Digit (0~9)
[23:20] TENYEAR 10-Year Calendar Digit (0~9)

Definition at line 7641 of file M471M_R1_S.h.

◆ CALM

RTC_T::CALM

Offset: 0x20 Calendar Alarm Register

Bits Field Descriptions
[3:0] DAY 1-Day Calendar Digit of Alarm Setting (0~9)
[5:4] TENDAY 10-Day Calendar Digit of Alarm Setting (0~3)
[11:8] MON 1-Month Calendar Digit of Alarm Setting (0~9)
[12] TENMON 10-Month Calendar Digit of Alarm Setting (0~1)
[19:16] YEAR 1-Year Calendar Digit of Alarm Setting (0~9)
[23:20] TENYEAR 10-Year Calendar Digit of Alarm Setting (0~9)

Definition at line 7645 of file M471M_R1_S.h.

◆ CAMSK

RTC_T::CAMSK

Offset: 0x38 Calendar Alarm Mask Register

Bits Field Descriptions
[0] MDAY Mask 1-Day Calendar Digit of Alarm Setting (0~9)
[1] MTENDAY Mask 10-Day Calendar Digit of Alarm Setting (0~3)
[2] MMON Mask 1-Month Calendar Digit of Alarm Setting (0~9)
[3] MTENMON Mask 10-Month Calendar Digit of Alarm Setting (0~1)
[4] MYEAR Mask 1-Year Calendar Digit of Alarm Setting (0~9)
[5] MTENYEAR Mask 10-Year Calendar Digit of Alarm Setting (0~9)

Definition at line 7651 of file M471M_R1_S.h.

◆ CAP

TIMER_T::CAP

Offset: 0x10 Timer Capture Data Register

Bits Field Descriptions
[23:0] CAPDAT Timer Capture Data Register
When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT (TIMERx_CNT[23:0]) will be auto-loaded into this CAPDAT field.

Definition at line 11256 of file M471M_R1_S.h.

◆ CAPCTL

PWM_T::CAPCTL

Offset: 0x204 PWM Capture Control Register

Bits Field Descriptions
[5:0] CAPENn Capture Function Enable
Each bit n controls the corresponding PWM channel n.
0 = Capture function Disabled. RCAPDAT/FCAPDAT register will not be updated.
1 = Capture function Enabled.
Capture latched the PWM counter value when detected rising or falling edge of input signal and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
[13:8] CAPINVn Capture Inverter Enable
Each bit n controls the corresponding PWM channel n.
0 = Capture source inverter Disabled.
1 = Capture source inverter Enabled. Reverse the input signal from GPIO.
[21:16] RCRLDENn Rising Capture Reload Enable
Each bit n controls the corresponding PWM channel n.
0 = Rising capture reload counter Disabled.
1 = Rising capture reload counter Enabled.
[29:24] FCRLDENn Falling Capture Reload Enable
Each bit n controls the corresponding PWM channel n.
0 = Falling capture reload counter Disabled.
1 = Falling capture reload counter Enabled.

Definition at line 5871 of file M471M_R1_S.h.

◆ CAPIEN

PWM_T::CAPIEN

Offset: 0x250 PWM Capture Interrupt Enable Register

Bits Field Descriptions
[5:0] CAPRIENn PWM Capture Rising Latch Interrupt Enable
Each bit n controls the corresponding PWM channel n.
0 = Capture rising edge latch interrupt Disabled.
1 = Capture rising edge latch interrupt Enabled.
Note: When Capture with PDMA operating, CINTENR corresponding channel CAPRIEN must be disabled.
[13:8] CAPFIENn PWM Capture Falling Latch Interrupt Enable
Each bit n controls the corresponding PWM channel n.
0 = Capture falling edge latch interrupt Disabled.
1 = Capture falling edge latch interrupt Enabled.
Note: When Capture with PDMA operating, CINTENR corresponding channel CAPFIEN must be disabled.

Definition at line 5890 of file M471M_R1_S.h.

◆ CAPIF

PWM_T::CAPIF

Offset: 0x254 PWM Capture Interrupt Flag Register

Bits Field Descriptions
[5:0] CRLIFn PWM Capture Rising Latch Interrupt Flag
This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.
0 = No capture rising latch condition happened.
1 = Capture rising latch condition happened, this flag will be set to high.
Note: When Capture with PDMA operating, CIFR corresponding channel CRLIF will cleared by hardware after PDMA transfer data.
[13:8] CFLIFn PWM Capture Falling Latch Interrupt Flag
This bit is writing 1 to clear. Each bit n controls the corresponding PWM channel n.
0 = No capture falling latch condition happened.
1 = Capture falling latch condition happened, this flag will be set to high.
Note: When Capture with PDMA operating, CIFR corresponding channel CFLIF will cleared by hardware after PDMA transfer data.

Definition at line 5891 of file M471M_R1_S.h.

◆ CAPINEN

PWM_T::CAPINEN

Offset: 0x200 PWM Capture Input Enable Register

Bits Field Descriptions
[5:0] CAPINENn Capture Input Enable
Each bit n controls the corresponding PWM channel n.
0 = PWM Channel capture input path Disabled.
The input of PWM channel capture function is always regarded as 0.
1 = PWM Channel capture input path Enabled.
The input of PWM channel capture function comes from correlative multifunction pin.

Definition at line 5870 of file M471M_R1_S.h.

◆ CAPSTS

PWM_T::CAPSTS

Offset: 0x208 PWM Capture Status Register

Bits Field Descriptions
[5:0] CRLIFOVn Capture Rising Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if rising latch happened when the corresponding CRLIF is 1.
Each bit n controls the corresponding PWM channel n.
Note: This bit will be cleared automatically when user clear corresponding CRLIF.
[13:8] CFLIFOVn Capture Falling Latch Interrupt Flag Overrun Status (Read Only)
This flag indicates if falling latch happened when the corresponding CFLIF is 1.
Each bit n controls the corresponding PWM channel n.
Note: This bit will be cleared automatically when user clear corresponding CFLIF.

Definition at line 5872 of file M471M_R1_S.h.

◆ CDLOWB

CLK_T::CDLOWB

Offset: 0x7C Clock Frequency Detector Low Boundary Register

Bits Field Descriptions
[9:0] LOWERBD HXT Clock Frequency Detector Low Boundary
The bits define the low value of frequency monitor window.
When HXT frequency monitor value lower than this register, the HXT frequency detect fail interrupt flag will set to 1.

Definition at line 1433 of file M471M_R1_S.h.

◆ CDUPB

CLK_T::CDUPB

Offset: 0x78 Clock Frequency Detector Upper Boundary Register

Bits Field Descriptions
[9:0] UPERBD HXT Clock Frequency Detector Upper Boundary
The bits define the high value of frequency monitor window.
When HXT frequency monitor value higher than this register, the HXT frequency detect fail interrupt flag will set to 1.

Definition at line 1432 of file M471M_R1_S.h.

◆ CFG

USBD_EP_T::CFG

Offset: 0x508/0x518/0x528/0x538/0x548/0x558/0x568/0x578 Endpoint 0~7 Configuration Register

Bits Field Descriptions
[3:0] EPNUM Endpoint Number
These bits are used to define the endpoint number of the current endpoint.
[4] ISOCH Isochronous Endpoint
This bit is used to set the endpoint as Isochronous endpoint, no handshake.
0 = No Isochronous endpoint.
1 = Isochronous endpoint.
[6:5] STATE Endpoint STATE
00 = Endpoint is Disabled.
01 = Out endpoint.
10 = IN endpoint.
11 = Undefined.
[7] DSQSYNC Data Sequence Synchronization
0 = DATA0 PID.
1 = DATA1 PID.
Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction.
Hardware will toggle automatically in IN token base on the bit.
[9] CSTALL Clear STALL Response
0 = Disable the device to clear the STALL handshake in setup stage.
1 = Clear the device to response STALL handshake in setup stage.

Definition at line 12273 of file M471M_R1_S.h.

◆ CFGP

USBD_EP_T::CFGP

Offset: 0x50C/0x51C/0x52C/0x53C/0x54C/0x55C/0x56C/0x57C Endpoint 0~7 Set Stall and Clear In/Out Ready Control Register

Bits Field Descriptions
[0] CLRRDY Clear Ready
When the USB_MXPLD register is set by user, it means that the endpoint is ready to transmit or receive data.
If the user wants to turn off this transaction before the transaction start, users can set this bit to 1 to turn it off and it will be cleared to 0 automatically.
For IN token, write 1 to clear the IN token had ready to transmit the data to USB.
For OUT token, write 1 to clear the OUT token had ready to receive the data from USB.
This bit is write 1 only and is always 0 when it is read back.
[1] SSTALL Set STALL
0 = Disable the device to response STALL.
1 = Set the device to respond STALL automatically.

Definition at line 12274 of file M471M_R1_S.h.

◆ CHCTL

PDMA_T::CHCTL

Offset: 0x400 PDMA Channel Control Register

Bits Field Descriptions
[11:0] CHENn PDMA Channel Enable Bit
Set this bit to 1 to enable PDMAn operation.
If each channel is not set as enabled, each channel cannot be active.
0 = PDMA channel [n] Disabled.
1 = PDMA channel [n] Enabled.
Note1: If software stops each PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer.
Note2: Software reset (writing 0xFFFF_FFFF to PDMA_STOP register) will also clear this bit.

Definition at line 4325 of file M471M_R1_S.h.

◆ CHECKSUM

CRC_T::CHECKSUM

Offset: 0x0C CRC Checksum Register

Bits Field Descriptions
[31:0] CHECKSUM CRC Checksum Results
This field indicates the CRC checksum result.

Definition at line 1811 of file M471M_R1_S.h.

◆ CLKDCTL

CLK_T::CLKDCTL

Offset: 0x70 Clock Fail Detector Control Register

Bits Field Descriptions
[4] HXTFDEN HXT Clock Fail Detector Enable Bit
0 = HXT clock Fail detector Disabled.
1 = HXT clock Fail detector Enabled.
[5] HXTFIEN HXT Clock Fail Interrupt Enable Bit
0 = HXT clock Fail interrupt Disabled.
1 = HXT clock Fail interrupt Enabled.
[12] LXTFDEN LXT Clock Fail Detector Enable Bit
0 = LXT clock Fail detector Disabled.
1 = LXT clock Fail detector Enabled.
[13] LXTFIEN LXT Clock Fail Interrupt Enable Bit
0 = LXT clock Fail interrupt Disabled.
1 = LXT clock Fail interrupt Enabled.
[16] HXTFQDEN HXT Clock Frequency Monitor Enable Bit
0 = HXT clock frequency monitor Disabled.
1 = HXT clock frequency monitor Enabled.
[17] HXTFQIEN HXT Clock Frequency Monitor Interrupt Enable Bit
0 = HXT clock frequency monitor fail interrupt Disabled.
1 = HXT clock frequency monitor fail interrupt Enabled.

Definition at line 1430 of file M471M_R1_S.h.

◆ CLKDIV [1/2]

I2C_T::CLKDIV

Offset: 0x10 I2C Clock Divided Register

Bits Field Descriptions
[7:0] DIVIDER I2C Clock Divided
Indicates the I2C clock rate: Data Baud Rate of I2C = (system clock) / (4x (I2C_CLKDIV+1)).
Note: The minimum value of I2C_CLKDIV is 4.

Definition at line 3705 of file M471M_R1_S.h.

◆ CLKDIV [2/2]

SPI_T::CLKDIV

Offset: 0x04 Clock Divider Register

Bits Field Descriptions
[7:0] DIVIDER Clock Divider
The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI master.
The frequency is obtained according to the following equation.
fspi_eclk = fspi_clock_src / (DIVIDER + 1)
where fspi_clock_src is the peripheral clock source, which is defined in the clock control register CLK_CLKSEL2.

Definition at line 9306 of file M471M_R1_S.h.

◆ CLKDIV0

CLK_T::CLKDIV0

Offset: 0x20 Clock Divider Number Register 0

Bits Field Descriptions
[3:0] HCLKDIV HCLK Clock Divide Number From HCLK Clock Source
HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1).
[7:4] USBDIV USB Clock Divide Number From PLL Clock
USB clock frequency = (PLL frequency) / (USBDIV + 1).
[11:8] UARTDIV UART Clock Divide Number From UART Clock Source
UART clock frequency = (UART clock source frequency) / (UARTDIV + 1).
[23:16] EADCDIV EADC Clock Divide Number From EADC Clock Source
EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1).

Definition at line 1421 of file M471M_R1_S.h.

◆ CLKDIV1

CLK_T::CLKDIV1

Offset: 0x24 Clock Divider Number Register 1

Bits Field Descriptions
[7:0] SC0DIV SC0 Clock Divide Number From SC0 Clock Source
SC0 clock frequency = (SC0 clock source frequency ) / (SC0DIV + 1).

Definition at line 1422 of file M471M_R1_S.h.

◆ CLKDSTS

CLK_T::CLKDSTS

Offset: 0x74 Clock Fail Detector Status Register

Bits Field Descriptions
[0] HXTFIF HXT Clock Fail Interrupt Flag
0 = HXT clock normal.
1 = HXT clock stop
Note: Write 1 to clear the bit to 0.
[1] LXTFIF LXT Clock Fail Interrupt Flag
0 = LXT clock normal.
1 = LXT stop
Note: Write 1 to clear the bit to 0.
[8] HXTFQIF HXT Clock Frequency Monitor Interrupt Flag
0 = HXT clock normal.
1 = HXT clock frequency abnormal
Note: Write 1 to clear the bit to 0.

Definition at line 1431 of file M471M_R1_S.h.

◆ CLKFMT

RTC_T::CLKFMT

Offset: 0x14 Time Scale Selection Register

Bits Field Descriptions
[0] 24HEN 24-Hour / 12-Hour Time Scale Selection
Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale
0 = 12-hour time scale with AM and PM indication selected.
1 = 24-hour time scale selected.

Definition at line 7642 of file M471M_R1_S.h.

◆ CLKOCTL

CLK_T::CLKOCTL

Offset: 0x60 Clock Output Control Register

Bits Field Descriptions
[3:0] FREQSEL Clock Output Frequency Selection
The formula of output frequency is
Fout = Fin/2(N+1).
Fin is the input clock frequency.
Fout is the frequency of divider output clock.
N is the 4-bit value of FREQSEL[3:0].
[4] CLKOEN Clock Output Enable Bit
0 =Clock Output function Disabled.
1 = Clock Output function Enabled.
[5] DIV1EN Clock Output Divide One Enable Bit
0 = Clock Output will output clock with source frequency divided by FREQSEL.
1 = Clock Output will output clock with source frequency.
[6] CLK1HZEN Clock Output 1Hz Enable Bit
0 = 1 Hz clock output for 32.768kHz frequency compensation Disabled.
1 = 1 Hz clock output for 332.768kHz frequency compensation Enabled.

Definition at line 1428 of file M471M_R1_S.h.

◆ CLKPSC0_1

PWM_T::CLKPSC0_1

Offset: 0x14 PWM Clock Pre-scale Register 0

Bits Field Descriptions
[11:0] CLKPSC PWM Counter Clock Pre-Scale
The clock of PWM counter is decided by clock prescaler.
Each PWM pair share one PWM counter clock prescaler.
The clock of PWM counter is divided by (CLKPSC+ 1).

Definition at line 5820 of file M471M_R1_S.h.

◆ CLKPSC2_3

PWM_T::CLKPSC2_3

Offset: 0x18 PWM Clock Pre-scale Register 2

Bits Field Descriptions
[11:0] CLKPSC PWM Counter Clock Pre-Scale
The clock of PWM counter is decided by clock prescaler.
Each PWM pair share one PWM counter clock prescaler.
The clock of PWM counter is divided by (CLKPSC+ 1).

Definition at line 5821 of file M471M_R1_S.h.

◆ CLKPSC4_5

PWM_T::CLKPSC4_5

Offset: 0x1C PWM Clock Pre-scale Register 4

Bits Field Descriptions
[11:0] CLKPSC PWM Counter Clock Pre-Scale
The clock of PWM counter is decided by clock prescaler.
Each PWM pair share one PWM counter clock prescaler.
The clock of PWM counter is divided by (CLKPSC+ 1).

Definition at line 5822 of file M471M_R1_S.h.

◆ CLKSEL0

CLK_T::CLKSEL0

Offset: 0x10 Clock Source Select Control Register 0

Bits Field Descriptions
[2:0] HCLKSEL HCLK Clock Source Selection (Write Protect)
Before clock switching, the related clock sources (both pre-select and new-select) must be turned on.
The default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration register of Flash controller by any reset.
Therefore the default value is either 000b or 111b.
000 = Clock source from external 4~24 MHz high-speed crystal clock.
001 = Clock source from external 32.768 kHz low-speed crystal clock.
010 = Clock source from PLL clock.
011 = Clock source from internal 10 kHz low-speed oscillator clock.
111= Clock source from internal 22.1184 MHz high-speed oscillator clock.
Other = Reserved.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[5:3] STCLKSEL Cortex-M4 SysTick Clock Source Selection (Write Protect)
If SYST_CTRL[2]=0, SysTick uses listed clock source below.
000 = Clock source from external 4~24 MHz high-speed crystal clock.
001 = Clock source from external 32.768 kHz low-speed crystal clock.
010 = Clock source from external 4~24 MHz high-speed crystal clock/2.
011 = Clock source from HCLK/2.
111 = Clock source from internal 22.1184 MHz high-speed oscillator clock/2.
Note: if SysTick clock source is not from HCLK (i.e.
SYST_CTRL[2] = 0), SysTick clock source must less than or equal to HCLK/2.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[6] PCLK0SEL PCLK0 Clock Source Selection (Write Protect)
0 = APB0 BUS clock source from HCLK.
1 = APB0 BUS clock source from HCLK/2.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[7] PCLK1SEL PCLK1 Clock Source Selection (Write Protect)
0 = APB1 BUS clock source from HCLK.
1 = APB1 BUS clock source from HCLK/2.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[8] USBCKSEL USB Clock Source Selection (Write Protect)
0 = USBH and USBD clock source from PLL.
1 = USBH and USBD clock source from HIRC48M.

Definition at line 1417 of file M471M_R1_S.h.

◆ CLKSEL1

CLK_T::CLKSEL1

Offset: 0x14 Clock Source Select Control Register 1

Bits Field Descriptions
[1:0] WDTSEL Watchdog Timer Clock Source Selection (Write Protect)
00 = Reserved.
01 = Clock source from external 32.768 kHz low-speed crystal clock.
10 = Clock source from HCLK/2048 clock.
11 = Clock source from internal 10 kHz low-speed oscillator clock.
[10:8] TMR0SEL TIMER0 Clock Source Selection
000 = Clock source from external 4~24 MHz high-speed crystal clock.
001 = Clock source from external 32.768 kHz low-speed crystal clock.
010 = Clock source from PCLK0.
011 = Clock source from external clock T0 pin
101 = Clock source from internal 10 kHz low-speed oscillator clock.
111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
Others = Reserved.
[14:12] TMR1SEL TIMER1 Clock Source Selection
000 = Clock source from external 4~24 MHz high-speed crystal clock.
001 = Clock source from external 32.768 kHz low-speed crystal clock.
010 = Clock source from PCLK0.
011 = Clock source from external clock T1 pin
101 = Clock source from internal 10 kHz low-speed oscillator clock.
111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
Others = Reserved.
[18:16] TMR2SEL TIMER2 Clock Source Selection
000 = Clock source from external 4~24 MHz high-speed crystal clock.
001 = Clock source from external 32.768 kHz low-speed crystal clock.
010 = Clock source from PCLK1.
011 = Clock source from external clock T2 pin
101 = Clock source from internal 10 kHz low-speed oscillator clock.
111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
Others = Reserved.
[22:20] TMR3SEL TIMER3 Clock Source Selection
000 = Clock source from external 4~24 MHz high-speed crystal clock.
001 = Clock source from external 32.768 kHz low-speed crystal clock.
010 = Clock source from PCLK1.
011 = Clock source from external clock T3 pin.
101 = Clock source from internal 10 kHz low-speed oscillator clock.
111 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
Others = Reserved.
[25:24] UARTSEL UART Clock Source Selection
00 = Clock source from external 4~24 MHz high-speed crystal clock (HXT).
01 = Clock source from PLL clock.
10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
11 = Clock source from internal 22.1184 MHz high-speed oscillator clock (HIRC).
[29:28] CLKOSEL Clock Divider Clock Source Selection
00 = Clock source from external 4~24 MHz high-speed crystal clock.
01 = Clock source from external 32.768 kHz low-speed crystal clock.
10 = Clock source from HCLK.
11 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
[31:30] WWDTSEL Window Watchdog Timer Clock Source Selection
10 = Clock source from HCLK/2048 clock.
11 = Clock source from internal 10 kHz low-speed oscillator clock.
Others = Reserved.

Definition at line 1418 of file M471M_R1_S.h.

◆ CLKSEL2

CLK_T::CLKSEL2

Offset: 0x18 Clock Source Select Control Register 2

Bits Field Descriptions
[0] PWM0SEL PWM0 Clock Source Selection
The peripheral clock source of PWM0 is defined by PWM0SEL.
0 = Clock source from PLL clock.
1 = Clock source from PCLK0.
[1] PWM1SEL PWM1 Clock Source Selection
The peripheral clock source of PWM1 is defined by PWM1SEL.
0 = Clock source from PLL clock.
1 = Clock source from PCLK1.
[3:2] SPI0SEL SPI0 Clock Source Selection
00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
01 = Clock source from PLL clock.
10 = Clock source from PCLK0.
11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
[5:4] SPI1SEL SPI1 Clock Source Selection
00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
01 = Clock source from PLL clock.
10 = Clock source from PCLK1.
11 = Clock source from internal 22.1184 MHz high speed oscillator clock.

Definition at line 1419 of file M471M_R1_S.h.

◆ CLKSEL3

CLK_T::CLKSEL3

Offset: 0x1C Clock Source Select Control Register 3

Bits Field Descriptions
[1:0] SC0SEL SC0 Clock Source Selection
00 = Clock source from external 4~24 MHz high-speed crystal clock.
01 = Clock source from PLL clock.
10 = Clock source from PCLK0.
11 = Clock source from internal 22.1184 MHz high-speed oscillator clock.
[8] RTCSEL RTC Clock Source Selection
0 = Clock source from external 32.768 kHz low-speed oscillator.
1 = Clock source from internal 10 kHz low speed RC oscillator.

Definition at line 1420 of file M471M_R1_S.h.

◆ CLKSRC

PWM_T::CLKSRC

Offset: 0x10 PWM Clock Source Register

Bits Field Descriptions
[2:0] ECLKSRC0 PWM_CH01 External Clock Source Select
000 = PWMx_CLK, x denotes 0 or 1.
001 = TIMER0 overflow.
010 = TIMER1 overflow.
011 = TIMER2 overflow.
100 = TIMER3 overflow.
Others = Reserved.
[10:8] ECLKSRC2 PWM_CH23 External Clock Source Select
000 = PWMx_CLK, x denotes 0 or 1.
001 = TIMER0 overflow.
010 = TIMER1 overflow.
011 = TIMER2 overflow.
100 = TIMER3 overflow.
Others = Reserved.
[18:16] ECLKSRC4 PWM_CH45 External Clock Source Select
000 = PWMx_CLK, x denotes 0 or 1.
001 = TIMER0 overflow.
010 = TIMER1 overflow.
011 = TIMER2 overflow.
100 = TIMER3 overflow.
Others = Reserved.

Definition at line 5819 of file M471M_R1_S.h.

◆ CLKTOUT

I2C_T::CLKTOUT

Offset: 0x5C I2C Bus Management Clock Low Timer Register

Bits Field Descriptions
[7:0] CLKTO Bus Clock Low Timer
The field is used to configure the cumulative clock extension time-out.
Note: If the user wants to revise the value of CLKLTOUT, the TORSTEN bit shall be set to 1 and d clear to 0 first in the BUSEN is set.

Definition at line 3723 of file M471M_R1_S.h.

◆ CMP [1/2]

EADC_T::CMP

Offset: 0xEC A/D Result Compare Register n, n=0~3

Bits Field Descriptions
[0] ADCMPEN A/D Result Compare Enable Bit
0 = Compare Disabled.
1 = Compare Enabled.
Set this bit to 1 to enable compare CMPDAT (EADC_CMPn[27:16], n=0~3) with specified sample module conversion result when converted data is loaded into EADC_DAT register.
[1] ADCMPIE A/D Result Compare Interrupt Enable Bit
0 = Compare function interrupt Disabled.
1 = Compare function interrupt Enabled.
If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated.
[2] CMPCOND Compare Condition
0= Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPDAT (EADC_CMPn
[27:16]), the internal match counter will increase one.
1= Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPn [27:16]), the internal match counter will increase one.
Note: When the internal counter reaches the value to (CMPMCNT (EADC_CMPn[11:8], n=0~3) +1), the CMPF bit will be set.
[7:3] CMPSPL Compare Sample Module Selection
00000 = Sample Module 0 conversion result EADC_DAT0 is selected to be compared.
00001 = Sample Module 1 conversion result EADC_DAT1 is selected to be compared.
00010 = Sample Module 2 conversion result EADC_DAT2 is selected to be compared.
00011 = Sample Module 3 conversion result EADC_DAT3 is selected to be compared.
00100 = Sample Module 4 conversion result EADC_DAT4 is selected to be compared.
00101 = Sample Module 5 conversion result EADC_DAT5 is selected to be compared.
00110 = Sample Module 6 conversion result EADC_DAT6 is selected to be compared.
00111 = Sample Module 7 conversion result EADC_DAT7 is selected to be compared.
01000 = Sample Module 8 conversion result EADC_DAT8 is selected to be compared.
01001 = Sample Module 9 conversion result EADC_DAT9 is selected to be compared.
01010 = Sample Module 10 conversion result EADC_DAT10 is selected to be compared.
01011 = Sample Module 11 conversion result EADC_DAT11 is selected to be compared.
01100 = Sample Module 12 conversion result EADC_DAT12 is selected to be compared.
01101 = Sample Module 13 conversion result EADC_DAT13 is selected to be compared.
01110 = Sample Module 14 conversion result EADC_DAT14 is selected to be compared.
01111 = Sample Module 15 conversion result EADC_DAT15 is selected to be compared.
10000 = Sample Module 16 conversion result EADC_DAT16 is selected to be compared.
10001 = Sample Module 17 conversion result EADC_DAT17 is selected to be compared.
10010 = Sample Module 18 conversion result EADC_DAT18 is selected to be compared.
[11:8] CMPMCNT Compare Match Count
When the specified A/D sample module analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPn[2], n=0~3), the internal match counter will increase 1.
If the compare result does not meet the compare condition, the internal compare match counter will reset to 0.
When the internal counter reaches the value to (CMPMCNT +1), the ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be set.
[15] CMPWEN Compare Window Mode Enable Bit
0 = ADCMPF0 (EADC_STATUS2[4]) will be set when EADC_CMP0 compared condition matched.
ADCMPF2 (EADC_STATUS2[6]) will be set when EADC_CMP2 compared condition matched.
1 = ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched.
ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.
Note: This bit is only present in EADC_CMP0 and EADC_CMP2 register.
[27:16] CMPDAT Comparison Data
The 12 bits data is used to compare with conversion result of specified sample module.
User can use it to monitor the external analog input pin voltage transition without imposing a load on software.

Definition at line 731 of file M471M_R1_S.h.

◆ CMP [2/2]

TIMER_T::CMP

Offset: 0x04 Timer Compare Register

Bits Field Descriptions
[23:0] CMPDAT Timer Compared Value
CMPDAT is a 24-bit compared value register.
When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will set to 1.
Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT).
Note1: Never write 0x0 or 0x1 in CMPDAT field, or the core will run into unknown state.
Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if user writes a new value into CMPDAT field.
But if timer is operating at other modes, the 24-bit up counter will restart counting from 0 and using newest CMPDAT value to be the timer compared value while user writes a new value into CMPDAT field.

Definition at line 11253 of file M471M_R1_S.h.

◆ CMPBUF

PWM_T::CMPBUF

Offset: 0x31C~0x330 PWM CMPDAT0~5 Buffer

Bits Field Descriptions
[15:0] CMPBUF PWM Comparator Register Buffer
(Read Only)
Used as CMP active register.

Definition at line 5894 of file M471M_R1_S.h.

◆ CMPDAT

PWM_T::CMPDAT

Offset: 0x50~0x64 PWM Comparator Register 0~5

Bits Field Descriptions
[15:0] CMP PWM Comparator Register
CMP use to compare with CNTR to generate PWM waveform, interrupt and trigger EADC.
In independent mode, CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.
In complementary mode, CMPDAT0, 2, 4 denote as first compared point, and CMPDAT1, 3, 5 denote as second compared point for the corresponding 3 complementary pairs PWM_CH0 and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.

Definition at line 5829 of file M471M_R1_S.h.

◆ CNT [1/3]

PWM_T::CNT

Offset: 0x90~0xA4 PWM Counter Register 0~5

Bits Field Descriptions
[15:0] CNT PWM Data Register (Read Only)
User can monitor CNTR to know the current value in 16-bit period counter.
[16] DIRF PWM Direction Indicator Flag (Read Only)
0 = Counter is Down count.
1 = Counter is UP count.

Definition at line 5839 of file M471M_R1_S.h.

◆ CNT [2/3]

TIMER_T::CNT

Offset: 0x0C Timer Data Register

Bits Field Descriptions
[23:0] CNT Timer Data Register
This field can be reflected the internal 24-bit timer counter value or external event input counter value from Tx_CNT (x=0~3) pin.
If EXTCNTEN (TIMERx_CTL[24] ) is 0, user can read CNT value for getting current 24- bit counter value .
If EXTCNTEN (TIMERx_CTL[24] ) is 1, user can read CNT value for getting current 24- bit event input counter value.

Definition at line 11255 of file M471M_R1_S.h.

◆ CNT [3/3]

WWDT_T::CNT

Offset: 0x0C WWDT Counter Value Register

Bits Field Descriptions
[5:0] CNTDAT WWDT Counter Value
CNTDAT will be updated continuously to monitor 6-bit WWDT down counter value.

Definition at line 13704 of file M471M_R1_S.h.

◆ CNTCLR

PWM_T::CNTCLR

Offset: 0x24 PWM Clear Counter Register

Bits Field Descriptions
[5:0] CNTCLRn Clear PWM Counter Control Bit
It is automatically cleared by hardware. Each bit n controls the corresponding PWM channel n.
0 = No effect.
1 = Clear 16-bit PWM counter to 0000H.

Definition at line 5824 of file M471M_R1_S.h.

◆ CNTEN

PWM_T::CNTEN

Offset: 0x20 PWM Counter Enable Register

Bits Field Descriptions
[5:0] CNTENn PWM Counter Enable
Each bit n controls the corresponding PWM channel n.
0 = PWM Counter and clock prescaler Stop Running.
1 = PWM Counter and clock prescaler Start Running.

Definition at line 5823 of file M471M_R1_S.h.

◆ CTL [1/9]

EADC_T::CTL

Offset: 0x50 A/D Control Register

Bits Field Descriptions
[0] ADCEN A/D Converter Enable Bit
0 = Disabled.
1 = Enabled.
Note: Before starting A/D conversion function, this bit should be set to 1.
Clear it to 0 to disable A/D converter analog circuit power consumption.
[1] ADCRST ADC A/D Converter Control Circuits Reset
0 = No effect.
1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value.
Note: ADCRST bit remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0.
[2] ADCIEN0 Specific Sample Module A/D ADINT0 Interrupt Enable Bit
The A/D converter generates a conversion end ADIF0 (EADC_STATUS2[0]) upon the end of specific sample module A/D conversion.
If ADCIEN0 bit is set then conversion end interrupt request ADINT0 is generated.
0 = Specific sample module A/D ADINT0 interrupt function Disabled.
1 = Specific sample module A/D ADINT0 interrupt function Enabled.
[3] ADCIEN1 Specific Sample Module A/D ADINT1 Interrupt Enable Bit
The A/D converter generates a conversion end ADIF1 (EADC_STATUS2[1]) upon the end of specific sample module A/D conversion.
If ADCIEN1 bit is set then conversion end interrupt request ADINT1 is generated.
0 = Specific sample module A/D ADINT1 interrupt function Disabled.
1 = Specific sample module A/D ADINT1 interrupt function Enabled.
[4] ADCIEN2 Specific Sample Module A/D ADINT2 Interrupt Enable Bit
The A/D converter generates a conversion end ADIF2 (EADC_STATUS2[2]) upon the end of specific sample module A/D conversion.
If ADCIEN2 bit is set then conversion end interrupt request ADINT2 is generated.
0 = Specific sample module A/D ADINT2 interrupt function Disabled.
1 = Specific sample module A/D ADINT2 interrupt function Enabled.
[5] ADCIEN3 Specific Sample Module A/D ADINT3 Interrupt Enable Bit
The A/D converter generates a conversion end ADIF3 (EADC_STATUS2[3]) upon the end of specific sample module A/D conversion.
If ADCIEN3 bit is set then conversion end interrupt request ADINT3 is generated.
0 = Specific sample module A/D ADINT3 interrupt function Disabled.
1 = Specific sample module A/D ADINT3 interrupt function Enabled.
[8] DIFFEN Differential Analog Input Mode Enable Bit
0 = Single-end analog input mode.
1 = Differential analog input mode.
[9] DMOF ADC Differential Input Mode Output Format
0 = A/D conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with unsigned format.
1 = A/D conversion result will be filled in RESULT (EADC_DATn[15:0] , n= 0 ~18) with 2'complement format.
[11] PDMAEN PDMA Transfer Enable Bit
When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request.
0 = PDMA data transfer Disabled.
1 = PDMA data transfer Enabled.
Note: When set this bit field to 1, user must set ADCIENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt.
[18:16] SMPTSEL ADC Internal Sampling Time Selection
ADC internal sampling cycle = SMPTSEL + 1.
000 = 1 ADC clock sampling time.
001 = 2 ADC clock sampling time.
010 = 3 ADC clock sampling time.
011 = 4 ADC clock sampling time.
100 = 5 ADC clock sampling time.
101 = 6 ADC clock sampling time.
110 = 7 ADC clock sampling time.
111 = 8 ADC clock sampling time.

Definition at line 723 of file M471M_R1_S.h.

◆ CTL [2/9]

CRC_T::CTL

Offset: 0x00 CRC Control Register

Bits Field Descriptions
[0] CRCEN CRC Channel Enable Bit
0 = No effect.
1 = CRC operation Enabled.
[1] CRCRST CRC Engine Reset
0 = No effect.
1 = Reset the internal CRC state machine and internal buffer.
The others contents of CRC_CTL register will not be cleared.
Note1: This bit will be cleared automatically.
Note2: Setting this bit will reload the initial seed value (CRC_SEED register).
[24] DATREV Write Data Bit Order Reverse
This bit is used to enable the bit order reverse function for write data value in CRC_DAT register.
0 = Bit order reversed for CRC write data in Disabled.
1 = Bit order reversed for CRC write data in Enabled (per byte).
Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB.
[25] CHKSREV Checksum Bit Order Reverse
This bit is used to enable the bit order reverse function for write data value in CRC_CHECKSUM register.
0 = Bit order reverse for CRC checksum Disabled.
1 = Bit order reverse for CRC checksum Enabled.
Note: If the checksum result is 0xDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB.
[26] DATFMT Write Data 1's Complement
This bit is used to enable the 1's complement function for write data value in CRC_DAT register.
0 = 1's complement for CRC writes data in Disabled.
1 = 1's complement for CRC writes data in Enabled.
[27] CHKSFMT Checksum 1's Complement
This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
0 = 1's complement for CRC checksum Disabled.
1 = 1's complement for CRC checksum Enabled.
[29:28] DATLEN CPU Write Data Length
This field indicates the write data length.
00 = Data length is 8-bit mode.
01 = Data length is 16-bit mode.
1x = Data length is 32-bit mode.
Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0]
[31:30] CRCMODE CRC Polynomial Mode
This field indicates the CRC operation polynomial mode.
00 = CRC-CCITT Polynomial mode.
01 = CRC-8 Polynomial mode.
10 = CRC-16 Polynomial mode.
11 = CRC-32 Polynomial mode.

Definition at line 1808 of file M471M_R1_S.h.

◆ CTL [3/9]

I2C_T::CTL

Offset: 0x00 I2C Control Register

Bits Field Descriptions
[2] AA Assert Acknowledge Control
When AA =1 prior to address or data is received,
an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when
1. A slave is acknowledging the address sent from master.
2. The receiver devices are acknowledging the data sent by transmitter.
When AA=0 prior to address or data received,
a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
[3] SI I2C Interrupt Flag
When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware.
If bit INTEN (I2C_CTL [7]) is set, the I2C interrupt is requested.
SI must be cleared by software.
Clear SI by writing 1 to this bit.
For ACKMEN is set in slave read mode, the SI flag is set in 8th clock period for user to confirm the acknowledge bit and 9th clock period for user to read the data in the data buffer.
[4] STO I2C STOP Control
In Master mode, setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected.
This bit will be cleared by hardware automatically.
[5] STA I2C START Control
Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
[6] I2CEN I2C Controller Enable Bit
Set to enable I2C serial function controller.
When I2CEN=1 the I2C serial function enable.
The multi-function pin function must set to SDA, and SCL of I2C function first.
0 = Disabled.
1 = Enabled.
[7] INTEN Enable Interrupt
0 = I2C interrupt Disabled.
1 = I2C interrupt Enabled.

Definition at line 3701 of file M471M_R1_S.h.

◆ CTL [4/9]

DSCT_T::CTL

Offset: 0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70/0x80/0x90/0xA0/0xB0 Descriptor Table Control Register of PDMA Channel 0~11

Bits Field Descriptions
[1:0] OPMODE PDMA Operation Mode Selection
0 = Idle state: Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to idle state automatically.
1 = Basic mode: The descriptor table only has one task.
When this task is finished, the PDMA_INTSTS[x] will be asserted.
2 = Scatter-Gather mode: When operating in this mode, user must give the next descriptor table address in PDMA_DSCT_NEXT register; PDMA controller will ignore this task, then load the next task to execute.
3 = Reserved.
Note: Before filling transfer task in the Descriptor Table, user must check if the descriptor table is complete.
[2] TXTYPE Transfer Type
0 = Burst transfer type.
1 = Single transfer type.
[6:4] BURSIZE Burst Size
This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.
000 = 128 Transfers.
001 = 64 Transfers.
010 = 32 Transfers.
011 = 16 Transfers.
100 = 8 Transfers.
101 = 4 Transfers.
110 = 2 Transfers.
111 = 1 Transfers.
Note: This field is only useful in burst transfer type.
[7] TBINTDIS Table Interrupt Disable
This field can be used to decide whether to enable table interrupt or not.
If the TBINTDIS bit is enabled when PDMA controller finishes transfer task, it will not generates interrupt.
0 = Table interrupt Enabled.
1 = Table interrupt Disabled.
Note: If this bit set to '1', the TEMPTYF will not be set.
[9:8] SAINC Source Address Increment
This field is used to set the source address increment size.
11 = No increment (fixed address).
Others = Increment and size is depended on TXWIDTH selection.
[11:10] DAINC Destination Address Increment
This field is used to set the destination address increment size.
11 = No increment (fixed address).
Others = Increment and size is depended on TXWIDTH selection.
[13:12] TXWIDTH Transfer Width Selection
This field is used for transfer width.
00 = One byte (8 bit) is transferred for every operation.
01= One half-word (16 bit) is transferred for every operation.
10 = One word (32-bit) is transferred for every operation.
11 = Reserved.
Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection
[29:16] TXCNT Transfer Count
The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
Note: When PDMA finish each transfer data, this field will be decrease immediately.

Definition at line 3992 of file M471M_R1_S.h.

◆ CTL [5/9]

SC_T::CTL

Offset: 0x04 SC Control Register.

Bits Field Descriptions
[0] SCEN SC Engine Enable Bit
Set this bit to 1 to enable SC operation.
If this bit is cleared, SC will force all transition to IDLE state.
[1] RXOFF RX Transition Disable Control
0 = The receiver Enabled.
1 = The receiver Disabled.
Note:
If AUTOCEN (SC_CTL[3])is enabled, these fields must be ignored.
[2] TXOFF TX Transition Disable Control
0 = The transceiver Enabled.
1 = The transceiver Disabled.
[3] AUTOCEN Auto Convention Enable Bit
0 = Auto-convention Disabled.
1 = Auto-convention Enabled.
When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11.
If software enables auto convention function, the setting step must be done before Answer to Reset state and the first data must be 0x3B or 0x3F.
After hardware received first data and stored it at buffer,
hardware will decided the convention and change the CONSEL (SC_CTL[5:4]) bits automatically.
If the first data is not 0x3B or 0x3F, hardware will generate an interrupt if ACERRIEN (SC_INTEN[10]) = 1 to CPU.
[5:4] CONSEL Convention Selection
00 = Direct convention.
01 = Reserved.
10 = Reserved.
11 = Inverse convention.
Note:
If AUTOCEN(SC_CTL[3]) enabled, this fields are ignored.
[7:6] RXTRGLV Rx Buffer Trigger Level
When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set (if SC_INTEN [RDAIEN] is enabled, an interrupt will be generated).
00 = INTR_RDA Trigger Level with 01 Bytes.
01 = INTR_RDA Trigger Level with 02 Bytes.
10 = INTR_RDA Trigger Level with 03 Bytes.
11 = Reserved.
[12:8] BGT Block Guard Time (BGT)
Block guard time means the minimum bit length between the leading edges of two consecutive characters between different transfer directions.
This field indicates the counter for the bit length of block guard time.
According to ISO7816-3, in T = 0 mode, software must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, software must fill 21 (real block guard time = 22.5) to it.
Note:
The real block guard time is BGT + 1.
[14:13] TMRSEL Timer Selection
00 = All internal timer function Disabled.
01 = Internal 24 bit timer Enabled.
Software can configure it by setting SC_TMRCTL0 [23:0].
SC_TMRCTL1 and SC_TMRCTL2 will be ignored in this mode.
10 = internal 24 bit timer and 8 bit internal timer Enabled.
Software can configure the 24 bit timer by setting SC_TMRCTL0 [23:0] and configure the 8 bit timer by setting SC_TMRCTL1[7:0].
SC_TMRCTL2 will be ignored in this mode.
11 = Internal 24 bit timer and two 8 bit timers Enabled.
Software can configure them by setting SC_TMRCTL0 [23:0], SC_TMRCTL1 [7:0] and SC_TMRCTL2 [7:0].
[15] NSB Stop Bit Length
This field indicates the length of stop bit.
0 = The stop bit length is 2 ETU.
1= The stop bit length is 1 ETU.
Note:
The default stop bit length is 2. SMC and UART adopts NSB to program the stop bit length
[18:16] RXRTY RX Error Retry Count Number
This field indicates the maximum number of receiver retries that are allowed when parity error has occurred
Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.
Note2: This field cannot be changed when RXRTYEN enabled.
The change flow is to disable RXRTYEN first and then fill in new retry value.
[19] RXRTYEN RX Error Retry Enable Bit
This bit enables receiver retry function when parity error has occurred.
0 = RX error retry function Disabled.
1 = RX error retry function Enabled.
Note:
Software must fill in the RXRTY value before enabling this bit.
[22:20] TXRTY TX Error Retry Count Number
This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.
Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.
Note2: This field cannot be changed when TXRTYEN enabled.
The change flow is to disable TXRTYEN first and then fill in new retry value.
[23] TXRTYEN TX Error Retry Enable Bit
This bit enables transmitter retry function when parity error has occurred.
0 = TX error retry function Disabled.
1 = TX error retry function Enabled.
[25:24] CDDBSEL Card Detect De-Bounce Selection
This field indicates the card detect de-bounce selection.
00 = De-bounce sample card insert once per 384 (128 * 3) peripheral clocks and de-bounce sample card removal once per 128 peripheral clocks.
01 = De-bounce sample card insert once per 192 (64 * 3) peripheral clocks and de-bounce sample card removal once per 64 peripheral clocks.
10 = De-bounce sample card insert once per 96 (32 * 3) peripheral clocks and de-bounce sample card removal once per 32 peripheral clocks.
11 = De-bounce sample card insert once per 48 (16 * 3) peripheral clocks and de-bounce sample card removal once per 16 peripheral clocks.
[26] CDLV Card Detect Level
0 = When hardware detects the card detect pin (SC_CD) from high to low, it indicates a card is detected.
1 = When hardware detects the card detect pin from low to high, it indicates a card is detected.
Note: Software must select card detect level before Smart Card engine enabled.
[30] SYNC SYNC Flag Indicator
Due to synchronization, software should check this bit before writing a new value to RXRTY and TXRTY.
0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY.
1 = Last value is synchronizing.
Note: This bit is read only.
[31] ICEDEBUG ICE Debug Mode Acknowledge Disable Control
0 = ICE debug mode acknowledgement affects SC counting.
SC internal counter will be held while CPU is held by ICE.
1 = ICE debug mode acknowledgement Disabled.
SC internal counter will keep going no matter CPU is held by ICE or not.

Definition at line 8493 of file M471M_R1_S.h.

◆ CTL [6/9]

SPI_T::CTL

Offset: 0x00 Control Register

Bits Field Descriptions
[0] SPIEN SPI Transfer Control Enable Bit
In Master mode, the transfer will start when there is data in the FIFO buffer after this is set to 1.
In Slave mode, this device is ready to receive data when this bit is set to 1.
0 = Transfer control Disabled.
1 = Transfer control Enabled.
Note: Before changing the configurations of SPI_CTL, SPI_CLKDIV, SPI_SSCTL and SPI_FIFOCTL registers, user shall clear the SPIEN (SPI_CTL[0]) and confirm the SPIENSTS (SPI_STATUS[15]) is 0.
[1] RXNEG Receive On Negative Edge
0 = Received data input signal is latched on the rising edge of SPI bus clock.
1 = Received data input signal is latched on the falling edge of SPI bus clock.
[2] TXNEG Transmit On Negative Edge
0 = Transmitted data output signal is changed on the rising edge of SPI bus clock.
1 = Transmitted data output signal is changed on the falling edge of SP bus clock.
[3] CLKPOL Clock Polarity
0 = SPI bus clock is idle low.
1 = SPI bus clock is idle high.
[7:4] SUSPITV Suspend Interval (Master Only)
The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer.
The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word.
The default value is 0x3.
The period of the suspend interval is obtained according to the following equation.
(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
Example:
SUSPITV = 0x0 ... 0.5 SPICLK clock cycle.
SUSPITV = 0x1 ... 1.5 SPICLK clock cycle.
...
SUSPITV = 0xE ... 14.5 SPICLK clock cycle.
SUSPITV = 0xF ... 15.5 SPICLK clock cycle.
[12:8] DWIDTH Data Width
This field specifies how many bits can be transmitted / received in one transaction.
The minimum bit length is 8 bits and can up to 32 bits.
DWIDTH = 0x08 ... 8 bits.
DWIDTH = 0x09 ... 9 bits.
...
DWIDTH = 0x1F ... 31 bits.
DWIDTH = 0x00 ... 32 bits.
[13] LSB Send LSB First
0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX).
[16] TWOBIT 2-Bit Transfer Mode Enable Bit (Only Supported in SPI0)
0 = 2-Bit Transfer mode Disabled.
1 = 2-Bit Transfer mode Enabled.
Note: When 2-Bit Transfer mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd
serial transmitted bit data is from the second FIFO buffer data.
As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
[17] UNITIEN Unit Transfer Interrupt Enable Bit
0 = SPI unit transfer interrupt Disabled.
1 = SPI unit transfer interrupt Enabled.
[18] SLAVE Slave Mode Control
0 = Master mode.
1 = Slave mode.
[19] REORDER Byte Reorder Function Enable Bit
0 = Byte Reorder function Disabled.
1 = Byte Reorder function Enabled. A byte suspend interval will be inserted among each byte.
The period of the byte suspend interval depends on the setting of SUSPITV.
Note:
1. Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
2. Byte Reorder function is not supported when the Quad or Dual I/O mode is enabled.
[20] QDIODIR Quad Or Dual I/O Mode Direction Control (Only Supported in SPI0)
0 = Quad or Dual Input mode.
1 = Quad or Dual Output mode.
[21] DUALIOEN Dual I/O Mode Enable Bit (Only Supported in SPI0)
0 = Dual I/O mode Disabled.
1 = Dual I/O mode Enabled.
[22] QUADIOEN Quad I/O Mode Enable Bit (Only Supported in SPI0)
0 = Quad I/O mode Disabled.
1 = Quad I/O mode Enabled.

Definition at line 9305 of file M471M_R1_S.h.

◆ CTL [7/9]

TIMER_T::CTL

Offset: 0x00 Timer Control and Status Register

Bits Field Descriptions
[7:0] PSC Prescale Counter
Timer input clock or event source is divided by (PSC+1) before it is fed to the timer up counter.
If this field is 0 (PSC = 0), then there is no scaling.
[17] WKTKEN Wake-Up Touch-Key Scan Enable Bit
If this bit is set to 1, timer time-out interrupt in Power-down mode can be triggered Touch-Key start scan.
0 = Timer time-out interrupt signal trigger Touch-Key start scan Disabled.
1 = Timer time-out interrupt signal trigger Touch-Key start scan Enabled.
Note: This bit is only available in TIMER0_CTL.
[18] TRGSSEL Trigger Source Select Bit
This bit is used to select trigger source is form Timer time-out interrupt signal or capture interrupt signal.
0 = Timer time-out interrupt signal is used to trigger PWM, EADC.
1 = Capture interrupt signal is used to trigger PWM, EADC.
[19] TRGPWM Trigger PWM Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered PWM.
0 = Timer interrupt trigger PWM Disabled.
1 = Timer interrupt trigger PWM Enabled.
Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger PWM.
If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger PWM.
[21] TRGEADC Trigger EADC Enable Bit
If this bit is set to 1, timer time-out interrupt or capture interrupt can be triggered EADC.
0 = Timer interrupt trigger EADC Disabled.
1 = Timer interrupt trigger EADC Enabled.
Note: If TRGSSEL (TIMERx_CTL[18]) = 0, time-out interrupt signal will trigger EADC.
If TRGSSEL (TIMERx_CTL[18]) = 1, capture interrupt signal will trigger EADC.
[22] TGLPINSEL Toggle-Output Pin Select
0 = Toggle mode output to Tx_OUT (Timer Event Counter Pin).
1 = Toggle mode output to Tx_EXT(Timer External Capture Pin).
[23] WKEN Wake-Up Function Enable Bit
If this bit is set to 1, while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
0 = Wake-up function Disabled if timer interrupt signal generated.
1 = Wake-up function Enabled if timer interrupt signal generated.
[24] EXTCNTEN Event Counter Mode Enable Bit
This bit is for external counting pin function enabled.
0 = Event counter mode Disabled.
1 = Event counter mode Enabled.
Note: When timer is used as an event counter, this bit should be set to 1 and select HCLK as timer clock source.
[25] ACTSTS Timer Active Status Bit (Read Only)
This bit indicates the 24-bit up counter status.
0 = 24-bit up counter is not active.
1 = 24-bit up counter is active.
[26] RSTCNT Timer Counter Reset Bit
Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.
0 = No effect.
1 = Reset internal 8-bit prescale counter, 24-bit up counter value and CNTEN bit.
[28:27] OPMODE Timer Counting Mode Select
00 = The Timer controller is operated in One-shot mode.
01 = The Timer controller is operated in Periodic mode.
10 = The Timer controller is operated in Toggle-output mode.
11 = The Timer controller is operated in Continuous Counting mode.
[29] INTEN Timer Interrupt Enable Bit
0 = Timer Interrupt Disabled.
1 = Timer Interrupt Enabled.
Note: If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
[30] CNTEN Timer Counting Enable Bit
0 = Stops/Suspends counting.
1 = Starts counting.
Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value.
Note2: This bit is auto-cleared by hardware in one-shot mode (TIMER_CTL[28:27] = 00) when the timer interrupt flag TIF (TIMERx_INTSTS[0]) is generated.
[31] ICEDEBUG ICE Debug Mode Acknowledge Disable
0 = ICE debug mode acknowledgement effects TIMER counting.
TIMER counter will be held while CPU is held by ICE.
1 = ICE debug mode acknowledgement Disabled.
TIMER counter will keep going no matter CPU is held by ICE or not.

Definition at line 11252 of file M471M_R1_S.h.

◆ CTL [8/9]

WDT_T::CTL

Offset: 0x00 WDT Control Register

Bits Field Descriptions
[0] RSTCNT Reset WDT Up Counter (Write Protect)
0 = No effect.
1 = Reset the internal 18-bit WDT up counter value.
Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note2: This bit will be automatically cleared by hardware.
[1] RSTEN WDT Time-Out Reset Enable Control (Write Protect)
Setting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.
0 = WDT time-out reset function Disabled.
1 = WDT time-out reset function Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[2] RSTF WDT Time-Out Reset Flag
This bit indicates the system has been reset by WDT time-out reset or not.
0 = WDT time-out reset did not occur.
1 = WDT time-out reset occurred.
Note: This bit is cleared by writing 1 to it.
[3] IF WDT Time-Out Interrupt Flag
This bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval
0 = WDT time-out interrupt did not occur.
1 = WDT time-out interrupt occurred.
Note: This bit is cleared by writing 1 to it.
[4] WKEN WDT Time-Out Wake-Up Function Control (Write Protect)
If this bit is set to 1, while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated.
1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated.
Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note2: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator.
[5] WKF WDT Time-Out Wake-Up Flag
This bit indicates the interrupt wake-up flag status of WDT
0 = WDT does not cause chip wake-up.
1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated.
Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note2: This bit is cleared by writing 1 to it.
[6] INTEN WDT Time-Out Interrupt Enable Control (Write Protect)
If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
0 = WDT time-out interrupt Disabled.
1 = WDT time-out interrupt Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[7] WDTEN WDT Enable Control (Write Protect)
0 = WDT Disabled (This action will reset the internal up counter value).
1 = WDT Enabled.
Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
Note2: If CWDTEN[2:0] (combined by Config0[31] and Config0[4:3]) bits is not configure to 111, this bit is forced as 1 and user cannot change this bit to 0.
[10:8] TOUTSEL WDT Time-Out Interval Selection (Write Protect)
These three bits select the time-out interval period for the WDT.
000 = (2^4)*TWDT.
001 = (2^6)*TWDT.
010 = (2^8)*TWDT.
011 = (2^10)*TWDT.
100 = (2^12)*TWDT.
101 = (2^14)*TWDT.
110 = (2^16)*TWDT.
111 = (2^18)*TWDT.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[31] ICEDEBUG ICE Debug Mode Acknowledge Disable Control (Write Protect)
0 = ICE debug mode acknowledgement affects WDT counting.
WDT up counter will be held while CPU is held by ICE.
1 = ICE debug mode acknowledgement Disabled.
WDT up counter will keep going no matter CPU is held by ICE or not.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 13566 of file M471M_R1_S.h.

◆ CTL [9/9]

WWDT_T::CTL

Offset: 0x04 WWDT Control Register

Bits Field Descriptions
[0] WWDTEN WWDT Enable Control Bit
Set this bit to enable WWDT counter counting.
0 = WWDT counter is stopped.
1 = WWDT counter is starting counting.
[1] INTEN WWDT Interrupt Enable Control Bit
If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
0 = WWDT counter compare match interrupt Disabled.
1 = WWDT counter compare match interrupt Enabled.
[11:8] PSCSEL WWDT Counter Prescale Period Selection
0000 = Pre-scale is 1; Max time-out period is 1 * 64 * TWWDT.
0001 = Pre-scale is 2; Max time-out period is 2 * 64 * TWWDT.
0010 = Pre-scale is 4; Max time-out period is 4 * 64 * TWWDT.
0011 = Pre-scale is 8; Max time-out period is 8 * 64 * TWWDT.
0100 = Pre-scale is 16; Max time-out period is 16 * 64 * TWWDT.
0101 = Pre-scale is 32; Max time-out period is 32 * 64 * TWWDT.
0110 = Pre-scale is 64; Max time-out period is 64 * 64 * TWWDT.
0111 = Pre-scale is 128; Max time-out period is 128 * 64 * TWWDT.
1000 = Pre-scale is 192; Max time-out period is 192 * 64 * TWWDT.
1001 = Pre-scale is 256; Max time-out period is 256 * 64 * TWWDT.
1010 = Pre-scale is 384; Max time-out period is 384 * 64 * TWWDT.
1011 = Pre-scale is 512; Max time-out period is 512 * 64 * TWWDT.
1100 = Pre-scale is 768; Max time-out period is 768 * 64 * TWWDT.
1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * TWWDT.
1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * TWWDT.
1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * TWWDT.
[21:16] CMPDAT WWDT Window Compare Register
Set this register to adjust the valid reload window.
Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.
If user writes WWDT_RLDCNT register when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
[31] ICEDEBUG ICE Debug Mode Acknowledge Disable Control
0 = ICE debug mode acknowledgement effects WWDT counting.
WWDT down counter will be held while CPU is held by ICE.
1 = ICE debug mode acknowledgement Disabled.
WWDT down counter will keep going no matter CPU is held by ICE or not.

Definition at line 13702 of file M471M_R1_S.h.

◆ CTL0 [1/2]

EBI_T::CTL0

Offset: 0x00 External Bus Interface Bank0 Control Register

Bits Field Descriptions
[0] EN EBI Enable Bit
This bit is the functional enable bit for EBI.
0 = EBI function Disabled.
1 = EBI function Enabled.
[1] DW16 EBI Data Width 16-Bit Select
This bit defines if the EBI data width is 8-bit or 16-bit.
0 = EBI data width is 8-bit.
1 = EBI data width is 16-bit.
[2] CSPOLINV Chip Select Pin Polar Inverse
This bit defines the active level of EBI chip select pin (EBI_nCS).
0 = Chip select pin (EBI_nCS) is active low.
1 = Chip select pin (EBI_nCS) is active high.
[10:8] MCLKDIV External Output Clock Divider
The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
000 = HCLK/1.
001 = HCLK/2.
010 = HCLK/4.
011 = HCLK/8.
100 = HCLK/16.
101 = HCLK/32.
110 = Reserved.
111 = Reserved.
[18:16] TALE Extend Time Of ALE
The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
tALE = (TALE+1)*EBI_MCLK.
Note: This field only available in EBI_CTL0 register
[24] WBUFEN EBI Write Buffer Enable Bit
0 = EBI write buffer Disabled.
1 = EBI write buffer Enabled.
Note: This bit only available in EBI_CTL0 register

Definition at line 1996 of file M471M_R1_S.h.

◆ CTL0 [2/2]

PWM_T::CTL0

Offset: 0x00 PWM Control Register 0

Bits Field Descriptions
[5:0] CTRLDn Center Re-Load
Each bit n controls the corresponding PWM channel n.
In up-down counter type, PERIOD will load to PBUF at the end point of each period.
CMPDAT will load to CMPBUF at the center point of a period.
[13:8] WINLDENn Window Load Enable
Each bit n controls the corresponding PWM channel n.
0 = PERIOD will load to PBUF at the end point of each period.
CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
1 = PERIOD will load to PBUF at the end point of each period.
CMPDAT will load to CMPBUF at the end point of each period when valid reload window is set.
The valid reload window is set by software write 1 to PWM_LOAD register and cleared by hardware after load success.
[21:16] IMMLDENn Immediately Load Enable
Each bit n controls the corresponding PWM channel n.
0 = PERIOD will load to PBUF at the end point of each period.
CMPDAT will load to CMPBUF at the end point or center point of each period by setting CTRLD bit.
1 = PERIOD/CMPDAT will load to PBUF and CMPBUF immediately when software update PERIOD/CMPDAT.
Note: If IMMLDENn is enabled, WINLDENn and CTRLDn will be invalid.
[24] GROUPEN Group Function Enable
0 = The output waveform of each PWM channel are independent.
1 = Unify the PWM_CH2 and PWM_CH4 to output the same waveform as PWM_CH0 and unify the PWM_CH3 and PWM_CH5 to output the same waveform as PWM_CH1.
[30] DBGHALT ICE Debug Mode Counter Halt (Write Protect)
If counter halt is enabled, PWM all counters will keep current value until exit ICE debug mode.
0 = ICE debug mode counter halt disable.
1 = ICE debug mode counter halt enable.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[31] DBGTRIOFF ICE Debug Mode Acknowledge Disable (Write Protect)
0 = ICE debug mode acknowledgement effects PWM output.
PWM pin will be forced as tri-state while ICE debug mode acknowledged.
1 = ICE debug mode acknowledgement disabled.
PWM pin will keep output no matter ICE debug mode acknowledged or not.
Note: This register is write protected. Refer to SYS_REGLCTL register.

Definition at line 5815 of file M471M_R1_S.h.

◆ CTL1 [1/2]

EBI_T::CTL1

Offset: 0x10 External Bus Interface Bank1 Control Register

Bits Field Descriptions
[0] EN EBI Enable Bit
This bit is the functional enable bit for EBI.
0 = EBI function Disabled.
1 = EBI function Enabled.
[1] DW16 EBI Data Width 16-Bit Select
This bit defines if the EBI data width is 8-bit or 16-bit.
0 = EBI data width is 8-bit.
1 = EBI data width is 16-bit.
[2] CSPOLINV Chip Select Pin Polar Inverse
This bit defines the active level of EBI chip select pin (EBI_nCS).
0 = Chip select pin (EBI_nCS) is active low.
1 = Chip select pin (EBI_nCS) is active high.
[10:8] MCLKDIV External Output Clock Divider
The frequency of EBI output clock (MCLK) is controlled by MCLKDIV as follow:
000 = HCLK/1.
001 = HCLK/2.
010 = HCLK/4.
011 = HCLK/8.
100 = HCLK/16.
101 = HCLK/32.
110 = Reserved.
111 = Reserved.
[18:16] TALE Extend Time Of ALE
The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
tALE = (TALE+1)*EBI_MCLK.
Note: This field only available in EBI_CTL0 register
[24] WBUFEN EBI Write Buffer Enable Bit
0 = EBI write buffer Disabled.
1 = EBI write buffer Enabled.
Note: This bit only available in EBI_CTL0 register

Definition at line 1999 of file M471M_R1_S.h.

◆ CTL1 [2/2]

PWM_T::CTL1

Offset: 0x04 PWM Control Register 1

Bits Field Descriptions
[11:0] CNTTYPEn PWM Counter Behavior Type
Each bit n controls corresponding PWM channel n.
00 = Up counter type (supports in capture mode).
01 = Down count type (supports in capture mode).
10 = Up-down counter type.
11 = Reserved.
[21:16] CNTMODEn PWM Counter Mode
Each bit n controls the corresponding PWM channel n.
0 = Auto-reload mode.
1 = One-shot mode.
[26:24] OUTMODEn PWM Output Mode
Each bit n controls the
output mode of
corresponding PWM channel n.
0 = PWM independent mode.
1 = PWM complementary mode.
Note: When operating in group function, these bits must all set to the same mode.

Definition at line 5816 of file M471M_R1_S.h.

◆ CURDAT

EADC_T::CURDAT

Offset: 0x4C EADC PDMA Current Transfer Data Register

Bits Field Descriptions
[17:0] CURDAT ADC PDMA Current Transfer Data Register
This register is a shadow register of EADC_DATn (n=0~18) for PDMA support.
This is a read only register.

Definition at line 722 of file M471M_R1_S.h.

◆ CURSCAT

PDMA_T::CURSCAT

Offset: 0xC0 ~ 0xEC Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~11

Bits Field Descriptions
[31:0] CURADDR PDMA Current Description Address Register (Read Only)
This field indicates a 32-bit current external description address of PDMA controller.
Note: This field is read only and only used for Scatter-Gather mode to indicate the current external description address.

Definition at line 4323 of file M471M_R1_S.h.

◆ DA

DSCT_T::DA

Offset: 0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78/0x88/0x98/0xA8/0xB8 Destination Address Register of PDMA Channel 0~11

Bits Field Descriptions
[31:0] DA PDMA Transfer Destination Address Register
This field indicates a 32-bit destination address of PDMA controller.

Definition at line 3994 of file M471M_R1_S.h.

◆ DAT [1/5]

EADC_T::DAT

Offset: 0x00-0x48 A/D Data Register n for Sample Module n, n=0~18

Bits Field Descriptions
[15:0] RESULT A/D Conversion Result
This field contains 12 bits conversion result.
When DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].
When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12].
[16] OV Overrun Flag
If converted data in RESULT[11:0] has not been read before new conversion result is loaded to this register, OV is set to 1.
0 = Data in RESULT[11:0] is recent conversion result.
1 = Data in RESULT[11:0] is overwrite.
Note: It is cleared by hardware after EADC_DAT register is read.
[17] VALID Valid Flag
This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DAT register is read.
0 = Data in RESULT[11:0] bits is not valid.
1 = Data in RESULT[11:0] bits is valid.

Definition at line 721 of file M471M_R1_S.h.

◆ DAT [2/5]

CRC_T::DAT

Offset: 0x04 CRC Write Data Register

Bits Field Descriptions
[31:0] DATA CRC Write Data Bits
User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.
Note: When the write data length is 8-bit mode, the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_DAT register is only DATA[15:0].

Definition at line 1809 of file M471M_R1_S.h.

◆ DAT [3/5]

I2C_T::DAT

Offset: 0x08 I2C Data Register

Bits Field Descriptions
[7:0] DAT I2C Data
Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port.

Definition at line 3703 of file M471M_R1_S.h.

◆ DAT [4/5]

SC_T::DAT

Offset: 0x00 SC Receiving/Transmit Holding Buffer Register.

Bits Field Descriptions
[7:0] DAT Receiving/ Transmit Holding Buffer
Write Operation:
By writing data to DAT, the SC will send out an 8-bit data.
Note: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed.
Read Operation:
By reading DAT, the SC will return an 8-bit received data.

Definition at line 8492 of file M471M_R1_S.h.

◆ DAT [5/5]

UART_T::DAT

Offset: 0x00 UART Receive/Transmit Buffer Register

Bits Field Descriptions
[7:0] DAT Receiving/Transmit Buffer
Write Operation:
By writing one byte to this register, the data byte will be stored in transmitter FIFO.
The UART Controller will send out the data stored in transmitter FIFO top location through the UART_TXD.
Read Operation:
By reading this register, the UART will return an 8-bit data received from receiving FIFO.

Definition at line 11883 of file M471M_R1_S.h.

◆ DATMSK

GPIO_T::DATMSK

Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C Port A-F Data Output Write Mask

Bits Field Descriptions
[n] DMASKn Port A-F Pin[n] Data Output Write Mask
These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit.
When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected.
If the write signal is masked, writing data to the protect bit is ignored.
0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
Note1: This function only protects the corresponding DOUT (Px_DOUT[n]) bit, and will not protect the corresponding PDIO (Pxn_PDIO[0]) bit.
Note2:
n=0~15 for port A/B/C/D.
n=0~14 for port E.
n=0~7 for port F.

Definition at line 2655 of file M471M_R1_S.h.

◆ DBCTL

GPIO_DBCTL_T::DBCTL

Offset: 0x440 Interrupt De-bounce Control Register

Bits Field Descriptions
[3:0] DBCLKSEL De-Bounce Sampling Cycle Selection
0000 = Sample interrupt input once per 1 clocks.
0001 = Sample interrupt input once per 2 clocks.
0010 = Sample interrupt input once per 4 clocks.
0011 = Sample interrupt input once per 8 clocks.
0100 = Sample interrupt input once per 16 clocks.
0101 = Sample interrupt input once per 32 clocks.
0110 = Sample interrupt input once per 64 clocks.
0111 = Sample interrupt input once per 128 clocks.
1000 = Sample interrupt input once per 256 clocks.
1001 = Sample interrupt input once per 2*256 clocks.
1010 = Sample interrupt input once per 4*256 clocks.
1011 = Sample interrupt input once per 8*256 clocks.
1100 = Sample interrupt input once per 16*256 clocks.
1101 = Sample interrupt input once per 32*256 clocks.
1110 = Sample interrupt input once per 64*256 clocks.
1111 = Sample interrupt input once per 128*256 clocks.
[4] DBCLKSRC De-Bounce Counter Clock Source Selection
0 = De-bounce counter clock source is the HCLK.
1 = De-bounce counter clock source is the internal 10 kHz internal low speed oscillator.
[5] ICLKON Interrupt Clock On Mode
0 = Edge detection circuit is active only if I/O pin corresponding RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) bit is set to 1.
1 = All I/O pins edge detection circuit is always active after reset.
Note: It is recommended to disable this bit to save system power if no special application concern.

Definition at line 2707 of file M471M_R1_S.h.

◆ DBEN

GPIO_T::DBEN

Offset: 0x14/0x54/0x94/0xD4/0x114/0x154 Port A-F De-Bounce Enable Control Register

Bits Field Descriptions
[n] DBENn Port A-F Pin[n] Input Signal De-Bounce Enable Bit
The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit.
If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt.
The de-bounce clock source is controlled by DBCLKSRC (GPIO_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (GPIO_DBCTL [3:0]).
0 = Px.n de-bounce function Disabled.
1 = Px.n de-bounce function Enabled.
The de-bounce function is valid only for edge triggered interrupt.
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note:
n=0~15 for port A/B/C/D.
n=0~14 for port E.
n=0~7 for port F.

Definition at line 2657 of file M471M_R1_S.h.

◆ DDAT

EADC_T::DDAT

Offset: 0x100-0x10C A/D Double Data Register n for Sample Module n, n=0~3

Bits Field Descriptions
[15:0] RESULT A/D Conversion Results
This field contains 12 bits conversion results.
When the DMOF (EADC_CTL[9]) is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT [11:0] and zero will be filled in RESULT [15:12].
When DMOF (EADC_CTL[9]) set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT [11:0] and signed bits to will be filled in RESULT [15:12].
[16] OV Overrun Flag
0 = Data in RESULT (EADC_DATn[15:0], n=0~3) is recent conversion result.
1 = Data in RESULT (EADC_DATn[15:0], n=0~3) is overwrite.
If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1.
It is cleared by hardware after EADC_DDAT register is read.
[17] VALID Valid Flag
0 = Double data in RESULT (EADC_DDATn[15:0]) is not valid.
1 = Double data in RESULT (EADC_DDATn[15:0]) is valid.
This bit is set to 1 when corresponding sample module channel analog input conversion is completed and cleared by hardware after EADC_DDATn register is read.
(n=0~3).

Definition at line 736 of file M471M_R1_S.h.

◆ DFBA

FMC_T::DFBA

Offset: 0x14 Data Flash Base Address

Bits Field Descriptions
[31:0] DFBA Data Flash Base Address
This register indicates Data Flash start address. It is a read only register.
The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1
This register is valid when DFEN (CONFIG0[0]) =0 .

Definition at line 2340 of file M471M_R1_S.h.

◆ DINOFF

GPIO_T::DINOFF

Offset: 0x04/0x44/0x84/0xC4/0x104/0x144 Port A-F Digital Input Path Disable Control

Bits Field Descriptions
[n+16] DINOFFn Port A-F Pin[n] Digital Input Path Disable Control
Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled.
If input is analog signal, users can disable Px.n digital input path to avoid input current leakage.
0 = Px.n digital input path Enabled.
1 = Px.n digital input path Disabled (digital input tied to low).
Note:
n=0~15 for port A/B/C/D.
n=0~14 for port E.
n=0~7 for port F.

Definition at line 2653 of file M471M_R1_S.h.

◆ DOUT

GPIO_T::DOUT

Offset: 0x08/0x48/0x88/0xC8/0x108/0x148 Port A-F Data Output Value

Bits Field Descriptions
[n] DOUTn Port A-F Pin[n] Output Value
Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.
Note:
n=0~15 for port A/B/C/D.
n=0~14 for port E.
n=0~7 for port F.

Definition at line 2654 of file M471M_R1_S.h.

◆ DRVCTL

GPIO_T::DRVCTL

Offset: 0x2C Port E High Drive Strength Control Register

Bits Field Descriptions
[n] HDRVENn Port E Pin[n] Driving Strength Control
0 = Px.n output with basic driving strength.
1 = Px.n output with high driving strength.
Note:
n=8,9..13 for port E.

Definition at line 2663 of file M471M_R1_S.h.

◆ DSCT

PDMA_T::DSCT

Offset: 0x0000 ~ 0x00BC DMA Embedded Description Table 0~11

Definition at line 4322 of file M471M_R1_S.h.

◆ DTCTL0_1

PWM_T::DTCTL0_1

Offset: 0x70 PWM Dead-Time Control Register 0

Bits Field Descriptions
[11:0] DTCNT Dead-Time Counter (Write Protect)
The dead-time can be calculated from the following formula:
Dead-time = (DTCNT[11:0]+1) * PWM_CLK period.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[16] DTEN Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
Dead-time insertion is only active when this pair of complementary PWM is enabled.
If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
0 = Dead-time insertion Disabled on the pin pair.
1 = Dead-time insertion Enabled on the pin pair.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[24] DTCKSEL Dead-Time Clock Select (Write Protect)
0 = Dead-time clock source from PWM_CLK.
1 = Dead-time clock source from prescaler output.
Note: This register is write protected. Refer to SYS_REGLCTL register.

Definition at line 5831 of file M471M_R1_S.h.

◆ DTCTL2_3

PWM_T::DTCTL2_3

Offset: 0x74 PWM Dead-Time Control Register 2

Bits Field Descriptions
[11:0] DTCNT Dead-Time Counter (Write Protect)
The dead-time can be calculated from the following formula:
Dead-time = (DTCNT[11:0]+1) * PWM_CLK period.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[16] DTEN Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
Dead-time insertion is only active when this pair of complementary PWM is enabled.
If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
0 = Dead-time insertion Disabled on the pin pair.
1 = Dead-time insertion Enabled on the pin pair.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[24] DTCKSEL Dead-Time Clock Select (Write Protect)
0 = Dead-time clock source from PWM_CLK.
1 = Dead-time clock source from prescaler output.
Note: This register is write protected. Refer to SYS_REGLCTL register.

Definition at line 5832 of file M471M_R1_S.h.

◆ DTCTL4_5

PWM_T::DTCTL4_5

Offset: 0x78 PWM Dead-Time Control Register 4

Bits Field Descriptions
[11:0] DTCNT Dead-Time Counter (Write Protect)
The dead-time can be calculated from the following formula:
Dead-time = (DTCNT[11:0]+1) * PWM_CLK period.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[16] DTEN Enable Dead-Time Insertion For PWM Pair (PWM_CH0, PWM_CH1) (PWM_CH2, PWM_CH3) (PWM_CH4, PWM_CH5) (Write Protect)
Dead-time insertion is only active when this pair of complementary PWM is enabled.
If dead- time insertion is inactive, the outputs of pin pair are complementary without any delay.
0 = Dead-time insertion Disabled on the pin pair.
1 = Dead-time insertion Enabled on the pin pair.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[24] DTCKSEL Dead-Time Clock Select (Write Protect)
0 = Dead-time clock source from PWM_CLK.
1 = Dead-time clock source from prescaler output.
Note: This register is write protected. Refer to SYS_REGLCTL register.

Definition at line 5833 of file M471M_R1_S.h.

◆ EADCTS0

PWM_T::EADCTS0

Offset: 0xF8 PWM Trigger EADC Source Select Register 0

Bits Field Descriptions
[3:0] TRGSEL0 PWM_CH0 Trigger EADC Source Select
0000 = PWM_CH0 zero point.
0001 = PWM_CH0 period point.
0010 = PWM_CH0 zero or period point.
0011 = PWM_CH0 up-count CMPDAT point.
0100 = PWM_CH0 down-count CMPDAT point.
0101 = PWM_CH1 zero point.
0110 = PWM_CH1 period point.
0111 = PWM_CH1 zero or period point.
1000 = PWM_CH1 up-count CMPDAT point.
1001 = PWM_CH1 down-count CMPDAT point.
1010 = PWM_CH0 up-count free CMPDAT point.
1011 = PWM_CH0 down-count free CMPDAT point.
1100 = PWM_CH2 up-count free CMPDAT point.
1101 = PWM_CH2 down-count free CMPDAT point.
1110 = PWM_CH4 up-count free CMPDAT point.
1111 = PWM_CH4 down-count free CMPDAT point.
[7] TRGEN0 PWM_CH0 Trigger EADC enable bit
[11:8] TRGSEL1 PWM_CH1 Trigger EADC Source Select
0000 = PWM_CH0 zero point.
0001 = PWM_CH0 period point.
0010 = PWM_CH0 zero or period point.
0011 = PWM_CH0 up-count CMPDAT point.
0100 = PWM_CH0 down-count CMPDAT point.
0101 = PWM_CH1 zero point.
0110 = PWM_CH1 period point.
0111 = PWM_CH1 zero or period point.
1000 = PWM_CH1 up-count CMPDAT point.
1001 = PWM_CH1 down-count CMPDAT point.
1010 = PWM_CH0 up-count free CMPDAT point.
1011 = PWM_CH0 down-count free CMPDAT point.
1100 = PWM_CH2 up-count free CMPDAT point.
1101 = PWM_CH2 down-count free CMPDAT point.
1110 = PWM_CH4 up-count free CMPDAT point.
1111 = PWM_CH4 down-count free CMPDAT point.
[15] TRGEN1 PWM_CH1 Trigger EADC enable bit
[19:16] TRGSEL2 PWM_CH2 Trigger EADC Source Select
0000 = PWM_CH2 zero point.
0001 = PWM_CH2 period point.
0010 = PWM_CH2 zero or period point.
0011 = PWM_CH2 up-count CMPDAT point.
0100 = PWM_CH2 down-count CMPDAT point.
0101 = PWM_CH3 zero point.
0110 = PWM_CH3 period point.
0111 = PWM_CH3 zero or period point.
1000 = PWM_CH3 up-count CMPDAT point.
1001 = PWM_CH3 down-count CMPDAT point.
1010 = PWM_CH0 up-count free CMPDAT point.
1011 = PWM_CH0 down-count free CMPDAT point.
1100 = PWM_CH2 up-count free CMPDAT point.
1101 = PWM_CH2 down-count free CMPDAT point.
1110 = PWM_CH4 up-count free CMPDAT point.
1111 = PWM_CH4 down-count free CMPDAT point.
[23] TRGEN2 PWM_CH2 Trigger EADC enable bit
[27:24] TRGSEL3 PWM_CH3 Trigger EADC Source Select
0000 = PWM_CH2 zero point.
0001 = PWM_CH2 period point.
0010 = PWM_CH2 zero or period point.
0011 = PWM_CH2 up-count CMPDAT point.
0100 = PWM_CH2 down-count CMPDAT point.
0101 = PWM_CH3 zero point.
0110 = PWM_CH3 period point.
0111 = PWM_CH3 zero or period point.
1000 = PWM_CH3 up-count CMPDAT point.
1001 = PWM_CH3 down-count CMPDAT point.
1010 = PWM_CH0 up-count free CMPDAT point.
1011 = PWM_CH0 down-count free CMPDAT point.
1100 = PWM_CH2 up-count free CMPDAT point.
1101 = PWM_CH2 down-count free CMPDAT point.
1110 = PWM_CH4 up-count free CMPDAT point.
1111 = PWM_CH4 down-count free CMPDAT point.
[31] TRGEN3 PWM_CH3 Trigger EADC enable bit

Definition at line 5859 of file M471M_R1_S.h.

◆ EADCTS1

PWM_T::EADCTS1

Offset: 0xFC PWM Trigger EADC Source Select Register 1

Bits Field Descriptions
[3:0] TRGSEL4 PWM_CH4 Trigger EADC Source Select
0000 = PWM_CH4 zero point.
0001 = PWM_CH4 period point.
0010 = PWM_CH4 zero or period point.
0011 = PWM_CH4 up-count CMPDAT point.
0100 = PWM_CH4 down-count CMPDAT point.
0101 = PWM_CH5 zero point.
0110 = PWM_CH5 period point.
0111 = PWM_CH5 zero or period point.
1000 = PWM_CH5 up-count CMPDAT point.
1001 = PWM_CH5 down-count CMPDAT point.
1010 = PWM_CH0 up-count free CMPDAT point.
1011 = PWM_CH0 down-count free CMPDAT point.
1100 = PWM_CH2 up-count free CMPDAT point.
1101 = PWM_CH2 down-count free CMPDAT point.
1110 = PWM_CH4 up-count free CMPDAT point.
1111 = PWM_CH4 down-count free CMPDAT point.
[7] TRGEN4 PWM_CH4 Trigger EADC enable bit
[11:8] TRGSEL5 PWM_CH5 Trigger EADC Source Select
0000 = PWM_CH4 zero point.
0001 = PWM_CH4 period point.
0010 = PWM_CH4 zero or period point.
0011 = PWM_CH4 up-count CMPDAT point.
0100 = PWM_CH4 down-count CMPDAT point.
0101 = PWM_CH5 zero point.
0110 = PWM_CH5 period point.
0111 = PWM_CH5 zero or period point.
1000 = PWM_CH5 up-count CMPDAT point.
1001 = PWM_CH5 down-count CMPDAT point.
1010 = PWM_CH0 up-count free CMPDAT point.
1011 = PWM_CH0 down-count free CMPDAT point.
1100 = PWM_CH2 up-count free CMPDAT point.
1101 = PWM_CH2 down-count free CMPDAT point.
1110 = PWM_CH4 up-count free CMPDAT point.
1111 = PWM_CH4 down-count free CMPDAT point.
[15] TRGEN5 PWM_CH5 Trigger EADC enable bit

Definition at line 5860 of file M471M_R1_S.h.

◆ EGT

SC_T::EGT

Offset: 0x0C SC Extend Guard Time Register.

Bits Field Descriptions
[7:0] EGT Extended Guard Time
This field indicates the extended guard timer value.
Note:
The counter is ETU base and the real extended guard time is EGT.

Definition at line 8495 of file M471M_R1_S.h.

◆ EINTSTS

TIMER_T::EINTSTS

Offset: 0x18 Timer External Interrupt Status Register

Bits Field Descriptions
[0] CAPIF Timer External Capture Interrupt Flag
This bit indicates the timer external capture interrupt flag status.
0 = Tx_EXT (x= 0~3) pin interrupt did not occur.
1 = Tx_EXT (x= 0~3) pin interrupt occurred.
Note1: This bit is cleared by writing 1 to it.
Note2: When CAPEN (TIMERx_EXTCTL[3]) bit is set, CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0, and a transition on Tx_EXT (x= 0~3) pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting, this bit will set to 1 by hardware.
Note3: There is a new incoming capture event detected before CPU clearing the CAPIF status.
If the above condition occurred, the Timer will keep register TIMERx_CAP unchanged and drop the new capture value.

Definition at line 11258 of file M471M_R1_S.h.

◆ EP

USBD_EP_T USBD_T::EP[8]

Definition at line 12519 of file M471M_R1_S.h.

◆ EPSTS

USBD_T::EPSTS

Offset: 0x0C USB Endpoint Status Register

Bits Field Descriptions
[7] OV Overrun
It indicates that the received data is over the maximum payload number or not.
0 = No overrun.
1 = Out Data is more than the Max Payload in MXPLD register or the Setup Data is more than 8 Bytes.
[10:8] EPSTS0 Endpoint 0 Bus Status
These bits are used to indicate the current status of this endpoint
000 = In ACK.
001 = In NAK.
010 = Out Packet Data0 ACK.
110 = Out Packet Data1 ACK.
011 = Setup ACK.
111 = Isochronous transfer end.
[13:11] EPSTS1 Endpoint 1 Bus Status
These bits are used to indicate the current status of this endpoint
000 = In ACK.
001 = In NAK.
010 = Out Packet Data0 ACK.
110 = Out Packet Data1 ACK.
011 = Setup ACK.
111 = Isochronous transfer end.
[16:14] EPSTS2 Endpoint 2 Bus Status
These bits are used to indicate the current status of this endpoint
000 = In ACK.
001 = In NAK.
010 = Out Packet Data0 ACK.
110 = Out Packet Data1 ACK.
011 = Setup ACK.
111 = Isochronous transfer end.
[19:17] EPSTS3 Endpoint 3 Bus Status
These bits are used to indicate the current status of this endpoint
000 = In ACK.
001 = In NAK.
010 = Out Packet Data0 ACK.
110 = Out Packet Data1 ACK.
011 = Setup ACK.
111 = Isochronous transfer end.
[22:20] EPSTS4 Endpoint 4 Bus Status
These bits are used to indicate the current status of this endpoint
000 = In ACK.
001 = In NAK.
010 = Out Packet Data0 ACK.
110 = Out Packet Data1 ACK.
011 = Setup ACK.
111 = Isochronous transfer end.
[25:23] EPSTS5 Endpoint 5 Bus Status
These bits are used to indicate the current status of this endpoint
000 = In ACK.
001 = In NAK.
010 = Out Packet Data0 ACK.
110 = Out Packet Data1 ACK.
011 = Setup ACK.
111 = Isochronous transfer end.
[28:26] EPSTS6 Endpoint 6 Bus Status
These bits are used to indicate the current status of this endpoint
000 = In ACK.
001 = In NAK.
010 = Out Packet Data0 ACK.
110 = Out Packet Data1 ACK.
011 = Setup ACK.
111 = Isochronous transfer end.
[31:29] EPSTS7 Endpoint 7 Bus Status
These bits are used to indicate the current status of this endpoint
000 = In ACK.
001 = In NAK.
010 = Out Packet Data0 ACK.
110 = Out Packet Data1 ACK.
011 = Setup ACK.
111 = Isochronous transfer end.

Definition at line 12512 of file M471M_R1_S.h.

◆ ETUCTL

SC_T::ETUCTL

Offset: 0x14 SC ETU Control Register.

Bits Field Descriptions
[11:0] ETURDIV ETU Rate Divider
The field indicates the clock rate divider.
The real ETU is ETURDIV + 1.
Note:
Software can configure this field, but this field must be greater than 0x004.
[15] CMPEN Compensation Mode Enable Bit
This bit enables clock compensation function.
When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written into the ETURDIV .
0 = Compensation function Disabled.
1 = Compensation function Enabled.

Definition at line 8497 of file M471M_R1_S.h.

◆ EXTCTL

TIMER_T::EXTCTL

Offset: 0x14 Timer External Control Register

Bits Field Descriptions
[0] CNTPHASE Timer External Count Phase
This bit indicates the detection phase of external counting pin Tx_CNT (x= 0~3).
0 = A Falling edge of external counting pin will be counted.
1 = A Rising edge of external counting pin will be counted.
[2:1] CAPEDGE Timer External Capture Pin Edge Detect
00 = A Falling edge on Tx_EXT (x= 0~3) pin will be detected.
01 = A Rising edge on Tx_EXT (x= 0~3) pin will be detected.
10 = Either Rising or Falling edge on Tx_EXT (x= 0~3) pin will be detected.
11 = Reserved.
[3] CAPEN Timer External Capture Pin Enable
This bit enables the Tx_EXT pin.
0 =Tx_EXT (x= 0~3) pin Disabled.
1 =Tx_EXT (x= 0~3) pin Enabled.
[4] CAPFUNCS Capture Function Selection
0 = External Capture Mode Enabled.
1 = External Reset Mode Enabled.
Note1: When CAPFUNCS is 0, transition on Tx_EXT (x= 0~3) pin is using to save the 24-bit timer counter value.
Note2: When CAPFUNCS is 1, transition on Tx_EXT (x= 0~3) pin is using to reset the 24-bit timer counter value.
[5] CAPIEN Timer External Capture Interrupt Enable
0 = Tx_EXT (x= 0~3) pin detection Interrupt Disabled.
1 = Tx_EXT (x= 0~3) pin detection Interrupt Enabled.
Note: CAPIEN is used to enable timer external interrupt.
If CAPIEN enabled, timer will rise an interrupt when CAPIF (TIMERx_EINTSTS[0]) is 1.
For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the Tx_EXT pin will cause the CAPIF to be set then the interrupt signal is generated and sent to NVIC to inform CPU.
[6] CAPDBEN Timer External Capture Pin De-Bounce Enable
0 = Tx_EXT (x= 0~3) pin de-bounce Disabled.
1 = Tx_EXT (x= 0~3) pin de-bounce Enabled.
Note: If this bit is enabled, the edge detection of Tx_EXT pin is detected with de-bounce circuit.
[7] CNTDBEN Timer Counter Pin De-Bounce Enable
0 = Tx_CNT (x= 0~3) pin de-bounce Disabled.
1 = Tx_CNT (x= 0~3) pin de-bounce Enabled.
Note: If this bit is enabled, the edge detection of Tx_CNT pin is detected with de-bounce circuit.

Definition at line 11257 of file M471M_R1_S.h.

◆ FADDR

USBD_T::FADDR

Offset: 0x08 USB Device Function Address Register

Bits Field Descriptions
[6:0] FADDR USB Device Function Address

Definition at line 12511 of file M471M_R1_S.h.

◆ FAILBRK

PWM_T::FAILBRK

Offset: 0xC4 PWM System Fail Brake Control Register

Bits Field Descriptions
[0] CSSBRKEN Clock Security System Detection Trigger PWM Brake Function 0 Enable
0 = Brake Function triggered by CSS detection Disabled.
1 = Brake Function triggered by CSS detection Enabled.
[1] BODBRKEN Brown-Out Detection Trigger PWM Brake Function 0 Enable
0 = Brake Function triggered by BOD Disabled.
1 = Brake Function triggered by BOD Enabled.
[3] CORBRKEN Core Lockup Detection Trigger PWM Brake Function 0 Enable
0 = Brake Function triggered by Core lockup detection Disabled.
1 = Brake Function triggered by Core lockup detection Enabled.

Definition at line 5846 of file M471M_R1_S.h.

◆ FCAPDAT0

PWM_T::FCAPDAT0

Offset: 0x210 PWM Falling Capture Data Register 0

Bits Field Descriptions
[15:0] FCAPDAT PWM Falling Capture Data Register (Read Only)
When falling capture condition happened, the PWM counter value will be saved in this register.

Definition at line 5874 of file M471M_R1_S.h.

◆ FCAPDAT1

PWM_T::FCAPDAT1

Offset: 0x218 PWM Falling Capture Data Register 1

Bits Field Descriptions
[15:0] FCAPDAT PWM Falling Capture Data Register (Read Only)
When falling capture condition happened, the PWM counter value will be saved in this register.

Definition at line 5876 of file M471M_R1_S.h.

◆ FCAPDAT2

PWM_T::FCAPDAT2

Offset: 0x220 PWM Falling Capture Data Register 2

Bits Field Descriptions
[15:0] FCAPDAT PWM Falling Capture Data Register (Read Only)
When falling capture condition happened, the PWM counter value will be saved in this register.

Definition at line 5878 of file M471M_R1_S.h.

◆ FCAPDAT3

PWM_T::FCAPDAT3

Offset: 0x228 PWM Falling Capture Data Register 3

Bits Field Descriptions
[15:0] FCAPDAT PWM Falling Capture Data Register (Read Only)
When falling capture condition happened, the PWM counter value will be saved in this register.

Definition at line 5880 of file M471M_R1_S.h.

◆ FCAPDAT4

PWM_T::FCAPDAT4

Offset: 0x230 PWM Falling Capture Data Register 4

Bits Field Descriptions
[15:0] FCAPDAT PWM Falling Capture Data Register (Read Only)
When falling capture condition happened, the PWM counter value will be saved in this register.

Definition at line 5882 of file M471M_R1_S.h.

◆ FCAPDAT5

PWM_T::FCAPDAT5

Offset: 0x238 PWM Falling Capture Data Register 5

Bits Field Descriptions
[15:0] FCAPDAT PWM Falling Capture Data Register (Read Only)
When falling capture condition happened, the PWM counter value will be saved in this register.

Definition at line 5884 of file M471M_R1_S.h.

◆ FIFO

UART_T::FIFO

Offset: 0x08 UART FIFO Control Register

Bits Field Descriptions
[1] RXRST RX Field Software Reset
When RXRST (UART_FIFO[1]) is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
0 = No effect.
1 = Reset the RX internal state machine and pointers.
Note: This bit will automatically clear at least 3 UART peripheral clock cycles.
[2] TXRST TX Field Software Reset
When TXRST (UART_FIFO[2]) is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
0 = No effect.
1 = Reset the TX internal state machine and pointers.
Note: This bit will automatically clear at least 3 UART peripheral clock cycles.
[7:4] RFITL RX FIFO Interrupt Trigger Level
When the number of bytes in the receive FIFO equals the RFITL, the RDAIF will be set (if RDAIEN (UART_INTEN [0]) enabled, and an interrupt will be generated).
0000 = RX FIFO Interrupt Trigger Level is 1 byte.
0001 = RX FIFO Interrupt Trigger Level is 4 bytes.
0010 = RX FIFO Interrupt Trigger Level is 8 bytes.
0011 = RX FIFO Interrupt Trigger Level is 14 bytes.
Others = Reserved.
[8] RXOFF Receiver Disable
The receiver is disabled or not (set 1 to disable receiver)
0 = Receiver Enabled.
1 = Receiver Disabled.
Note: This bit is used for RS-485 Normal Multi-drop mode.
It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed.
[19:16] RTSTRGLV nRTS Trigger Level For Auto-Flow Control Use
0000 = nRTS Trigger Level is 1 bytes.
0001 = nRTS Trigger Level is 4bytes.
0010 = nRTS Trigger Level is 8 bytes.
0011 = nRTS Trigger Level is 14 bytes.
Others = Reserved.
Note: This field is used for auto nRTS flow control.

Definition at line 11885 of file M471M_R1_S.h.

◆ FIFOCTL

SPI_T::FIFOCTL

Offset: 0x10 SPI FIFO Control Register

Bits Field Descriptions
[0] RXRST Receive Reset
0 = No effect.
1 = Reset receive FIFO pointer and receive circuit. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1.
This bit will be cleared to 0 by hardware about 3 system clock cycles + 3 peripheral clock cycles after it is set to 1.
User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not.
Note: If there is slave receive time-out event, the RXRST will be set 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
[1] TXRST Transmit Reset
0 = No effect.
1 = Reset transmit FIFO pointer and transmit circuit. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1.
This bit will be cleared to 0 by hardware about 3 system clock cycles + 3 peripheral clock cycles after it is set to 1.
User can read TXRXRST (SPI_STATUS[23]) to check if reset is accomplished or not.
Note: If there is slave receive time-out event, the TXRST will be set to 1 when the SLVTORST (SPI_SSCTL[6]) is enabled.
[2] RXTHIEN Receive FIFO Threshold Interrupt Enable Bit
0 = RX FIFO threshold interrupt Disabled.
1 = RX FIFO threshold interrupt Enabled.
[3] TXTHIEN Transmit FIFO Threshold Interrupt Enable Bit
0 = TX FIFO threshold interrupt Disabled.
1 = TX FIFO threshold interrupt Enabled.
[4] RXTOIEN Slave Receive Time-Out Interrupt Enable Bit
0 = Receive time-out interrupt Disabled.
1 = Receive time-out interrupt Enabled.
[5] RXOVIEN Receive FIFO Overrun Interrupt Enable Bit
0 = Receive FIFO overrun interrupt Disabled.
1 = Receive FIFO overrun interrupt Enabled.
[6] TXUFPOL TX Underflow Data Polarity
0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode.
1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode.
Note: The TX underflow event occurs if there is not any data in TX FIFO when the slave selection signal is active.
[7] TXUFIEN TX Underflow Interrupt Enable Bit
In Slave mode, when TX underflow event occurs, this interrupt flag will be set to 1.
0 = Slave TX underflow interrupt Disabled.
1 = Slave TX underflow interrupt Enabled.
[8] RXFBCLR Receive FIFO Buffer Clear
0 = No effect.
1 = Clear receive FIFO pointer. The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1.
This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
Note: The RX shift register will not be cleared.
[9] TXFBCLR Transmit FIFO Buffer Clear
0 = No effect.
1 = Clear transmit FIFO pointer. The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1.
This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1.
Note: The TX shift register will not be cleared.
[26:24] RXTH Receive FIFO Threshold
If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
In SPI0, RXTH is a 3-bit wide configuration; in SPI1, 2-bit wide only (SPI_FIFOCTL[25:24]).
[30:28] TXTH Transmit FIFO Threshold
If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
In SPI0, TXTH is a 3-bit wide configuration; in SPI1, 2-bit wide only (SPI_FIFOCTL[29:28]).

Definition at line 9309 of file M471M_R1_S.h.

◆ FIFOSTS

UART_T::FIFOSTS

Offset: 0x18 UART FIFO Status Register

Bits Field Descriptions
[0] RXOVIF RX Overflow Error Interrupt Flag (Read Only)
This bit is set when RX FIFO overflow.
If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 16 bytes this bit will be set.
0 = RX FIFO is not overflow.
1 = RX FIFO is overflow.
Note: This bit is read only, but can be cleared by writing "1" to it.
[1] ABRDIF Auto-Baud Rate Detect Interrupt (Read Only)
0 = Auto-baud rate detect function is not finished.
1 = Auto-baud rate detect function is finished.
This bit is set to logic "1" when auto-baud rate detect function is finished.
Note: This bit is read only, but can be cleared by writing "1" to it.
[2] ABRDTOIF Auto-Baud Rate Time-Out Interrupt (Read Only)
0 = Auto-baud rate counter is underflow.
1 = Auto-baud rate counter is overflow.
Note1: This bit is set to logic "1" in Auto-baud Rate Detect mode and the baud rate counter is overflow.
Note2: This bit is read only, but can be cleared by writing "1" to it.
[3] ADDRDETF RS-485 Address Byte Detect Flag (Read Only)
0 = Receiver detects a data that is not an address bit (bit 9 ='0').
1 = Receiver detects a data that is an address bit (bit 9 ='1').
Note1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode .
Note2: This bit is read only, but can be cleared by writing '1' to it.
[4] PEF Parity Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid "parity bit".
0 = No parity error is generated.
1 = Parity error is generated.
Note: This bit is read only, but can be cleared by writing '1' to it.
[5] FEF Framing Error Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
0 = No framing error is generated.
1 = Framing error is generated.
Note: This bit is read only, but can be cleared by writing '1' to it.
[6] BIF Break Interrupt Flag (Read Only)
This bit is set to logic 1 whenever the received data input (RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits).
0 = No Break interrupt is generated.
1 = Break interrupt is generated.
Note: This bit is read only, but can be cleared by writing '1' to it.
[13:8] RXPTR RX FIFO Pointer (Read Only)
This field indicates the RX FIFO Buffer Pointer.
When UART receives one byte from external device, RXPTR increases one.
When one byte of RX FIFO is read by CPU, RXPTR decreases one.
The Maximum value shown in RXPTR is 15.
When the using level of RX FIFO Buffer equal to 16, the RXFULL bit is set to 1 and RXPTR will show 0.
As one byte of RX FIFO is read by CPU, the RXFULL bit is cleared to 0 and RXPTR will show 15.
[14] RXEMPTY Receiver FIFO Empty (Read Only)
This bit initiate RX FIFO empty or not.
0 = RX FIFO is not empty.
1 = RX FIFO is empty.
Note: When the last byte of RX FIFO has been read by CPU, hardware sets this bit high.
It will be cleared when UART receives any new data.
[15] RXFULL Receiver FIFO Full (Read Only)
This bit initiates RX FIFO full or not.
0 = RX FIFO is not full.
1 = RX FIFO is full.
Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
[21:16] TXPTR TX FIFO Pointer (Read Only)
This field indicates the TX FIFO Buffer Pointer.
When CPU writes one byte into UART_DAT, TXPTR increases one.
When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
The Maximum value shown in TXPTR is 15.
When the using level of TX FIFO Buffer equal to 16, the TXFULL bit is set to 1 and TXPTR will show 0.
As one byte of TX FIFO is transferred to Transmitter Shift Register, the TXFULL bit is cleared to 0 and TXPTR will show 15.
[22] TXEMPTY Transmitter FIFO Empty (Read Only)
This bit indicates TX FIFO empty or not.
0 = TX FIFO is not empty.
1 = TX FIFO is empty.
Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high.
It will be cleared when writing data into DAT (TX FIFO not empty).
[23] TXFULL Transmitter FIFO Full (Read Only)
This bit indicates TX FIFO full or not.
0 = TX FIFO is not full.
1 = TX FIFO is full.
Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16, otherwise is cleared by hardware.
[24] TXOVIF TX Overflow Error Interrupt Flag (Read Only)
If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to logic 1.
0 = TX FIFO is not overflow.
1 = TX FIFO is overflow.
Note: This bit is read only, but can be cleared by writing "1" to it.
[28] TXEMPTYF Transmitter Empty Flag (Read Only)
This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
0 = TX FIFO is not empty.
1 = TX FIFO is empty.
Note: This bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.

Definition at line 11889 of file M471M_R1_S.h.

◆ FREQADJ

RTC_T::FREQADJ

Offset: 0x08 RTC Frequency Compensation Register

Bits Field Descriptions
[5:0] FRACTION Fraction Part
Formula = (fraction part of detected value) x 60.
Note: Digit in RTC_FREQADJ must be expressed as hexadecimal number.
[11:8] INTEGER Integer Part

Definition at line 7639 of file M471M_R1_S.h.

◆ FTCBUF0_1

PWM_T::FTCBUF0_1

Offset: 0x340 PWM FTCMPDAT0_1 Buffer

Bits Field Descriptions
[15:0] FTCMPBUF PWM FTCMPDAT Buffer (Read Only)
Used as FTCMPDAT active register.

Definition at line 5896 of file M471M_R1_S.h.

◆ FTCBUF2_3

PWM_T::FTCBUF2_3

Offset: 0x344 PWM FTCMPDAT2_3 Buffer

Bits Field Descriptions
[15:0] FTCMPBUF PWM FTCMPDAT Buffer (Read Only)
Used as FTCMPDAT active register.

Definition at line 5897 of file M471M_R1_S.h.

◆ FTCBUF4_5

PWM_T::FTCBUF4_5

Offset: 0x348 PWM FTCMPDAT4_5 Buffer

Bits Field Descriptions
[15:0] FTCMPBUF PWM FTCMPDAT Buffer (Read Only)
Used as FTCMPDAT active register.

Definition at line 5898 of file M471M_R1_S.h.

◆ FTCI

PWM_T::FTCI

Offset: 0x34C PWM FTCMPDAT Indicator Register

Bits Field Descriptions
[2:0] FTCMUn PWM FTCMPDAT Up Indicator
Indicator will be set to high when FTCMPDATn equal to PERIODn and DIRF=1, software can write 1 to clear this bit.
Each bit n controls the corresponding PWM channel n.
[10:8] FTCMDn PWM FTCMPDAT Down Indicator
Indicator will be set to high when FTCMPDATn equal to PERIODn and DIRF=0, software can write 1 to clear this bit.
Each bit n controls the corresponding PWM channel n.

Definition at line 5899 of file M471M_R1_S.h.

◆ FTCMPDAT0_1

PWM_T::FTCMPDAT0_1

Offset: 0x100 PWM Free Trigger Compare Register 0

Bits Field Descriptions
[15:0] FTCMP PWM Free Trigger Compare Register
FTCMP use to compare with even CNTR to trigger EADC.
FTCMPDAT0, 2, 4 corresponding complementary pairs PWM_CH0and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.

Definition at line 5861 of file M471M_R1_S.h.

◆ FTCMPDAT2_3

PWM_T::FTCMPDAT2_3

Offset: 0x104 PWM Free Trigger Compare Register 2

Bits Field Descriptions
[15:0] FTCMP PWM Free Trigger Compare Register
FTCMP use to compare with even CNTR to trigger EADC.
FTCMPDAT0, 2, 4 corresponding complementary pairs PWM_CH0and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.

Definition at line 5862 of file M471M_R1_S.h.

◆ FTCMPDAT4_5

PWM_T::FTCMPDAT4_5

Offset: 0x108 PWM Free Trigger Compare Register 4

Bits Field Descriptions
[15:0] FTCMP PWM Free Trigger Compare Register
FTCMP use to compare with even CNTR to trigger EADC.
FTCMPDAT0, 2, 4 corresponding complementary pairs PWM_CH0and PWM_CH1, PWM_CH2 and PWM_CH3, PWM_CH4 and PWM_CH5.

Definition at line 5863 of file M471M_R1_S.h.

◆ FTCTL

FMC_T::FTCTL

Offset: 0x18 Flash Access Time Control Register

Bits Field Descriptions
[6:4] FOM Frequency Optimization Mode (Write Protect)
The NuMicro M471M/R1/S support adjustable flash access timing to optimize the flash access cycles in different working frequency.
001 = Frequency <= 12MHz.
010 = Frequency <= 36MHz.
100 = Frequency <= 60MHz.
Others = Frequency <= 72MHz.

Definition at line 2341 of file M471M_R1_S.h.

◆ FUNCSEL

UART_T::FUNCSEL

Offset: 0x30 UART Function Select Register

Bits Field Descriptions
[1:0] FUNCSEL Function Select
00 = UART function.
01 = LIN function (Only Available in UART0/UART1 Channel).
10 = IrDA function.
11 = RS-485 function.
Note: In IrDA function mode (FUNCSEL(UART_FUNCSEL[1:0])=10), the first received data is unreliable and it should be skipped if IrDA receiver is enabled (TXEN(UART_IRDA[1])=0) at the first time.

Definition at line 11895 of file M471M_R1_S.h.

◆ GPA_MFPH

SYS_T::GPA_MFPH

Offset: 0x34 GPIOA High Byte Multiple Function Control Register

Bits Field Descriptions
[3:0] PA8MFP PA.8 Multi-function Pin Selection
[7:4] PA9MFP PA.9 Multi-function Pin Selection
[11:8] PA10MFP PA.10 Multi-function Pin Selection
[15:12] PA11MFP PA.11 Multi-function Pin Selection
[19:16] PA12MFP PA.12 Multi-function Pin Selection
[23:20] PA13MFP PA.13 Multi-function Pin Selection
[27:24] PA14MFP PA.14 Multi-function Pin Selection
[31:28] PA15MFP PA.15 Multi-function Pin Selection

Definition at line 10321 of file M471M_R1_S.h.

◆ GPA_MFPL

SYS_T::GPA_MFPL

Offset: 0x30 GPIOA Low Byte Multiple Function Control Register

Bits Field Descriptions
[3:0] PA0MFP PA.0 Multi-function Pin Selection
[7:4] PA1MFP PA.1 Multi-function Pin Selection
[11:8] PA2MFP PA.2 Multi-function Pin Selection
[15:12] PA3MFP PA.3 Multi-function Pin Selection
[19:16] PA4MFP PA.4 Multi-function Pin Selection
[23:20] PA5MFP PA.5 Multi-function Pin Selection
[27:24] PA6MFP PA.6 Multi-function Pin Selection
[31:28] PA7MFP PA.7 Multi-function Pin Selection

Definition at line 10320 of file M471M_R1_S.h.

◆ GPB_MFPH

SYS_T::GPB_MFPH

Offset: 0x3C GPIOB High Byte Multiple Function Control Register

Bits Field Descriptions
[3:0] PB8MFP PB.8 Multi-function Pin Selection
[7:4] PB9MFP PB.9 Multi-function Pin Selection
[11:8] PB10MFP PB.10 Multi-function Pin Selection
[15:12] PB11MFP PB.11 Multi-function Pin Selection
[19:16] PB12MFP PB.12 Multi-function Pin Selection
[23:20] PB13MFP PB.13 Multi-function Pin Selection
[27:24] PB14MFP PB.14 Multi-function Pin Selection
[31:28] PB15MFP PB.15 Multi-function Pin Selection

Definition at line 10323 of file M471M_R1_S.h.

◆ GPB_MFPL

SYS_T::GPB_MFPL

Offset: 0x38 GPIOB Low Byte Multiple Function Control Register

Bits Field Descriptions
[3:0] PB0MFP PB.0 Multi-function Pin Selection
[7:4] PB1MFP PB.1 Multi-function Pin Selection
[11:8] PB2MFP PB.2 Multi-function Pin Selection
[15:12] PB3MFP PB.3 Multi-function Pin Selection
[19:16] PB4MFP PB.4 Multi-function Pin Selection
[23:20] PB5MFP PB.5 Multi-function Pin Selection
[27:24] PB6MFP PB.6 Multi-function Pin Selection
[31:28] PB7MFP PB.7 Multi-function Pin Selection

Definition at line 10322 of file M471M_R1_S.h.

◆ GPC_MFPH

SYS_T::GPC_MFPH

Offset: 0x44 GPIOC High Byte Multiple Function Control Register

Bits Field Descriptions
[3:0] PC8MFP PC.8 Multi-function Pin Selection
[7:4] PC9MFP PC.9 Multi-function Pin Selection
[11:8] PC10MFP PC.10 Multi-function Pin Selection
[15:12] PC11MFP PC.11 Multi-function Pin Selection
[19:16] PC12MFP PC.12 Multi-function Pin Selection
[23:20] PC13MFP PC.13 Multi-function Pin Selection
[27:24] PC14MFP PC.14 Multi-function Pin Selection
[31:28] PC15MFP PC.15 Multi-function Pin Selection

Definition at line 10325 of file M471M_R1_S.h.

◆ GPC_MFPL

SYS_T::GPC_MFPL

Offset: 0x40 GPIOC Low Byte Multiple Function Control Register

Bits Field Descriptions
[3:0] PC0MFP PC.0 Multi-function Pin Selection
[7:4] PC1MFP PC.1 Multi-function Pin Selection
[11:8] PC2MFP PC.2 Multi-function Pin Selection
[15:12] PC3MFP PC.3 Multi-function Pin Selection
[19:16] PC4MFP PC.4 Multi-function Pin Selection
[23:20] PC5MFP PC.5 Multi-function Pin Selection
[27:24] PC6MFP PC.6 Multi-function Pin Selection
[31:28] PC7MFP PC.7 Multi-function Pin Selection

Definition at line 10324 of file M471M_R1_S.h.

◆ GPD_MFPH

SYS_T::GPD_MFPH

Offset: 0x4C GPIOD High Byte Multiple Function Control Register

Bits Field Descriptions
[3:0] PD8MFP PD.8 Multi-function Pin Selection
[7:4] PD9MFP PD.9 Multi-function Pin Selection
[11:8] PD10MFP PD.10 Multi-function Pin Selection
[15:12] PD11MFP PD.11 Multi-function Pin Selection
[19:16] PD12MFP PD.12 Multi-function Pin Selection
[23:20] PD13MFP PD.13 Multi-function Pin Selection
[27:24] PD14MFP PD.14 Multi-function Pin Selection
[31:28] PD15MFP PD.15 Multi-function Pin Selection

Definition at line 10327 of file M471M_R1_S.h.

◆ GPD_MFPL

SYS_T::GPD_MFPL

Offset: 0x48 GPIOD Low Byte Multiple Function Control Register

Bits Field Descriptions
[3:0] PD0MFP PD.0 Multi-function Pin Selection
[7:4] PD1MFP PD.1 Multi-function Pin Selection
[11:8] PD2MFP PD.2 Multi-function Pin Selection
[15:12] PD3MFP PD.3 Multi-function Pin Selection
[19:16] PD4MFP PD.4 Multi-function Pin Selection
[23:20] PD5MFP PD.5 Multi-function Pin Selection
[27:24] PD6MFP PD.6 Multi-function Pin Selection
[31:28] PD7MFP PD.7 Multi-function Pin Selection

Definition at line 10326 of file M471M_R1_S.h.

◆ GPE_MFPH

SYS_T::GPE_MFPH

Offset: 0x54 GPIOE High Byte Multiple Function Control Register

Bits Field Descriptions
[3:0] PE8MFP PE.8 Multi-function Pin Selection
[7:4] PE9MFP PE.9 Multi-function Pin Selection
[11:8] PE10MFP PE.10 Multi-function Pin Selection
[15:12] PE11MFP PE.11 Multi-function Pin Selection
[19:16] PE12MFP PE.12 Multi-function Pin Selection
[23:20] PE13MFP PE.13 Multi-function Pin Selection
[27:24] PE14_MFP PE.14 Multi-function Pin Selection

Definition at line 10329 of file M471M_R1_S.h.

◆ GPE_MFPL

SYS_T::GPE_MFPL

Offset: 0x50 GPIOE Low Byte Multiple Function Control Register

Bits Field Descriptions
[3:0] PE0MFP PE.0 Multi-function Pin Selection
[7:4] PE1MFP PE.1 Multi-function Pin Selection
[11:8] PE2MFP PE.2 Multi-function Pin Selection
[15:12] PE3MFP PE.3 Multi-function Pin Selection
[19:16] PE4MFP PE.4 Multi-function Pin Selection
[23:20] PE5MFP PE.5 Multi-function Pin Selection
[27:24] PE6MFP PE.6 Multi-function Pin Selection
[31:28] PE7MFP PE.7 Multi-function Pin Selection

Definition at line 10328 of file M471M_R1_S.h.

◆ GPF_MFPL

SYS_T::GPF_MFPL

Offset: 0x58 GPIOF Low Byte Multiple Function Control Register

Bits Field Descriptions
[3:0] PF0MFP PF.0 Multi-function Pin Selection
[7:4] PF1MFP PF.1 Multi-function Pin Selection
[11:8] PF2MFP PF.2 Multi-function Pin Selection
[15:12] PF3MFP PF.3 Multi-function Pin Selection
[19:16] PF4MFP PF.4 Multi-function Pin Selection
[23:20] PF5MFP PF.5 Multi-function Pin Selection
[27:24] PF6MFP PF.6 Multi-function Pin Selection
[31:28] PF7MFP PF.7 Multi-function Pin Selection

Definition at line 10330 of file M471M_R1_S.h.

◆ HcBulkCurrentED

USBH_T::HcBulkCurrentED

Offset: 0x2C Host Controller Bulk Current ED Register

Bits Field Descriptions
[31:4] BCED Bulk Current Head ED
Pointer to indicate the physical address of the current endpoint of the Bulk list.

Definition at line 13223 of file M471M_R1_S.h.

◆ HcBulkHeadED

USBH_T::HcBulkHeadED

Offset: 0x28 Host Controller Bulk Head ED Register

Bits Field Descriptions
[31:4] BHED Bulk Head ED
Pointer to indicate the physical address of the first Endpoint Descriptor of the Bulk list.

Definition at line 13222 of file M471M_R1_S.h.

◆ HcCommandStatus

USBH_T::HcCommandStatus

Offset: 0x08 Host Controller CMD Status Register

Bits Field Descriptions
[0] HCR Host Controller Reset
This bit is set to initiate the software reset of Host Controller.
This bit is cleared by the Host Controller, upon completed of the reset operation.
This bit, when set, didn't reset the Root Hub and no subsequent reset signaling be asserted to its downstream ports.
0 = Host Controller is not in software reset state.
1 = Host Controller is in software reset state.
[1] CLF Control List Filled
Set high to indicate there is an active TD on the Control List.
It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List.
0 = No active TD found or Host Controller begins to process the head of the Control list.
1 = An active TD added or found on the Control list.
[2] BLF Bulk List Filled
Set high to indicate there is an active TD on the Bulk list.
This bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk list.
0 = No active TD found or Host Controller begins to process the head of the Bulk list.
1 = An active TD added or found on the Bulk list.
[17:16] SOC Schedule Overrun Count
These bits are incremented on each scheduling overrun error.
It is initialized to 00b and wraps around at 11b.
This will be incremented when a scheduling overrun is detected even if SO (HcIntSts[0]) has already been set.

Definition at line 13214 of file M471M_R1_S.h.

◆ HcControl

USBH_T::HcControl

Offset: 0x04 Host Controller Control Register

Bits Field Descriptions
[1:0] CBSR Control Bulk Service Ratio
This specifies the service ratio between Control and Bulk EDs.
Before processing any of the non-periodic lists, HC must compare the ratio specified with its internal count on how many nonempty Control EDs have been processed, in determining whether to continue serving another Control ED or switching to Bulk EDs.
The internal count will be retained when crossing the frame boundary.
In case of reset, HCD is responsible for restoring this.
Value.
00 = Number of Control EDs over Bulk EDs served is 1:1.
01 = Number of Control EDs over Bulk EDs served is 2:1.
10 = Number of Control EDs over Bulk EDs served is 3:1.
11 = Number of Control EDs over Bulk EDs served is 4:1.
[2] PLE Periodic List Enable Bit
When set, this bit enables processing of the Periodic (interrupt and Isochronous) list.
The Host Controller checks this bit prior to attempting any periodic transfers in a frame.
0 = Disable the processing of the Periodic (Interrupt and Isochronous) list after next SOF (Start-Of-Frame).
1 = Enable the processing of the Periodic (Interrupt and Isochronous) list in the next frame.
Note: To enable the processing of the Isochronous list, user has to set both PLE and IE (HcControl[3]) high.
[3] IE Isochronous List Enable Bit
Both ISOEn and PLE (HcControl[2]) high enables Host Controller to process the Isochronous list.
Either ISOEn or PLE (HcControl[2]) is low disables Host Controller to process the Isochronous list.
0 = Disable the processing of the Isochronous list after next SOF (Start-Of-Frame).
1 = Enable the processing of the Isochronous list in the next frame if the PLE (HcControl[2]) is high, too.
[4] CLE Control List Enable Bit
0 = Disable processing of the Control list after next SOF (Start-Of-Frame).
1 = Enable processing of the Control list in the next frame.
[5] BLE Bulk List Enable Bit
0 = Disable processing of the Bulk list after next SOF (Start-Of-Frame).
1 = Enable processing of the Bulk list in the next frame.
[7:6] HCFS Host Controller Functional State
This field sets the Host Controller state.
The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port.
States are:
00 = USBSUSPEND.
01 = USBRESUME.
10 = USBOPERATIONAL.
11 = USBRESET.

Definition at line 13213 of file M471M_R1_S.h.

◆ HcControlCurrentED

USBH_T::HcControlCurrentED

Offset: 0x24 Host Controller Control Current ED Register

Bits Field Descriptions
[31:4] CCED Control Current Head ED
Pointer to indicate the physical address of the current Endpoint Descriptor of the Control list.

Definition at line 13221 of file M471M_R1_S.h.

◆ HcControlHeadED

USBH_T::HcControlHeadED

Offset: 0x20 Host Controller Control Head ED Register

Bits Field Descriptions
[31:4] CHED Control Head ED
Pointer to indicate physical address of the first Endpoint Descriptor of the Control list.

Definition at line 13220 of file M471M_R1_S.h.

◆ HcDoneHead

USBH_T::HcDoneHead

Offset: 0x30 Host Controller Done Head Register

Bits Field Descriptions
[31:4] DH Done Head
Pointer to indicate the physical address of the last completed Transfer Descriptor that was added to the Done queue.

Definition at line 13224 of file M471M_R1_S.h.

◆ HcFmInterval

USBH_T::HcFmInterval

Offset: 0x34 Host Controller Frame Interval Register

Bits Field Descriptions
[13:0] FI Frame Interval
This field specifies the length of a frame as (bit times - 1).
For 12,000 bit times in a frame, a value of 11,999 is stored here.
[30:16] FSMPS FS Largest Data Packet
This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame.
[31] FIT Frame Interval Toggle
This bit is toggled by Host Controller Driver when it loads a new value into FI (HcFmIntv[13:0]).
0 = Host Controller Driver didn't load new value into FI (HcFmIntv[13:0]).
1 = Host Controller Driver loads a new value into FI (HcFmIntv[13:0]).

Definition at line 13225 of file M471M_R1_S.h.

◆ HcFmNumber

USBH_T::HcFmNumber

Offset: 0x3C Host Controller Frame Number Register

Bits Field Descriptions
[15:0] FN Frame Number
This 16-bit incrementing counter field is incremented coincident with the re-load of FR (HcFmRem[13:0]).
The count rolls over from 'FFFFh' to '0h.'.

Definition at line 13227 of file M471M_R1_S.h.

◆ HcFmRemaining

USBH_T::HcFmRemaining

Offset: 0x38 Host Controller Frame Remaining Register

Bits Field Descriptions
[13:0] FR Frame Remaining
When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period.
When the count reaches 0, (end of frame) the counter reloads with Frame Interval.
In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL.
[31] FRT Frame Remaining Toggle
This bit is loaded from the FIT (HcFmIntv[31]) whenever FR (HcFmRem[13:0]) reaches 0.

Definition at line 13226 of file M471M_R1_S.h.

◆ HcHCCA

USBH_T::HcHCCA

Offset: 0x18 Host Controller Communication Area Register

Bits Field Descriptions
[31:8] HCCA Host Controller Communication Area
Pointer to indicate base address of the Host Controller Communication Area (HCCA).

Definition at line 13218 of file M471M_R1_S.h.

◆ HcInterruptDisable

USBH_T::HcInterruptDisable

Offset: 0x14 Host Controller Interrupt Disable Register

Bits Field Descriptions
[0] SO Scheduling Overrun Disable Bit
Write Operation:
0 = No effect.
1 = Disable interrupt generation due to SO (HcIntSts[0]).
Read Operation:
0 = Interrupt generation due to SO (HcIntSts[0]) disabled.
1 = Interrupt generation due to SO (HcIntSts[0]) enabled.
[1] WDH Write Back Done Head Disable Bit
Write Operation:
0 = No effect.
1 = Disable interrupt generation due to WDH (HcIntSts[1]).
Read Operation:
0 = Interrupt generation due to WDH (HcIntSts[1]) disabled.
1 = Interrupt generation due to WDH (HcIntSts[1]) enabled.
[2] SF Start Of Frame Disable Bit
Write Operation:
0 = No effect.
1 = Disable interrupt generation due to SF (HcIntSts[2]).
Read Operation:
0 = Interrupt generation due to SF (HcIntSts[2]) disabled.
1 = Interrupt generation due to SF (HcIntSts[2]) enabled.
[3] RD Resume Detected Disable Bit
Write Operation:
0 = No effect.
1 = Disable interrupt generation due to RD (HcIntSts[3]).
Read Operation:
0 = Interrupt generation due to RD (HcIntSts[3]) disabled.
1 = Interrupt generation due to RD (HcIntSts[3]) enabled.
[5] FNO Frame Number Overflow Disable Bit
Write Operation:
0 = No effect.
1 = Disable interrupt generation due to FNO (HcIntSts[5]).
Read Operation:
0 = Interrupt generation due to FNO (HcIntSts[5]) disabled.
1 = Interrupt generation due to FNO (HcIntSts[5]) enabled.
[6] RHSC Root Hub Status Change Disable Bit
Write Operation:
0 = No effect.
1 = Disable interrupt generation due to RHSC (HcIntSts[6]).
Read Operation:
0 = Interrupt generation due to RHSC (HcIntSts[6]) disabled.
1 = Interrupt generation due to RHSC (HcIntSts[6]) enabled.
[31] MIE Master Interrupt Disable Bit
Global interrupt disable. Writing '1' to disable all interrupts.
Write Operation:
0 = No effect.
1 = Disable interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) if the corresponding bit in HcIntEn is high.
Read Operation:
0 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) disabled even if the corresponding bit in HcIntEn is high.
1 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) enabled if the corresponding bit in HcIntEn is high.

Definition at line 13217 of file M471M_R1_S.h.

◆ HcInterruptEnable

USBH_T::HcInterruptEnable

Offset: 0x10 Host Controller Interrupt Enable Register

Bits Field Descriptions
[0] SO Scheduling Overrun Enable Bit
Write Operation:
0 = No effect.
1 = Enable interrupt generation due to SO (HcIntSts[0]).
Read Operation:
0 = Interrupt generation due to SO (HcIntSts[0]) disabled.
1 = Interrupt generation due to SO (HcIntSts[0]) enabled.
[1] WDH Write Back Done Head Enable Bit
Write Operation:
0 = No effect.
1 = Enable interrupt generation due to WDH (HcIntSts[1]).
Read Operation:
0 = Interrupt generation due to WDH (HcIntSts[1]) disabled.
1 = Interrupt generation due to WDH (HcIntSts[1]) enabled.
[2] SF Start Of Frame Enable Bit
Write Operation:
0 = No effect.
1 = Enable interrupt generation due to SF (HcIntSts[2]).
Read Operation:
0 = Interrupt generation due to SF (HcIntSts[2]) disabled.
1 = Interrupt generation due to SF (HcIntSts[2]) enabled.
[3] RD Resume Detected Enable Bit
Write Operation:
0 = No effect.
1 = Enable interrupt generation due to RD (HcIntSts[3]).
Read Operation:
0 = Interrupt generation due to RD (HcIntSts[3]) disabled.
1 = Interrupt generation due to RD (HcIntSts[3]) enabled.
[5] FNO Frame Number Overflow Enable Bit
Write Operation:
0 = No effect.
1 = Enable interrupt generation due to FNO (HcIntSts[5]).
Read Operation:
0 = Interrupt generation due to FNO (HcIntSts[5]) disabled.
1 = Interrupt generation due to FNO (HcIntSts[5]) enabled.
[6] RHSC Root Hub Status Change Enable Bit
Write Operation:
0 = No effect.
1 = Enable interrupt generation due to RHSC (HcIntSts[6]).
Read Operation:
0 = Interrupt generation due to RHSC (HcIntSts[6]) disabled.
1 = Interrupt generation due to RHSC (HcIntSts[6]) enabled.
[31] MIE Master Interrupt Enable Bit
This bit is a global interrupt enable.
A write of '1' allows interrupts to be enabled via the specific enable bits listed above.
Write Operation:
0 = No effect.
1 = Enable interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) if the corresponding bit in HcIntEn is high.
Read Operation:
0 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) disabled even if the corresponding bit in HcIntEn is high.
1 = Interrupt generation due to RHSC (HcIntSts[6]), FNO (HcIntSts[5]), RD (HcIntSts[3]), SF (HcIntSts[2]), WDH (HcIntSts[1]) or SO (HcIntSts[0]) enabled if the corresponding bit in HcIntEn is high.

Definition at line 13216 of file M471M_R1_S.h.

◆ HcInterruptStatus

USBH_T::HcInterruptStatus

Offset: 0x0C Host Controller Interrupt Status Register

Bits Field Descriptions
[0] SO Scheduling Overrun
Set when the List Processor determines a Schedule Overrun has occurred.
0 = Schedule Overrun didn't occur.
1 = Schedule Overrun has occurred.
[1] WDH Write Back Done Head
Set after the Host Controller has written HcDoneHead to HccaDoneHead.
Further updates of the HccaDoneHead will not occur until this bit has been cleared.
0 =.Host Controller didn't update HccaDoneHead.
1 =.Host Controller has written HcDoneHead to HccaDoneHead.
[2] SF Start Of Frame
Set when the Frame Management functional block signals a 'Start of Frame' event.
Host Control generates a SOF token at the same time.
0 =.Not the start of a frame.
1 =.Indicate the start of a frame and Host Controller generates a SOF token.
[3] RD Resume Detected
Set when Host Controller detects resume signaling on a downstream port.
0 = No resume signaling detected on a downstream port.
1 = Resume signaling detected on a downstream port.
[5] FNO Frame Number Overflow
This bit is set when bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
0 = The bit 15 of Frame Number didn't change.
1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
[6] RHSC Root Hub Status Change
This bit is set when the content of HcRhSts or the content of HcRhPrt1 register has changed.
0 = The content of HcRhSts and the content of HcRhPrt1 register didn't change.
1 = The content of HcRhSts or the content of HcRhPrt1 register has changed.

Definition at line 13215 of file M471M_R1_S.h.

◆ HcLSThreshold

USBH_T::HcLSThreshold

Offset: 0x44 Host Controller Low-speed Threshold Register

Bits Field Descriptions
[11:0] LST Low-Speed Threshold
This field contains a value which is compared to the FR (HcFmRem[13:0]) field prior to initiating a Low-speed transaction.
The transaction is started only if FR (HcFmRem[13:0]) >= this field.
The value is calculated by Host Controller Driver with the consideration of transmission and setup overhead.

Definition at line 13229 of file M471M_R1_S.h.

◆ HcMiscControl

USBH_T::HcMiscControl

Offset: 0x204 USB Host Controller Miscellaneous Control Register

Bits Field Descriptions
[1] ABORT AHB Bus ERROR Response
This bit indicates there is an ERROR response received in AHB bus.
0 = No ERROR response received.
1 = ERROR response received.
[3] OCAL Over Current Active Low
This bit controls the polarity of over current flag from external power IC.
0 = Over current flag is high active.
1 = Over current flag is low active.
[16] DPRT1 Disable Port 1
This bit controls if the connection between USB host controller and transceiver of port 1 is disabled.
If the connection is disabled, the USB host controller will not recognize any event of USB bus.
Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is.
0 = The connection between USB host controller and transceiver of port 1 is enabled.
1 = The connection between USB host controller and transceiver of port 1 is disabled and the transceiver of port 1 will also be forced into the standby mode.

Definition at line 13236 of file M471M_R1_S.h.

◆ HcPeriodCurrentED

USBH_T::HcPeriodCurrentED

Offset: 0x1C Host Controller Period Current ED Register

Bits Field Descriptions
[31:4] PCED Periodic Current ED
Pointer to indicate physical address of the current Isochronous or Interrupt Endpoint Descriptor.

Definition at line 13219 of file M471M_R1_S.h.

◆ HcPeriodicStart

USBH_T::HcPeriodicStart

Offset: 0x40 Host Controller Periodic Start Register

Bits Field Descriptions
[13:0] PS Periodic Start
This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.

Definition at line 13228 of file M471M_R1_S.h.

◆ HcPhyControl

USBH_T::HcPhyControl

Offset: 0x200 USB Host Controller PHY Control Register

Bits Field Descriptions
[27] STBYEN USB Transceiver Standby Enable Bit
This bit controls if USB transceiver could enter the standby mode to reduce power consumption.
0 = The USB transceiver would never enter the standby mode.
1 = The USB transceiver will enter standby mode while port is in power off state (port power is inactive).

Definition at line 13235 of file M471M_R1_S.h.

◆ HcRevision

USBH_T::HcRevision

Offset: 0x00 Host Controller Revision Register

Bits Field Descriptions
[7:0] REV Revision Number
Indicates the Open HCI Specification revision number implemented by the Hardware.
Host Controller supports 1.1 specification.
(X.Y = XYh).

Definition at line 13212 of file M471M_R1_S.h.

◆ HcRhDescriptorA

USBH_T::HcRhDescriptorA

Offset: 0x48 Host Controller Root Hub Descriptor A Register

Bits Field Descriptions
[7:0] NDP Number Downstream Ports
USB host control supports two downstream ports and only one port is available in this series of chip.
[8] PSM Power Switching Mode
This bit is used to specify how the power switching of the Root Hub ports is controlled.
0 = Global Switching.
1 = Individual Switching.
[11] OCPM Over Current Protection Mode
This bit describes how the over current status for the Root Hub ports reported.
This bit is only valid when NOCP (HcRhDeA[12]) is cleared.
0 = Global Over current.
1 = Individual Over current.
[12] NOCP No Over Current Protection
This bit describes how the over current status for the Root Hub ports reported.
0 = Over current status is reported.
1 = Over current status is not reported.

Definition at line 13230 of file M471M_R1_S.h.

◆ HcRhDescriptorB

USBH_T::HcRhDescriptorB

Offset: 0x4C Host Controller Root Hub Descriptor B Register

Bits Field Descriptions
[31:16] PPCM Port Power Control Mask
Global power switching.
This field is only valid if PowerSwitchingMode is set (individual port switching).
When set, the port only responds to individual port power switching commands (Set/ClearPortPower).
When cleared, the port only responds to global power switching commands (Set/ClearGlobalPower).
0 = Port power controlled by global power switching.
1 = Port power controlled by port power switching.
Note: PPCM[15:2] and PPCM[0] are reserved.

Definition at line 13231 of file M471M_R1_S.h.

◆ HcRhPortStatus

USBH_T::HcRhPortStatus

Offset: 0x54 Host Controller Root Hub Port Status [1]

Bits Field Descriptions
[0] CCS CurrentConnectStatus (Read) Or ClearPortEnable Bit (Write)
Write Operation:
0 = No effect.
1 = Clear port enable.
Read Operation:
0 = No device connected.
1 = Device connected.
[1] PES Port Enable Status
Write Operation:
0 = No effect.
1 = Set port enable.
Read Operation:
0 = Port Disabled.
1 = Port Enabled.
[2] PSS Port Suspend Status
This bit indicates the port is suspended
Write Operation:
0 = No effect.
1 = Set port suspend.
Read Operation:
0 = Port is not suspended.
1 = Port is selectively suspended.
[3] POCI Port Over Current Indicator (Read) Or Clear Port Suspend (Write)
This bit reflects the state of the over current status pin dedicated to this port.
This field is only valid if NOCP (HcRhDeA[12]) is cleared and OCPM (HcRhDeA[11]) is set.
This bit is also used to initiate the selective result sequence for the port.
Write Operation:
0 = No effect.
1 = Clear port suspend.
Read Operation:
0 = No over current condition.
1 = Over current condition.
[4] PRS Port Reset Status
This bit reflects the reset state of the port.
Write Operation:
0 = No effect.
1 = Set port reset.
Read Operation
0 = Port reset signal is not active.
1 = Port reset signal is active.
[8] PPS Port Power Status
This bit reflects the power state of the port regardless of the power switching mode.
Write Operation:
0 = No effect.
1 = Port Power Enabled.
Read Operation:
0 = Port power is Disabled.
1 = Port power is Enabled.
[9] LSDA Low Speed Device Attached (Read) Or Clear Port Power (Write)
This bit defines the speed (and bud idle) of the attached device.
It is only valid when CCS (HcRhPrt1[0]) is set.
This bit is also used to clear port power.
Write Operation:
0 = No effect.
1 = Clear PPS (HcRhPrt1[8]).
Read Operation:
0 = Full Speed device.
1 = Low-speed device.
[16] CSC Connect Status Change
This bit indicates connect or disconnect event has been detected (CCS
(HcRhPrt1[0]) changed).
Write 1 to clear this bit to zero.
0 = No connect/disconnect event (CCS (HcRhPrt1[0]) didn't change).
1 = Hardware detection of connect/disconnect event (CCS
(HcRhPrt1[0]) changed).
[17] PESC Port Enable Status Change
This bit indicates that the port has been disabled (PES (HcRhPrt1[1]) cleared) due to a hardware event.
Write 1 to clear this bit to zero.
0 = PES (HcRhPrt1[1]) didn't change.
1 = PES (HcRhPrt1[1]) changed.
[18] PSSC Port Suspend Status Change
This bit indicates the completion of the selective resume sequence for the port.
Write 1 to clear this bit to zero.
0 = Port resume is not completed.
1 = Port resume completed.
[19] OCIC Port Over Current Indicator Change
This bit is set when POCI (HcRhPrt1[3]) changes.
Write 1 to clear this bit to zero.
0 = POCI (HcRhPrt1[3]) didn't change.
1 = POCI (HcRhPrt1[3]) changes.
[20] PRSC Port Reset Status Change
This bit indicates that the port reset signal has completed.
Write 1 to clear this bit to zero.
0 = Port reset is not complete.
1 = Port reset is complete.

Definition at line 13233 of file M471M_R1_S.h.

◆ HcRhStatus

USBH_T::HcRhStatus

Offset: 0x50 Host Controller Root Hub Status Register

Bits Field Descriptions
[0] LPS Clear Global Power
In global power mode (PSM (HcRhDeA[8]) = 0), this bit is written to one to clear all ports' power.
This bit always read as zero.
Write Operation:
0 = No effect.
1 = Clear global power.
[1] OCI Over Current Indicator
This bit reflects the state of the over current status pin.
This field is only valid if NOCP (HcRhDesA[12]) and OCPM (HcRhDesA[11]) are cleared.
0 = No over current condition.
1 = Over current condition.
[15] DRWE Device Remote Wakeup Enable Bit
This bit controls if port's Connect Status Change as a remote wake-up event.
Write Operation:
0 = No effect.
1 = Enable Connect Status Change as a remote wake-up event.
Read Operation:
0 = Connect Status Change as a remote wake-up event disabled.
1 = Connect Status Change as a remote wake-up event enabled.
[16] LPSC Set Global Power
In global power mode (PSM (HcRhDeA[8]) = 0), this bit is written to one to enable power to all ports.
This bit always read as zero.
Write Operation:
0 = No effect.
1 = Set global power.
[17] OCIC Over Current Indicator Change
This bit is set by hardware when a change has occurred in OCI (HcRhSts[1]).
Write 1 to clear this bit to zero.
0 = OCI (HcRhSts[1]) didn't change.
1 = OCI (HcRhSts[1]) change.
[31] CRWE Clear Remote Wake-up Enable Bit
This bit is use to clear DRWE (HcRhSts[15]).
This bit always read as zero.
Write Operation:
0 = No effect.
1 = Clear DRWE (HcRhSts[15]).

Definition at line 13232 of file M471M_R1_S.h.

◆ I2SCLK

SPI_T::I2SCLK

Offset: 0x64 I2S Clock Divider Control Register

Bits Field Descriptions
[5:0] MCLKDIV Master Clock Divider
If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices.
The master clock rate, F_MCLK, is determined by the following expressions.
If MCLKDIV >= 1, F_MCLK = F_I2SCLK/(2x(MCLKDIV)).
If MCLKDIV = 0, F_MCLK = F_I2SCLK.
F_I2SCLK is the frequency of I2S peripheral clock.
In general, the master clock rate is 256 times sampling clock rate.
[16:8] BCLKDIV Bit Clock Divider
The I2S controller will generate bit clock in Master mode.
The bit clock rate, F_BCLK, is determined by the following expression.
F_BCLK = F_I2SCLK /(2x(BCLKDIV + 1)) , where F_I2SCLK is the frequency of I2S peripheral clock.

Definition at line 9317 of file M471M_R1_S.h.

◆ I2SCTL

SPI_T::I2SCTL

Offset: 0x60 I2S Control Register

Bits Field Descriptions
[0] I2SEN I2S Controller Enable Bit
0 = Disabled.
1 = Enabled.
Note: If enable this bit, I2Sn_BCLK will start to output in master mode.
[1] TXEN Transmit Enable Bit
0 = Data transmit Disabled.
1 = Data transmit Enabled.
[2] RXEN Receive Enable Bit
0 = Data receiving Disabled.
1 = Data receiving Enabled.
[3] MUTE Transmit Mute Enable Bit
0 = Transmit data is shifted from buffer.
1= Transmit channel zero.
[5:4] WDWIDTH Word Width
00 = data is 8-bit.
01 = data is 16-bit.
10 = data is 24-bit.
11 = data is 32-bit.
[6] MONO Monaural Data
0 = Data is stereo format.
1 = Data is monaural format.
[7] ORDER Stereo Data Order In FIFO
0 = Left channel data at high byte.
1 = Left channel data at low byte.
[8] SLAVE Slave Mode
I2S can operate as master or slave.
For Master mode, I2Sn_BCLK and I2Sn_LRCLK pins are output mode and send bit clock from NuMicro M471M/R1/S to Audio CODEC chip.
In Slave mode, I2Sn_BCLK and I2Sn_LRCLK pins are input mode and I2Sn_BCLK and I2Sn_LRCLK signals are received from outer Audio CODEC chip.
0 = Master mode.
1 = Slave mode.
[15] MCLKEN Master Clock Enable Bit
If MCLKEN is set to 1, I2S controller will generate master clock on I2Sn_MCLK pin for external audio devices.
0 = Master clock Disabled.
1 = Master clock Enabled.
[16] RZCEN Right Channel Zero Cross Detection Enable Bit
If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPI_I2SSTS register is set to 1.
This function is only available in transmit operation.
0 = Right channel zero cross detection Disabled.
1 = Right channel zero cross detection Enabled.
[17] LZCEN Left Channel Zero Cross Detection Enable Bit
If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPI_I2SSTS register is set to 1.
This function is only available in transmit operation.
0 = Left channel zero cross detection Disabled.
1 = Left channel zero cross detection Enabled.
[23] RXLCH Receive Left Channel Enable Bit
When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1.
0 = Receive right channel data in Mono mode.
1 = Receive left channel data in Mono mode.
[24] RZCIEN Right Channel Zero-Cross Interrupt Enable Bit
Interrupt occurs if this bit is set to 1 and right channel zero-cross event occurs.
0 = Interrupt Disabled.
1 = Interrupt Enabled.
[25] LZCIEN Left Channel Zero-Cross Interrupt Enable Bit
Interrupt occurs if this bit is set to 1 and left channel zero-cross event occurs.
0 = Interrupt Disabled.
1 = Interrupt Enabled.
[29:28] FORMAT Data Format Selection
00 = I2S data format.
01 = MSB justified data format.
10 = PCM mode A.
11 = PCM mode B.

Definition at line 9316 of file M471M_R1_S.h.

◆ I2SSTS

SPI_T::I2SSTS

Offset: 0x68 I2S Status Register

Bits Field Descriptions
[4] RIGHT Right Channel (Read Only)
This bit indicates the current transmit data is belong to which channel.
0 = Left channel.
1 = Right channel.
[8] RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only)
0 = Receive FIFO buffer is not empty.
1 = Receive FIFO buffer is empty.
[9] RXFULL Receive FIFO Buffer Full Indicator (Read Only)
0 = Receive FIFO buffer is not full.
1 = Receive FIFO buffer is full.
[10] RXTHIF Receive FIFO Threshold Interrupt Flag (Read Only)
0 = The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RXTH.
1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request.
[11] RXOVIF Receive FIFO Overrun Interrupt Flag
When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
Note: This bit will be cleared by writing 1 to it.
[12] RXTOIF Receive Time-Out Interrupt Flag
0 = No receive FIFO time-out event.
1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode.
When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
Note: This bit will be cleared by writing 1 to it.
[15] I2SENSTS I2S Enable Status (Read Only)
0 = The SPI/I2S control logic is disabled.
1 = The SPI/I2S control logic is enabled.
Note: The SPI peripheral clock is asynchronous with the system clock.
In order to make sure the SPI/I2S controller logic is disabled, this bit indicates the real status of SPI/I2S controller logic for user.
[16] TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only)
0 = Transmit FIFO buffer is not empty.
1 = Transmit FIFO buffer is empty.
[17] TXFULL Transmit FIFO Buffer Full Indicator (Read Only)
0 = Transmit FIFO buffer is not full.
1 = Transmit FIFO buffer is full.
[18] TXTHIF Transmit FIFO Threshold Interrupt Flag (Read Only)
0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI controller will generate a SPI interrupt request.
[19] TXUFIF Transmit FIFO Underflow Interrupt Flag
When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input,
the output data depends on the setting of TXUFPOL and this bit will be set to 1.
Note: This bit will be cleared by writing 1 to it.
[20] RZCIF Right Channel Zero Cross Interrupt Flag
0 = No zero cross event occurred on right channel.
1 = Zero cross event occurred on right channel.
[21] LZCIF Left Channel Zero Cross Interrupt Flag
0 = No zero cross event occurred on left channel.
1 = Zero cross event occurred on left channel.
[23] TXRXRST TX or RX Reset Status (Read Only)
0 = The reset function of TXRST or RXRST is done.
1 = Doing the reset function of TXRST or RXRST.
Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 3 peripheral clock cycles.
User can check the status of this bit to monitor the reset function is doing or done.
[26:24] RXCNT Receive FIFO Data Count (Read Only)
This bit field indicates the valid data count of receive FIFO buffer.
[30:28] TXCNT Transmit FIFO Data Count (Read Only)
This bit field indicates the valid data count of transmit FIFO buffer.

Definition at line 9318 of file M471M_R1_S.h.

◆ IFA

PWM_T::IFA

Offset: 0xF0 PWM Interrupt Flag Accumulator Register

Bits Field Descriptions
[3:0] IFCNT0_1 PWM_CH0 And PWM_CH1 Interrupt Flag Counter
The register sets the count number which defines how many times of PWM_CH0 and PWM_CH1 period occurs to set bit IFAIF0_1 to request the PWM period interrupt.
PWM flag will be set in every IFCNT0_1 [3:0] times of PWM period.
[6:4] IFSEL0_1 PWM_CH0 And PWM_CH1 Interrupt Flag Accumulator Source Select
000 = CNT equal to Zero in channel 0.
001 = CNT equal to PERIOD in channel 0.
010 = CNT equal to CMPU in channel 0.
011 = CNT equal to CMPD in channel 0.
100 = CNT equal to Zero in channel 1.
101 = CNT equal to PERIOD in channel 1.
110 = CNT equal to CMPU in channel 1.
111 = CNT equal to CMPD in channel 1.
[7] IFAEN0_1 PWM_CH0 And PWM_CH1 Interrupt Flag Accumulator Enable
0 = PWM_CH0 and PWM_CH1 interrupt flag accumulator disable.
1 = PWM_CH0 and PWM_CH1 interrupt flag accumulator enable.
[11:8] IFCNT2_3 PWM_CH2 And PWM_CH3 Interrupt Flag Counter
The register sets the count number which defines how many times of PWM_CH2 and PWM_CH3 period occurs to set bit IFAIF2_3 to request the PWM period interrupt.
PWM flag will be set in every IFCNT2_3[3:0] times of PWM period.
[14:12] IFSEL2_3 PWM_CH2 And PWM_CH3 Interrupt Flag Accumulator Source Select
000 = CNT equal to Zero in channel 2.
001 = CNT equal to PERIOD in channel 2.
010 = CNT equal to CMPU in channel 2.
011 = CNT equal to CMPD in channel 2.
100 = CNT equal to Zero in channel 3.
101 = CNT equal to PERIOD in channel 3.
110 = CNT equal to CMPU in channel 3.
111 = CNT equal to CMPD in channel 3.
[15] IFAEN2_3 PWM_CH2 And PWM_CH3 Interrupt Flag Accumulator Enable
0 = PWM_CH2 and PWM_CH3 interrupt flag accumulator disable.
1 = PWM_CH2 and PWM_CH3 interrupt flag accumulator enable.
[19:16] IFCNT4_5 PWM_CH4 And PWM_CH5 Interrupt Flag Counter
The register sets the count number which defines how many times of PWM_CH4 and PWM_CH5 period occurs to set bit IFAIF4_5 to request the PWM period interrupt.
PWM flag will be set in every IFCNT4_5[3:0] times of PWM period.
[22:20] IFSEL4_5 PWM_CH4 And PWM_CH5 Interrupt Flag Accumulator Source Select
000 = CNT equal to Zero in channel 4.
001 = CNT equal to PERIOD in channel 4.
010 = CNT equal to CMPU in channel 4.
011 = CNT equal to CMPD in channel 4.
100 = CNT equal to Zero in channel 5.
101 = CNT equal to PERIOD in channel 5.
110 = CNT equal to CMPU in channel 5.
111 = CNT equal to CMPD in channel 5.
[23] IFAEN4_5 PWM_CH4 And PWM_CH5 Interrupt Flag Accumulator Enable
0 = PWM_CH4 and PWM_CH5 interrupt flag accumulator disable.
1 = PWM_CH4 and PWM_CH5 interrupt flag accumulator enable.

Definition at line 5857 of file M471M_R1_S.h.

◆ INIT

RTC_T::INIT

Offset: 0x00 RTC Initiation Register

Bits Field Descriptions
[0] INIT[0]/ACTIVE RTC Active Status (Read Only)
0 = RTC is at reset state.
1 = RTC is at normal active state.
[31:1] INIT[31:1] RTC Initiation
When RTC block is powered on, RTC is at reset state.
User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state.
Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
The INIT is a write-only field and read value will be always 0.

Definition at line 7637 of file M471M_R1_S.h.

◆ INTEN [1/6]

GPIO_T::INTEN

Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C Port A-F Interrupt Enable Control Register

Bits Field Descriptions
[n] FLIENn Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
Set bit to 1 also enable the pin wake-up function.
When setting the FLIEN (Px_INTEN[n]) bit to 1 :
If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
If the interrupt is edge trigger(TYPE (Px_INTTYPE[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
0 = Px.n level low or high to low interrupt Disabled.
1 = Px.n level low or high to low interrupt Enabled.
Note:
n=0~15 for port A/B/C/D.
n=0~14 for port E.
n=0~7 for port F.

Definition at line 2659 of file M471M_R1_S.h.

◆ INTEN [2/6]

PDMA_T::INTEN

Offset: 0x418 PDMA Interrupt Enable Register

Bits Field Descriptions
[11:0] INTENn PDMA Interrupt Enable Register
This field is used for enabling PDMA channel[n] interrupt.
0 = PDMA channel n interrupt Disabled.
1 = PDMA channel n interrupt Enabled.
[31:12] Reserved should be keep 0.

Definition at line 4331 of file M471M_R1_S.h.

◆ INTEN [3/6]

RTC_T::INTEN

Offset: 0x28 RTC Interrupt Enable Register

Bits Field Descriptions
[0] ALMIEN Alarm Interrupt Enable Bit
0 = RTC Alarm interrupt Disabled.
1 = RTC Alarm interrupt Enabled.
[1] TICKIEN Time Tick Interrupt Enable Bit
0 = RTC Time Tick interrupt Disabled.
1 = RTC Time Tick interrupt Enabled.
[2] SNPDIEN Snoop Detection Interrupt Enable Bit
0 = Snoop detected interrupt Disabled.
1 = Snoop detected interrupt Enabled.

Definition at line 7647 of file M471M_R1_S.h.

◆ INTEN [4/6]

SC_T::INTEN

Offset: 0x18 SC Interrupt Enable Control Register.

Bits Field Descriptions
[0] RDAIEN Receive Data Reach Interrupt Enable Bit
This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt enable.
0 = Receive data reach trigger level interrupt Disabled.
1 = Receive data reach trigger level interrupt Enabled.
[1] TBEIEN Transmit Buffer Empty Interrupt Enable Bit
This field is used for transmit buffer empty interrupt enable.
0 = Transmit buffer empty interrupt Disabled.
1 = Transmit buffer empty interrupt Enabled.
[2] TERRIEN Transfer Error Interrupt Enable Bit
This field is used for transfer error interrupt enable.
The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]), receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22]) and transmitter retry over limit error TXOVERR (SC_STATUS[30]).
0 = Transfer error interrupt Disabled.
1 = Transfer error interrupt Enabled.
[3] TMR0IEN Timer0 Interrupt Enable Bit
This field is used to enable TMR0 interrupt enable.
0 = Timer0 interrupt Disabled.
1 = Timer0 interrupt Enabled.
[4] TMR1IEN Timer1 Interrupt Enable Bit
This field is used to enable the TMR1 interrupt.
0 = Timer1 interrupt Disabled.
1 = Timer1 interrupt Enabled.
[5] TMR2IEN Timer2 Interrupt Enable Bit
This field is used for TMR2 interrupt enable.
0 = Timer2 interrupt Disabled.
1 = Timer2 interrupt Enabled.
[6] BGTIEN Block Guard Time Interrupt Enable Bit
This field is used for block guard time interrupt enable.
0 = Block guard time Disabled.
1 = Block guard time Enabled.
[7] CDIEN Card Detect Interrupt Enable Bit
This field is used for card detect interrupt enable. The card detect status is CINSERT(SC_STATUS[12])
0 = Card detect interrupt Disabled.
1 = Card detect interrupt Enabled.
[8] INITIEN Initial End Interrupt Enable Bit
This field is used for activation (ACTEN(SC_ALTCTL[3] = 1)), deactivation ((DACTEN SC_ALTCTL[2]) = 1) and warm reset (WARSTEN (SC_ALTCTL [4])) sequence interrupt enable.
0 = Initial end interrupt Disabled.
1 = Initial end interrupt Enabled.
[9] RXTOIF Receiver Buffer Time-Out Interrupt Enable Bit
This field is used for receiver buffer time-out interrupt enable.
0 = Receiver buffer time-out interrupt Disabled.
1 = Receiver buffer time-out interrupt Enabled.
[10] ACERRIEN Auto Convention Error Interrupt Enable Bit
This field is used for auto-convention error interrupt enable.
0 = Auto-convention error interrupt Disabled.
1 = Auto-convention error interrupt Enabled.

Definition at line 8498 of file M471M_R1_S.h.

◆ INTEN [5/6]

UART_T::INTEN

Offset: 0x04 UART Interrupt Enable Register

Bits Field Descriptions
[0] RDAIEN Receive Data Available Interrupt Enable Bit
0 = Receive data available interrupt Disabled.
1 = Receive data available interrupt Enabled.
[1] THREIEN Transmit Holding Register Empty Interrupt Enable Bit
0 = Transmit holding register empty interrupt Disabled.
1 = Transmit holding register empty interrupt Enabled.
[2] RLSIEN Receive Line Status Interrupt Enable Bit
0 = Receive Line Status interrupt Disabled.
1 = Receive Line Status interrupt Enabled.
[3] MODEMIEN Modem Status Interrupt Enable Bit
0 = Modem status interrupt Disabled.
1 = Modem status interrupt Enabled.
[4] RXTOIEN RX Time-Out Interrupt Enable Bit
0 = RX time-out interrupt Disabled.
1 = RX time-out interrupt Enabled.
[5] BUFERRIEN Buffer Error Interrupt Enable Bit
0 = Buffer error interrupt Disabled.
1 = Buffer error interrupt Enabled.
[8] LINIEN LIN Bus Interrupt Enable Bit (Not Available In UART2/UART3)
0 = LIN bus interrupt Disabled.
1 = LIN bus interrupt Enabled.
Note: This bit is used for LIN function mode.
[9] WKCTSIEN nCTS Wake-Up Interrupt Enable Bit
0 = nCTS wake-up system function Disabled.
1 = Wake-up system function Enabled, when the system is in Power-down mode, an external nCTS change will wake-up system from Power-down mode.
[10] WKDATIEN Incoming Data Wake-Up Interrupt Enable Bit
0 = Incoming data wake-up system function Disabled.
1 = Incoming data wake-up system function Enabled, when the system is in Power-down mode, incoming data will wake-up system from Power-down mode.
Note: Hardware will clear this bit when the incoming data wake-up operation finishes and "system clock" work stable
[11] TOCNTEN Time-Out Counter Enable Bit
0 = Time-out counter Disabled.
1 = Time-out counter Enabled.
[12] ATORTSEN nRTS Auto-Flow Control Enable Bit
0 = nRTS auto-flow control Disabled.
1 = nRTS auto-flow control Enabled.
Note: When nRTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert nRTS signal.
[13] ATOCTSEN nCTS Auto-Flow Control Enable Bit
0 = nCTS auto-flow control Disabled.
1 = nCTS auto-flow control Enabled.
Note: When nCTS auto-flow is enabled, the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted).
[14] TXPDMAEN TX DMA Enable Bit
This bit can enable or disable TX DMA service.
0 = TX DMA Disabled.
1 = TX DMA Enabled.
[15] RXPDMAEN RX DMA Enable Bit
This bit can enable or disable RX DMA service.
0 = RX DMA Disabled.
1 = RX DMA Enabled.
[18] ABRIEN Auto-Baud Rate Interrupt Enable Bit
0 = Auto-baud rate interrupt Disabled.
1 = Auto-baud rate interrupt Enabled.

Definition at line 11884 of file M471M_R1_S.h.

◆ INTEN [6/6]

USBD_T::INTEN

Offset: 0x00 USB Interrupt Enable Register

Bits Field Descriptions
[0] BUSIEN Bus Event Interrupt Enable
0 = BUS event interrupt Disabled.
1 = BUS event interrupt Enabled.
[1] USBIEN USB Event Interrupt Enable
0 = USB event interrupt Disabled.
1 = USB event interrupt Enabled.
[2] VBDETIEN VBUS Detection Interrupt Enable
0 = Floating detection Interrupt Disabled.
1 = Floating detection Interrupt Enabled.
[3] NEVWKIEN USB No-Event-Wake-Up Interrupt Enable
0 = No-Event-Wake-up Interrupt Disabled.
1 = No-Event-Wake-up Interrupt Enabled.
[8] WKEN Wake-Up Function Enable
0 = USB wake-up function Disabled.
1 = USB wake-up function Enabled.
[15] INNAKEN Active NAK Function And Its Status In IN Token
0 = When device responds NAK after receiving IN token, IN NAK status will not be
updated to USBD_EPSTS register, so that the USB interrupt event will not be asserted.
1 = IN NAK status will be updated to USBD_EPSTS register and the USB interrupt event
will be asserted, when the device responds NAK after receiving IN token.

Definition at line 12509 of file M471M_R1_S.h.

◆ INTEN0

PWM_T::INTEN0

Offset: 0xE0 PWM Interrupt Enable Register 0

Bits Field Descriptions
[5:0] ZIENn PWM Zero Point Interrupt Enable
Each bit n controls the corresponding PWM channel n.
0 = Zero point interrupt Disabled.
1 = Zero point interrupt Enabled.
Note: Odd channels will read always 0 at complementary mode.
[7] IFAIEN0_1 PWM_CH0/1 Interrupt Flag Accumulator Interrupt Enable
0 = Interrupt Flag accumulator interrupt Disabled.
1 = Interrupt Flag accumulator interrupt Enabled.
[13:8] PIENn PWM Period Point Interrupt Enable
Each bit n controls the corresponding PWM channel n.
0 = Period point interrupt Disabled.
1 = Period point interrupt Enabled.
Note1: When up-down counter type period point means center point.
Note2: Odd channels will read always 0 at complementary mode.
[15] IFAIEN2_3 PWM_CH2/3 Interrupt Flag Accumulator Interrupt Enable
0 = Interrupt Flag accumulator interrupt Disabled.
1 = Interrupt Flag accumulator interrupt Enabled.
[21:16] CMPUIENn PWM Compare Up Count Interrupt Enable
Each bit n controls the corresponding PWM channel n.
0 = Compare up count interrupt Disabled.
1 = Compare up count interrupt Enabled.
Note: In complementary mode, CMPUIEN1, 3, 5 use as another CMPUIEN for channel 0, 2, 4.
[23] IFAIEN4_5 PWM_CH4/5 Interrupt Flag Accumulator Interrupt Enable
0 = Interrupt Flag accumulator interrupt Disabled.
1 = Interrupt Flag accumulator interrupt Enabled.
[29:24] CMPDIENn PWM Compare Down Count Interrupt Enable
Each bit n controls the corresponding PWM channel n.
0 = Compare down count interrupt Disabled.
1 = Compare down count interrupt Enabled.
Note: In complementary mode, CMPDIEN1, 3, 5 use as another CMPDIEN for channel 0, 2, 4.

Definition at line 5853 of file M471M_R1_S.h.

◆ INTEN1

PWM_T::INTEN1

Offset: 0xE4 PWM Interrupt Enable Register 1

Bits Field Descriptions
[0] BRKEIEN0_1 PWM Edge-Detect Brake Interrupt Enable For Channel0/1 (Write Protect)
0 = Edge-detect Brake interrupt for channel0/1 Disabled.
1 = Edge-detect Brake interrupt for channel0/1 Enabled.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[1] BRKEIEN2_3 PWM Edge-Detect Brake Interrupt Enable For Channel2/3 (Write Protect)
0 = Edge-detect Brake interrupt for channel2/3 Disabled.
1 = Edge-detect Brake interrupt for channel2/3 Enabled.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[2] BRKEIEN4_5 PWM Edge-Detect Brake Interrupt Enable For Channel4/5 (Write Protect)
0 = Edge-detect Brake interrupt for channel4/5 Disabled.
1 = Edge-detect Brake interrupt for channel4/5 Enabled.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[8] BRKLIEN0_1 PWM Level-Detect Brake Interrupt Enable For Channel0/1 (Write Protect)
0 = Level-detect Brake interrupt for channel0/1 Disabled.
1 = Level-detect Brake interrupt for channel0/1 Enabled.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[9] BRKLIEN2_3 PWM Level-Detect Brake Interrupt Enable For Channel2/3 (Write Protect)
0 = Level-detect Brake interrupt for channel2/3 Disabled.
1 = Level-detect Brake interrupt for channel2/3 Enabled.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[10] BRKLIEN4_5 PWM Level-Detect Brake Interrupt Enable For Channel4/5 (Write Protect)
0 = Level-detect Brake interrupt for channel4/5 Disabled.
1 = Level-detect Brake interrupt for channel4/5 Enabled.
Note: This register is write protected. Refer to SYS_REGLCTL register.

Definition at line 5854 of file M471M_R1_S.h.

◆ INTSRC [1/2]

EADC_T::INTSRC

Offset: 0xDC ADC interrupt n Source Enable Control Register, n=0~3

Bits Field Descriptions
[0] SPLIE0 Sample Module 0 Interrupt Enable Bit
0 = Sample Module 0 interrupt Disabled.
1 = Sample Module 0 interrupt Enabled.
[1] SPLIE1 Sample Module 1 Interrupt Enable Bit
0 = Sample Module 1 interrupt Disabled.
1 = Sample Module 1 interrupt Enabled.
[2] SPLIE2 Sample Module 2 Interrupt Enable Bit
0 = Sample Module 2 interrupt Disabled.
1 = Sample Module 2 interrupt Enabled.
[3] SPLIE3 Sample Module 3 Interrupt Enable Bit
0 = Sample Module 3 interrupt Disabled.
1 = Sample Module 3 interrupt Enabled.
[4] SPLIE4 Sample Module 4 Interrupt Enable Bit
0 = Sample Module 4 interrupt Disabled.
1 = Sample Module 4 interrupt Enabled.
[5] SPLIE5 Sample Module 5 Interrupt Enable Bit
0 = Sample Module 5 interrupt Disabled.
1 = Sample Module 5 interrupt Enabled.
[6] SPLIE6 Sample Module 6 Interrupt Enable Bit
0 = Sample Module 6 interrupt Disabled.
1 = Sample Module 6 interrupt Enabled.
[7] SPLIE7 Sample Module 7 Interrupt Enable Bit
0 = Sample Module 7 interrupt Disabled.
1 = Sample Module 7 interrupt Enabled.
[8] SPLIE8 Sample Module 8 Interrupt Enable Bit
0 = Sample Module 8 interrupt Disabled.
1 = Sample Module 8 interrupt Enabled.
[9] SPLIE9 Sample Module 9 Interrupt Enable Bit
0 = Sample Module 9 interrupt Disabled.
1 = Sample Module 9 interrupt Enabled.
[10] SPLIE10 Sample Module 10 Interrupt Enable Bit
0 = Sample Module 10 interrupt Disabled.
1 = Sample Module 10 interrupt Enabled.
[11] SPLIE11 Sample Module 11 Interrupt Enable Bit
0 = Sample Module 11 interrupt Disabled.
1 = Sample Module 11 interrupt Enabled.
[12] SPLIE12 Sample Module 12 Interrupt Enable Bit
0 = Sample Module 12 interrupt Disabled.
1 = Sample Module 12 interrupt Enabled.
[13] SPLIE13 Sample Module 13 Interrupt Enable Bit
0 = Sample Module 13 interrupt Disabled.
1 = Sample Module 13 interrupt Enabled.
[14] SPLIE14 Sample Module 14 Interrupt Enable Bit
0 = Sample Module 14 interrupt Disabled.
1 = Sample Module 14 interrupt Enabled.
[15] SPLIE15 Sample Module 15 Interrupt Enable Bit
0 = Sample Module 15 interrupt Disabled.
1 = Sample Module 15 interrupt Enabled.
[16] SPLIE16 Sample Module 16 Interrupt Enable Bit
0 = Sample Module 16 interrupt Disabled.
1 = Sample Module 16 interrupt Enabled.
[17] SPLIE17 Sample Module 17 Interrupt Enable Bit
0 = Sample Module 17 interrupt Disabled.
1 = Sample Module 17 interrupt Enabled.
[18] SPLIE18 Sample Module 18 Interrupt Enable Bit
0 = Sample Module 18 interrupt Disabled.
1 = Sample Module 18 interrupt Enabled.

Definition at line 730 of file M471M_R1_S.h.

◆ INTSRC [2/2]

GPIO_T::INTSRC

Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160 Port A-F Interrupt Source Flag

Bits Field Descriptions
[n] INTSRCn Port A-F Pin[n] Interrupt Source Flag
Write Operation :
0 = No action.
1 = Clear the corresponding pending interrupt.
Read Operation :
0 = No interrupt at Px.n.
1 = Px.n generates an interrupt.
Note:
n=0~15 for port A/B/C/D.
n=0~14 for port E.
n=0~7 for port F.

Definition at line 2660 of file M471M_R1_S.h.

◆ INTSTS [1/6]

PDMA_T::INTSTS

Offset: 0x41C PDMA Interrupt Status Register

Bits Field Descriptions
[0] ABTIF PDMA Read/Write Target Abort Interrupt Flag (Read-Only)
This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error.
0 = No AHB bus ERROR response received.
1 = AHB bus ERROR response received.
[1] TDIF Transfer Done Interrupt Flag (Read Only)
This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer.
0 = Not finished yet.
1 = PDMA channel has finished transmission.
[2] TEIF Table Empty Interrupt Flag (Read Only)
This bit indicates that PDMA controller has finished each table transmission and the operation is Stop mode.
User can read TEIF register to indicate which channel finished transfer.
0 = PDMA channel transfer is not finished.
1 = PDMA channel transfer is finished and the operation is in idle state.
[8:15] REQTOFn Request Time-out Flag For Each Channel [N]
This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn, user can write 1 to clear these bits.
0 = No request time-out.
1 = Peripheral request time-out.

Definition at line 4332 of file M471M_R1_S.h.

◆ INTSTS [2/6]

RTC_T::INTSTS

Offset: 0x2C RTC Interrupt Indicator Register

Bits Field Descriptions
[0] ALMIF RTC Alarm Interrupt Flag
When RTC time counters RTC_TIME and RTC_CAL match the alarm setting time registers RTC_TALM and RTC_CALM, this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled ALMIEN (RTC_INTEN[0]) is set to 1.
Chip will be waken up if RTC Alarm Interrupt is enabled when chip is at Power-down mode.
0 = Alarm condition is not matched.
1 = Alarm condition is matched.
Note: Write 1 to clear this bit.
[1] TICKIF RTC Time Tick Interrupt Flag
When RTC time tick happened, this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled TICKIEN (RTC_INTEN[1]) is set to 1.
Chip will also be waken up if RTC Tick Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode.
0 = Tick condition does not occur.
1 = Tick condition occur.
Note: Write 1 to clear to clear this bit.
[2] SNPDIF Snoop Detect Interrupt Flag
When tamper pin transition event is detected, this bit is set to 1 and an interrupt is generated if Snoop Detection Interrupt enabled SNPDIEN (RTC_INTEN[2]) is set to1.
Chip will be waken up from Power-down mode if spare register snooper detect interrupt is enabled.
0 = No snoop event is detected.
1 = Snoop event is detected.
Note: Write 1 to clear this bit.

Definition at line 7648 of file M471M_R1_S.h.

◆ INTSTS [3/6]

SC_T::INTSTS

Offset: 0x1C SC Interrupt Status Register.

Bits Field Descriptions
[0] RDAIF Receive Data Reach Interrupt Status Flag (Read Only)
This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.
Note: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]).
If software reads data from SC_DAT and receiver buffer data byte number is less than RXTRGLV (SC_CTL[7:6]), this bit will be cleared automatically.
[1] TBEIF Transmit Buffer Empty Interrupt Status Flag (Read Only)
This field is used for transmit buffer empty interrupt status flag.
Note: This field is the status flag of transmit buffer empty state.
If software wants to clear this bit, software must write data to DAT(SC_DAT[7:0]) buffer and then this bit will be cleared automatically.
[2] TERRIF Transfer Error Interrupt Status Flag (Read Only)
This field is used for transfer error interrupt status flag.
The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]) and receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOV(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22]) and transmitter retry over limit error TXOVERR(SC_STATUS[30]).
Note: This field is the status flag of
BEF(SC_STATUS[6]), FEF(SC_STATUS[5]), PEF(SC_STATUS[4]), RXOV(SC_STATUS[0]), TXOV(SC_STATUS[8]), RXOVERR(SC_STATUS[22]) or TXOVERR(SC_STATUS[30]).
So, if software wants to clear this bit, software must write 1 to each field.
[3] TMR0IF Timer0 Interrupt Status Flag (Read Only)
This field is used for TMR0 interrupt status flag.
Note: This bit is read only, but it can be cleared by writing 1 to it.
[4] TMR1IF Timer1 Interrupt Status Flag (Read Only)
This field is used for TMR1 interrupt status flag.
Note: This bit is read only, but it can be cleared by writing 1 to it.
[5] TMR2IF Timer2 Interrupt Status Flag (Read Only)
This field is used for TMR2 interrupt status flag.
Note: This bit is read only, but it can be cleared by writing 1 to it.
[6] BGTIF Block Guard Time Interrupt Status Flag (Read Only)
This field is used for block guard time interrupt status flag.
Note1: This bit is valid when RXBGTEN (SC_ALTCTL[12]) is enabled.
Note2: This bit is read only, but it can be cleared by writing "1" to it.
[7] CDIF Card Detect Interrupt Status Flag (Read Only)
This field is used for card detect interrupt status flag.
The card detect status is CINSERT (SC_STATUS[12]) and CREMOVE(SC_STATUS[11]).
Note:
This field is the status flag of CINSERT(SC_STATUS[12]) or CREMOVE(SC_STATUS[11])].
So if software wants to clear this bit, software must write 1 to this field.
[8] INITIF Initial End Interrupt Status Flag (Read Only)
This field is used for activation (ACTEN(SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.
Note: This bit is read only, but it can be cleared by writing 1 to it.
[9] RBTOIF Receiver Buffer Time-Out Interrupt Status Flag (Read Only)
This field is used for receiver buffer time-out interrupt status flag.
Note: This field is the status flag of receiver buffer time-out state.
If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_DAT buffer,.
[10] ACERRIF Auto Convention Error Interrupt Status Flag (Read Only)
This field indicates auto convention sequence error.
If the received TS at ATR state is neither 0x3B nor 0x3F, this bit will be set.
Note: This bit is read only, but it can be cleared by writing 1 to it.

Definition at line 8499 of file M471M_R1_S.h.

◆ INTSTS [4/6]

TIMER_T::INTSTS

Offset: 0x08 Timer Interrupt Status Register

Bits Field Descriptions
[0] TIF Timer Interrupt Flag
This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches to CMPDAT (TIMERx_CMP[23:0]) value.
0 = No effect.
1 = CNT value matches the CMPDAT value.
Note: This bit is cleared by writing 1 to it.
[1] TWKF Timer Wake-Up Flag
This bit indicates the interrupt wake-up flag status of timer.
0 = Timer does not cause CPU wake-up.
1 = CPU wake-up from Idle or Power-down mode if timer time-out interrupt signal generated.
Note: This bit is cleared by writing 1 to it.

Definition at line 11254 of file M471M_R1_S.h.

◆ INTSTS [5/6]

UART_T::INTSTS

Offset: 0x1C UART Interrupt Status Register

Bits Field Descriptions
[0] RDAIF Receive Data Available Interrupt Flag (Read Only)
When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set.
If RDAIEN (UART_INTEN [0]) is enabled, the RDA interrupt will be generated.
0 = No RDA interrupt flag is generated.
1 = RDA interrupt flag is generated.
Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL(UART_FIFO[7:4])).
[1] THREIF Transmit Holding Register Empty Interrupt Flag (Read Only)
This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register.
If THREIEN (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.
0 = No THRE interrupt flag is generated.
1 = THRE interrupt flag is generated.
Note: This bit is read only and it will be cleared when writing data into UART_DAT (TX FIFO not empty).
[2] RLSIF Receive Line Interrupt Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]), is set).
If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
0 = No RLS interrupt flag is generated.
1 = RLS interrupt flag is generated.
Note1: In RS-485 function mode, this field is set include receiver detect and received address byte character (bit9 = '1') bit.
At the same time, the bit of ADDRDETF (UART_FIFOSTS[3]) is also set.
Note2: This bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF (UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
[3] MODEMIF MODEM Interrupt Flag (Read Only) Channel This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]) = 1). If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.
0 = No Modem interrupt flag is generated.
1 = Modem interrupt flag is generated.
Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0]).
[4] RXTOIF Time-Out Interrupt Flag (Read Only)
This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC.
If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.
0 = No Time-out interrupt flag is generated.
1 = Time-out interrupt flag is generated.
Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
[5] BUFERRIF Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set).
When BERRIF (UART_INTSTS[5])is set, the transfer is not correct.
If BFERRIEN (UART_INTEN [8]) is enabled, the buffer error interrupt will be generated.
0 = No buffer error interrupt flag is generated.
1 = Buffer error interrupt flag is generated.
Note: This bit is read only.
This bit is cleared if both of RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]) are cleared to 0 by writing 1 to RXOVIF(UART_FIFOSTS[0]) and TXOVIF(UART_FIFOSTS[24]).
[6] WKIF UART Wake-up Interrupt Flag (Read Only)
This bit is set when DATWKIF (UART_INTSTS[17]) or CTSWKIF(UART_INTSTS[16]) is set to 1.
0 = No DATWKIF and CTSWKIF are generated.
1 = DATWKIF or CTSWKIF.
Note: This bit is read only.
This bit is cleared if both of DATWKIF (UART_INTSTS[17]) and CTSWKIF(UART_INTSTS[16]) are cleared to 0 by writing 1 to DATWKIF (UART_INTSTS[17]) and CTSWKIF (UART_INTSTS[17]).
[7] LINIF LIN Bus Interrupt Flag (Read Only) (Not Available in UART2/UART3 Channel)
This bit is set when LIN slave header detect (SLVHDETF (UART_LINSTS[0] =1)), LIN break detect (BRKDETF(UART_LINSTS[9])=1), bit error detect (BITEF(UART_LINSTS[9])=1), LIN slave ID parity error (SLVIDPEF(UART_LINSTS[2]) = 1) or LIN slave header error detect (SLVHEF (UART_LINSTS[1])).
If LIN_ IEN (UART_INTEN [8]) is enabled the LIN interrupt will be generated.
0 = None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.
1 = At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.
Note: This bit is read only.
This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]), SLVHEF(UART_LINSTS[1]) and SLVSYNCF(UART_LINSTS[3]) all are cleared.
[8] RDAINT Receive Data Available Interrupt Indicator (Read Only)
This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
0 = No RDA interrupt is generated.
1 = RDA interrupt is generated.
[9] THREINT Transmit Holding Register Empty Interrupt Indicator (Read Only)
This bit is set if THREIEN (UART_INTEN[1])and THREIF(UART_INTSTS[1]) are both set to 1.
0 = No DATE interrupt is generated.
1 = DATE interrupt is generated.
[10] RLSINT Receive Line Status Interrupt Indicator (Read Only)
This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1.
0 = No RLS interrupt is generated.
1 = RLS interrupt is generated.
[11] MODEMINT MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[4]) are both set to 1
0 = No Modem interrupt is generated.
1 = Modem interrupt is generated.
[12] RXTOINT Time-Out Interrupt Indicator (Read Only)
This bit is set if TOUTIEN(UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1.
0 = No Tout interrupt is generated.
1 = Tout interrupt is generated.
[13] BUFERRINT Buffer Error Interrupt Indicator (Read Only)
This bit is set if BFERRIEN(UART_INTEN[5]) and BERRIF(UART_INTSTS[5]) are both set to 1.
0 = No buffer error interrupt is generated.
1 = Buffer error interrupt is generated.
[15] LININT LIN Bus Interrupt Indicator (Read Only)(Not Available in UART2/UART3 Channel)
This bit is set if LINIEN (UART_INTEN[8]) and LIN IF(UART_INTSTS[7]) are both set to 1.
0 = No LIN Bus interrupt is generated.
1 = The LIN Bus interrupt is generated.
[16] CTSWKIF nCTS Wake-Up Interrupt Flag (Read Only)
0 = Chip stays in power-down state.
1 = Chip wake-up from power-down state by nCTS wake-up.
Note1: If WKCTSIEN (UART_INTEN[9])is enabled, the wake-up interrupt is generated.
Note2: This bit is read only, but can be cleared by writing '1' to it.
[17] DATWKIF Data Wake-Up Interrupt Flag (Read Only)
This bit is set if chip wake-up from power-down state by data wake-up.
0 = Chip stays in power-down state.
1 = Chip wake-up from power-down state by data wake-up.
Note1: If WKDATIEN (UART_INTEN[10]) is enabled, the wake-up interrupt is generated.
Note2: This bit is read only, but can be cleared by writing '1' to it.
[18] HWRLSIF In DMA Mode, Receive Line Status Flag (Read Only)
This bit is set when the RX receive data have parity error, frame error or break error (at least one of 3 bits, BIF (UART_FIFOSTS[6]), FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set).
If RLSIEN (UART_INTEN [2]) is enabled, the RLS interrupt will be generated.
0 = No RLS interrupt flag is generated.
1 = RLS interrupt flag is generated.
Note1: In RS-485 function mode, this field include receiver detect any address byte received address byte character (bit9 = '1') bit.
Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared
[19] HWMODIF In DMA Mode, MODEM Interrupt Flag (Read Only)
This bit is set when the nCTS pin has state change (CTSDETF (UART_CTSDETF[0] =1)).
If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.
0 = No Modem interrupt flag is generated.
1 = Modem interrupt flag is generated.
Note: This bit is read only and reset to 0 when the bit UART_CTSDETF (US_MSR[0]) is cleared by writing 1 on CTSDETF (UART_CTSDETF [0]).
[20] HWTOIF In DMA Mode, Time-Out Interrupt Flag (Read Only)
This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0]).
If TOUTIEN (UART_INTEN [4]) is enabled, the Tout interrupt will be generated.
0 = No Time-out interrupt flag is generated.
1 = Time-out interrupt flag is generated.
Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
[21] HWBUFEIF In DMA Mode, Buffer Error Interrupt Flag (Read Only)
This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set).
When BERRIF (UART_INTSTS[5]) is set, the transfer maybe is not correct.
If BFERRIEN (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
0 = No buffer error interrupt flag is generated.
1 = Buffer error interrupt flag is generated.
Note: This bit is cleared when both TXOVIF (UART_FIFOSTS[24]]) and RXOVIF (UART_FIFOSTS[0]) are cleared.
[26] HWRLSINT In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)
This bit is set if RLSIEN (UART_INTEN[2])and HWRLSIF(UART_INTSTS[18]) are both set to 1.
0 = No RLS interrupt is generated in DMA mode.
1 = RLS interrupt is generated in DMA mode.
[27] HWMODINT In DMA Mode, MODEM Status Interrupt Indicator (Read Only)
This bit is set if MODEMIEN(UART_INTEN[3]) and HWMODIF(UART_INTSTS[3]) are both set to 1.
0 = No Modem interrupt is generated in DMA mode.
1 = Modem interrupt is generated in DMA mode.
[28] HWTOINT In DMA Mode, Time-Out Interrupt Indicator (Read Only)
This bit is set if TOUTIEN (UART_INTEN[4])and HWTOIF(UART_INTSTS[20]) are both set to 1.
0 = No Tout interrupt is generated in DMA mode.
1 = Tout interrupt is generated in DMA mode.
[29] HWBUFEINT In DMA Mode, Buffer Error Interrupt Indicator (Read Only)
This bit is set if BFERRIEN (UART_INTEN[5]) and HWBEIF (UART_INTSTS[5])are both set to 1.
0 = No buffer error interrupt is generated in DMA mode.
1 = Buffer error interrupt is generated in DMA mode.

Definition at line 11890 of file M471M_R1_S.h.

◆ INTSTS [6/6]

USBD_T::INTSTS

Offset: 0x04 USB Interrupt Event Status Register

Bits Field Descriptions
[0] BUSIF BUS Interrupt Status
The BUS event means that there is one of the suspense or the resume function in the bus.
0 = No BUS event occurred.
1 = Bus event occurred; check USB_ATTR[3:0] to know which kind of bus event was occurred, cleared by write 1 to USB_INTSTS[0].
[1] USBIF USB Event Interrupt Status
The USB event includes the SETUP Token, IN Token, OUT ACK, ISO IN, or ISO OUT events in the bus.
0 = No USB event occurred.
1 = USB event occurred, check EPSTS0~7 to know which kind of USB event occurred.
Cleared by write 1 to USB_INTSTS[1] or EPEVT0~7 and SETUP (USB_INTSTS[31]).
[2] VBDETIF VBUS Detection Interrupt Status
0 = There is not attached/detached event in the USB.
1 = There is attached/detached event in the USB bus and it is cleared by write 1 to USB_INTSTS[2].
[3] NEVWKIF USB No-Event-Wake-Up Interrupt Status
0 = No Wake-up event occurred.
1 = Wake-up event occurred, cleared by write 1 to USB_INTSTS[3].
[4] SOFIF Start of Frame Interrupt Status
0 = SOF event does not occur.
1 = SOF event occurred, cleared by write 1 to USBD_INTSTS[4].
[16] EPEVT0 Endpoint 0's USB Event Status
0 = No event occurred on endpoint 0.
1 = USB event occurred on Endpoint 0, check USB_EPSTS[10:8] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[16] or USB_INTSTS[1].
[17] EPEVT1 Endpoint 1's USB Event Status
0 = No event occurred on endpoint 1.
1 = USB event occurred on Endpoint 1, check USB_EPSTS[13:11] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[17] or USB_INTSTS[1].
[18] EPEVT2 Endpoint 2's USB Event Status
0 = No event occurred on endpoint 2.
1 = USB event occurred on Endpoint 2, check USB_EPSTS[16:14] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[18] or USB_INTSTS[1].
[19] EPEVT3 Endpoint 3's USB Event Status
0 = No event occurred on endpoint 3.
1 = USB event occurred on Endpoint 3, check USB_EPSTS[19:17] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[19] or USB_INTSTS[1].
[20] EPEVT4 Endpoint 4's USB Event Status
0 = No event occurred on endpoint 4.
1 = USB event occurred on Endpoint 4, check USB_EPSTS[22:20] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[20] or USB_INTSTS[1].
[21] EPEVT5 Endpoint 5's USB Event Status
0 = No event occurred on endpoint 5.
1 = USB event occurred on Endpoint 5, check USB_EPSTS[25:23] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[21] or USB_INTSTS[1].
[22] EPEVT6 Endpoint 6's USB Event Status
0 = No event occurred on endpoint 6.
1 = USB event occurred on Endpoint 6, check USB_EPSTS[28:26] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[22] or USB_INTSTS[1].
[23] EPEVT7 Endpoint 7's USB Event Status
0 = No event occurred on endpoint 7.
1 = USB event occurred on Endpoint 7, check USB_EPSTS[31:29] to know which kind of USB event was occurred, cleared by write 1 to USB_INTSTS[23] or USB_INTSTS[1].
[31] SETUP Setup Event Status
0 = No Setup event.
1 = SETUP event occurred, cleared by write 1 to USB_INTSTS[31].

Definition at line 12510 of file M471M_R1_S.h.

◆ INTSTS0

PWM_T::INTSTS0

Offset: 0xE8 PWM Interrupt Flag Register 0

Bits Field Descriptions
[5:0] ZIFn PWM Zero Point Interrupt Flag
Each bit n controls the corresponding PWM channel n.
This bit is set by hardware when PWM counter reaches zero, software can write 1 to clear this bit to zero.
[7] IFAIF0_1 PWM_CH0/1 Interrupt Flag Accumulator Interrupt Flag
Flag is set by hardware when condition match IFSEL0_1 in PWM_IFA register, software can clear this bit by writing 1 to it.
[13:8] PIFn PWM Period Point Interrupt Flag
This bit is set by hardware when PWM counter reaches PWM_PERIODn, software can write 1 to clear this bit to zero.
Each bit n controls the corresponding PWM channel n.
[15] IFAIF2_3 PWM_CH2/3 Interrupt Flag Accumulator Interrupt Flag
Flag is set by hardware when condition match IFSEL2_3 in PWM_IFA register, software can clear this bit by writing 1 to it.
[21:16] CMPUIFn PWM Compare Up Count Interrupt Flag
Flag is set by hardware when PWM counter up count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.
Each bit n controls the corresponding PWM channel n.
Note1: If CMPDAT equal to PERIOD, this flag is not working in up counter type selection.
Note2: In complementary mode, CMPUIF1, 3, 5 use as another CMPUIF for channel 0, 2, 4.
[23] IFAIF4_5 PWM_CH4/5 Interrupt Flag Accumulator Interrupt Flag
Flag is set by hardware when condition match IFSEL4_5 in PWM_IFA register, software can clear this bit by writing 1 to it.
[29:24] CMPDIFn PWM Compare Down Count Interrupt Flag
Each bit n controls the corresponding PWM channel n.
Flag is set by hardware when PWM counter down count and reaches PWM_CMPDATn, software can clear this bit by writing 1 to it.
Note1: If CMPDAT equal to PERIOD, this flag is not working in down counter type selection.
Note2: In complementary mode, CMPDIF1, 3, 5 use as another CMPDIF for channel 0, 2, 4.

Definition at line 5855 of file M471M_R1_S.h.

◆ INTSTS1

PWM_T::INTSTS1

Offset: 0xEC PWM Interrupt Flag Register 1

Bits Field Descriptions
[0] BRKEIF0 PWM Channel0 Edge-Detect Brake Interrupt Flag (Write Protect)
0 = PWM channel0 edge-detect brake event do not happened.
1 = When PWM channel0 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[1] BRKEIF1 PWM Channel1 Edge-Detect Brake Interrupt Flag (Write Protect)
0 = PWM channel1 edge-detect brake event do not happened.
1 = When PWM channel1 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[2] BRKEIF2 PWM Channel2 Edge-Detect Brake Interrupt Flag (Write Protect)
0 = PWM channel2 edge-detect brake event do not happened.
1 = When PWM channel2 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[3] BRKEIF3 PWM Channel3 Edge-Detect Brake Interrupt Flag (Write Protect)
0 = PWM channel3 edge-detect brake event do not happened.
1 = When PWM channel3 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[4] BRKEIF4 PWM Channel4 Edge-Detect Brake Interrupt Flag (Write Protect)
0 = PWM channel4 edge-detect brake event do not happened.
1 = When PWM channel4 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[5] BRKEIF5 PWM Channel5 Edge-Detect Brake Interrupt Flag (Write Protect)
0 = PWM channel5 edge-detect brake event do not happened.
1 = When PWM channel5 edge-detect brake event happened, this bit is set to 1, writing 1 to clear.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[8] BRKLIF0 PWM Channel0 Level-Detect Brake Interrupt Flag (Write Protect)
0 = PWM channel0 level-detect brake event do not happened.
1 = When PWM channel0 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[9] BRKLIF1 PWM Channel1 Level-Detect Brake Interrupt Flag (Write Protect)
0 = PWM channel1 level-detect brake event do not happened.
1 = When PWM channel1 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[10] BRKLIF2 PWM Channel2 Level-Detect Brake Interrupt Flag (Write Protect)
0 = PWM channel2 level-detect brake event do not happened.
1 = When PWM channel2 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[11] BRKLIF3 PWM Channel3 Level-Detect Brake Interrupt Flag (Write Protect)
0 = PWM channel3 level-detect brake event do not happened.
1 = When PWM channel3 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[12] BRKLIF4 PWM Channel4 Level-Detect Brake Interrupt Flag (Write Protect)
0 = PWM channel4 level-detect brake event do not happened.
1 = When PWM channel4 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[13] BRKLIF5 PWM Channel5 Level-Detect Brake Interrupt Flag (Write Protect)
0 = PWM channel5 level-detect brake event do not happened.
1 = When PWM channel5 level-detect brake event happened, this bit is set to 1, writing 1 to clear.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[16] BRKESTS0 PWM Channel0 Edge-Detect Brake Status
0 = PWM channel0 edge-detect brake state is released.
1 = When PWM channel0 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state, writing 1 to clear.
[17] BRKESTS1 PWM Channel1 Edge-Detect Brake Status
0 = PWM channel1 edge-detect brake state is released.
1 = When PWM channel1 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state, writing 1 to clear.
[18] BRKESTS2 PWM Channel2 Edge-Detect Brake Status
0 = PWM channel2 edge-detect brake state is released.
1 = When PWM channel2 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state, writing 1 to clear.
[19] BRKESTS3 PWM Channel3 Edge-Detect Brake Status
0 = PWM channel3 edge-detect brake state is released.
1 = When PWM channel3 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state, writing 1 to clear.
[20] BRKESTS4 PWM Channel4 Edge-Detect Brake Status
0 = PWM channel4 edge-detect brake state is released.
1 = When PWM channel4 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state, writing 1 to clear.
[21] BRKESTS5 PWM Channel5 Edge-Detect Brake Status
0 = PWM channel5 edge-detect brake state is released.
1 = When PWM channel5 edge-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state, writing 1 to clear.
[24] BRKLSTS0 PWM Channel0 Level-Detect Brake Status (Read Only)
0 = PWM channel0 level-detect brake state is released.
1 = When PWM channel0 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel0 at brake state.
Note: This bit is read only and auto cleared by hardware.
When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
The PWM waveform will start output from next full PWM period.
[25] BRKLSTS1 PWM Channel1 Level-Detect Brake Status (Read Only)
0 = PWM channel1 level-detect brake state is released.
1 = When PWM channel1 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel1 at brake state.
Note: This bit is read only and auto cleared by hardware.
When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
The PWM waveform will start output from next full PWM period.
[26] BRKLSTS2 PWM Channel2 Level-Detect Brake Status (Read Only)
0 = PWM channel2 level-detect brake state is released.
1 = When PWM channel2 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel2 at brake state.
Note: This bit is read only and auto cleared by hardware.
When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
The PWM waveform will start output from next full PWM period.
[27] BRKLSTS3 PWM Channel3 Level-Detect Brake Status (Read Only)
0 = PWM channel3 level-detect brake state is released.
1 = When PWM channel3 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel3 at brake state.
Note: This bit is read only and auto cleared by hardware.
When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
The PWM waveform will start output from next full PWM period.
[28] BRKLSTS4 PWM Channel4 Level-Detect Brake Status (Read Only)
0 = PWM channel4 level-detect brake state is released.
1 = When PWM channel4 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel4 at brake state.
Note: This bit is read only and auto cleared by hardware.
When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
The PWM waveform will start output from next full PWM period.
[29] BRKLSTS5 PWM Channel5 Level-Detect Brake Status (Read Only)
0 = PWM channel5 level-detect brake state is released.
1 = When PWM channel5 level-detect brake detects a falling edge of any enabled brake source; this flag will be set to indicate the PWM channel5 at brake state.
Note: This bit is read only and auto cleared by hardware.
When enabled brake source return to high level, PWM will release brake state until current PWM period finished.
The PWM waveform will start output from next full PWM period.

Definition at line 5856 of file M471M_R1_S.h.

◆ INTTYPE

GPIO_T::INTTYPE

Offset: 0x18/0x58/0x98/0xD8/0x118/0x158 Port A-F Interrupt Trigger Type Control

Bits Field Descriptions
[n] TYPEn Port A-F Pin[n] Edge Or Level Detection Interrupt Trigger Type Control
TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger.
If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
0 = Edge trigger interrupt.
1 = Level trigger interrupt.
If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]).
If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
The de-bounce function is valid only for edge triggered interrupt.
If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
Note:
n=0~15 for port A/B/C/D.
n=0~14 for port E.
n=0~7 for port F.

Definition at line 2658 of file M471M_R1_S.h.

◆ IPRST0

SYS_T::IPRST0

Offset: 0x08 Peripheral Reset Control Register 0

Bits Field Descriptions
[0] CHIPRST Chip One-Shot Reset (Write Protect)
Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.
About the difference between CHIPRST and SYSRESETREQ, please refer to section 5.2.2
0 = Chip normal operation.
1 = Chip one shot reset.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[1] CPURST Processor Core One-Shot Reset (Write Protect)
Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles.
0 = Processor core normal operation.
1 = Processor core one-shot reset.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[2] PDMARST PDMA Controller Reset (Write Protect)
Setting this bit to 1 will generate a reset signal to the PDMA.
User needs to set this bit to 0 to release from reset state.
0 = PDMA controller normal operation.
1 = PDMA controller reset.
[3] EBIRST EBI Controller Reset (Write Protect)
Set this bit to 1 will generate a reset signal to the EBI.
User needs to set this bit to 0 to release from the reset state.
0 = EBI controller normal operation.
1 = EBI controller reset.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[4] USBHRST USBH Controller Reset (Write Protect)
Set this bit to 1 will generate a reset signal to the USB host controller.
User needs to set this bit to 0 to release from the reset state.
0 = USBH controller normal operation.
1 = USBH controller reset.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[7] CRCRST CRC Calculation Unit Reset (Write Protect)
Set this bit to 1 will generate a reset signal to the CRC calculation module.
User needs to set this bit to 0 to release from the reset state.
0 = CRC Calculation unit normal operation.
1 = CRC Calculation unit reset.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 10310 of file M471M_R1_S.h.

◆ IPRST1

SYS_T::IPRST1

Offset: 0x0C Peripheral Reset Control Register 1

Bits Field Descriptions
[1] GPIORST GPIO Controller Reset
0 = GPIO controller normal operation.
1 = GPIO controller reset.
[2] TMR0RST Timer0 Controller Reset
0 = Timer0 controller normal operation.
1 = Timer0 controller reset.
[3] TMR1RST Timer1 Controller Reset
0 = Timer1 controller normal operation.
1 = Timer1 controller reset.
[4] TMR2RST Timer2 Controller Reset
0 = Timer2 controller normal operation.
1 = Timer2 controller reset.
[5] TMR3RST Timer3 Controller Reset
0 = Timer3 controller normal operation.
1 = Timer3 controller reset.
[8] I2C0RST I2C0 Controller Reset
0 = I2C0 controller normal operation.
1 = I2C0 controller reset.
[9] I2C1RST I2C1 Controller Reset
0 = I2C1 controller normal operation.
1 = I2C1 controller reset.
[12] SPI0RST SPI0 Controller Reset
0 = SPI0 controller normal operation.
1 = SPI0 controller reset.
[13] SPI1RST SPI1 Controller Reset
0 = SPI1 controller normal operation.
1 = SPI1 controller reset.
[16] UART0RST UART0 Controller Reset
0 = UART0 controller normal operation.
1 = UART0 controller reset.
[17] UART1RST UART1 Controller Reset
0 = UART1 controller normal operation.
1 = UART1 controller reset.
[18] UART2RST UART2 Controller Reset
0 = UART2 controller normal operation.
1 = UART2 controller reset.
[19] UART3RST UART3 Controller Reset
0 = UART3 controller normal operation.
1 = UART3 controller reset.
[27] USBDRST USB Device Controller Reset
0 = USB device controller normal operation.
1 = USB device controller reset.
[28] EADCRST EADC Controller Reset
0 = EADC controller normal operation.
1 = EADC controller reset.

Definition at line 10311 of file M471M_R1_S.h.

◆ IPRST2

SYS_T::IPRST2

Offset: 0x10 Peripheral Reset Control Register 2

Bits Field Descriptions
[0] SC0RST SC0 Controller Reset
0 = SC0 controller normal operation.
1 = SC0 controller reset.
[16] PWM0RST PWM0 Controller Reset
0 = PWM0 controller normal operation.
1 = PWM0 controller reset.
[17] PWM1RST PWM1 Controller Reset
0 = PWM1 controller normal operation.
1 = PWM1 controller reset.
[25] TKRST Touch Key Controller Reset
0 = Touch Key controller normal operation.
1 = Touch Key controller reset.

Definition at line 10312 of file M471M_R1_S.h.

◆ IRC48MTCTL

SYS_T::IRC48MTCTL

Offset: 0x130 IRC48M Trim Control Register

Bits Field Descriptions
[1:0] FREQSEL Trim Frequency Selection
This field indicates the target frequency of internal 48 MHz high-speed oscillator auto trim.
During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
00 = Disable HIRC auto trim function.
01 = Enable HIRC auto trim function and trim HIRC to 48 MHz.
10 = Reserved.
11 = Reserved.
[5:4] LOOPSEL Trim Calculation Loop Selection
This field defines that trim value calculation is based on how many reference clocks.
00 = Trim value calculation is based on average difference in 4 clocks of reference clock.
01 = Trim value calculation is based on average difference in 8 clocks of reference clock.
10 = Trim value calculation is based on average difference in 16 clocks of reference clock.
11 = Trim value calculation is based on average difference in 32 clocks of reference clock.
Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.
[7:6] RETRYCNT Trim Value Update Limitation Count
This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.
Once the HIRC locked, the internal trim value update counter will be reset.
If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
00 = Trim retry count limitation is 64 loops.
01 = Trim retry count limitation is 128 loops.
10 = Trim retry count limitation is 256 loops.
11 = Trim retry count limitation is 512 loops.
[8] CESTOPEN Clock Error Stop Enable Bit
0 = The trim operation is keep going if clock is inaccuracy.
1 = The trim operation is stopped if clock is inaccuracy.
[10] REFCKSEL Reference Clock Selection
0 = HIRC trim 48M reference clock is from LXT (32.768 kHz) or HXT(12MHz).
1 = HIRC trim 48M reference clock is from internal USB synchronous mode or HXT(12MHz).

Definition at line 10341 of file M471M_R1_S.h.

◆ IRC48MTIEN

SYS_T::IRC48MTIEN

Offset: 0x134 IRC48M Trim Interrupt Enable Register

Bits Field Descriptions
[1] TFAILIEN Trim Failure Interrupt Enable Bit
This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]).
If this bit is high and TFAILIF(SYS_IRCTSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
0 = Disable TFAILIF(SYS_IRC48MTSTS[1]) status to trigger an interrupt to CPU.
1 = Enable TFAILIF(SYS_IRC48MTSTS[1]) status to trigger an interrupt to CPU.
[2] CLKEIEN Clock Error Interrupt Enable Bit
This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.
If this bit is set to1, and CLKERRIF(SYS_IRCTSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
0 = Disable CLKERRIF(SYS_IRC48MTSTS[2]) status to trigger an interrupt to CPU.
1 = Enable CLKERRIF(SYS_IRC48MTSTS[2]) status to trigger an interrupt to CPU.

Definition at line 10342 of file M471M_R1_S.h.

◆ IRC48MTISTS

SYS_T::IRC48MTISTS

Offset: 0x138 IRC48M Trim Interrupt Status Register

Bits Field Descriptions
[0] FREQLOCK HIRC Frequency Lock Status
This bit indicates the internal 48 MHz high-speed oscillator frequency is locked.
This is a status bit and doesn't trigger any interrupt.
[1] TFAILIF Trim Failure Interrupt Status
This bit indicates that internal 48 MHz high-speed oscillator trim value update limitation count reached and the internal 48 MHz high-speed oscillator clock frequency still doesn't be locked.
Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_IRC48MTCTL[1:0]) will be cleared to 00 by hardware automatically.
If this bit is set and TFAILIEN(SYS_IRC48MTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
Write 1 to clear this to 0.
0 = Trim value update limitation count does not reach.
1 = Trim value update limitation count reached and internal 48 MHz high-speed oscillator frequency still not locked.
[2] CLKERRIF Clock Error Interrupt Status
When the frequency of external 32.768 kHz low-speed crystal or internal 48 MHz high-speed oscillator is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy
Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRC48MTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRC48MTCTL[8]) is set to 1.
If this bit is set and CLKEIEN(SYS_IRC48MTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy.
Write 1 to clear this to 0.
0 = Clock frequency is accuracy.
1 = Clock frequency is inaccuracy.

Definition at line 10343 of file M471M_R1_S.h.

◆ IRCTCTL

SYS_T::IRCTCTL

Offset: 0xF0 IRC Trim Control Register

Bits Field Descriptions
[1:0] FREQSEL Trim Frequency Selection
This field indicates the target frequency of internal 22.1184 MHz high-speed oscillator auto trim.
During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
00 = Disable HIRC auto trim function.
01 = Enable HIRC auto trim function and trim HIRC to 22.1184 MHz.
10 = Enable HIRC auto trim function and trim HIRC to 24 MHz.
11 = Reserved.
[5:4] LOOPSEL Trim Calculation Loop Selection
This field defines that trim value calculation is based on how many 32.768 kHz clock.
00 = Trim value calculation is based on average difference in 4 32.768 kHz clock.
01 = Trim value calculation is based on average difference in 8 32.768 kHz clock.
10 = Trim value calculation is based on average difference in 16 32.768 kHz clock.
11 = Trim value calculation is based on average difference in 32 32.768 kHz clock.
Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.
[7:6] RETRYCNT Trim Value Update Limitation Count
This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.
Once the HIRC locked, the internal trim value update counter will be reset.
If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
00 = Trim retry count limitation is 64 loops.
01 = Trim retry count limitation is 128 loops.
10 = Trim retry count limitation is 256 loops.
11 = Trim retry count limitation is 512 loops.
[8] CESTOPEN Clock Error Stop Enable Bit
0 = The trim operation is keep going if clock is inaccuracy.
1 = The trim operation is stopped if clock is inaccuracy.

Definition at line 10335 of file M471M_R1_S.h.

◆ IRCTIEN

SYS_T::IRCTIEN

Offset: 0xF4 IRC Trim Interrupt Enable Register

Bits Field Descriptions
[1] TFAILIEN Trim Failure Interrupt Enable Bit
This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]).
If this bit is high and TFAILIF(SYS_IRCTSTS[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
0 = Disable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU.
1 = Enable TFAILIF(SYS_IRCTSTS[1]) status to trigger an interrupt to CPU.
[2] CLKEIEN Clock Error Interrupt Enable Bit
This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.
If this bit is set to1, and CLKERRIF(SYS_IRCTSTS[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
0 = Disable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU.
1 = Enable CLKERRIF(SYS_IRCTSTS[2]) status to trigger an interrupt to CPU.

Definition at line 10336 of file M471M_R1_S.h.

◆ IRCTISTS

SYS_T::IRCTISTS

Offset: 0xF8 IRC Trim Interrupt Status Register

Bits Field Descriptions
[0] FREQLOCK HIRC Frequency Lock Status
This bit indicates the internal 22.1184 MHz high-speed oscillator frequency is locked.
This is a status bit and doesn't trigger any interrupt.
[1] TFAILIF Trim Failure Interrupt Status
This bit indicates that internal 22.1184 MHz high-speed oscillator trim value update limitation count reached and the internal 22.1184 MHz high-speed oscillator clock frequency still doesn't be locked.
Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_iRCTCTL[1:0]) will be cleared to 00 by hardware automatically.
If this bit is set and TFAILIEN(SYS_IRCTIEN[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
Write 1 to clear this to 0.
0 = Trim value update limitation count does not reach.
1 = Trim value update limitation count reached and internal 22.1184 MHz high-speed oscillator frequency still not locked.
[2] CLKERRIF Clock Error Interrupt Status
When the frequency of external 32.768 kHz low-speed crystal or internal 22.1184 MHz high-speed oscillator is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy
Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_IRCTCL[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_IRCTCTL[8]) is set to 1.
If this bit is set and CLKEIEN(SYS_IRCTIEN[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy.
Write 1 to clear this to 0.
0 = Clock frequency is accuracy.
1 = Clock frequency is inaccuracy.

Definition at line 10337 of file M471M_R1_S.h.

◆ IRDA

UART_T::IRDA

Offset: 0x28 UART IrDA Control Register

Bits Field Descriptions
[1] TXEN IrDA Receiver/Transmitter Selection Enable Bit
0 = IrDA Transmitter Disabled and Receiver Enabled. (Default)
1 = IrDA Transmitter Enabled and Receiver Disabled.
Note: In IrDA function mode (FUNCSEL(UART_FUNCSEL[1:0])=10), the first received data is unreliable and it should be skipped if IrDA receiver is enabled (TXEN(UART_IRDA[1])=0) at the first time.
[5] TXINV IrDA Inverse Transmitting Output Signal
0 = None inverse transmitting signal. (Default)
1 = Inverse transmitting output signal.
[6] RXINV IrDA Inverse Receive Input Signal
0 = None inverse receiving input signal.
1 = Inverse receiving input signal. (Default)

Definition at line 11893 of file M471M_R1_S.h.

◆ ISPADDR

FMC_T::ISPADDR

Offset: 0x04 ISP Address Register

Bits Field Descriptions
[31:0] ISPADDR ISP Address
The NuMicro M471M/R1/S is equipped with embedded flash.
ISPADDR[1:0] must be kept 00 for ISP 32-bit operation.
ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.
For Checksum Calculation command, this field is the flash starting address for checksum calculation, 2 Kbytes alignment is necessary for checksum calculation.

Definition at line 2336 of file M471M_R1_S.h.

◆ ISPCMD

FMC_T::ISPCMD

Offset: 0x0C ISP CMD Register

Bits Field Descriptions
[6:0] CMD ISP CMD
ISP command table is shown below:
0x00= FLASH Read.
0x04= Read Unique ID.
0x0B= Read Company ID.
0x0C= Read Device ID.
0x0D= Read Checksum.
0x21= FLASH 32-bit Program.
0x22= FLASH Page Erase.
0x27= FLASH Multi-Word Program.
0x2D= Run Checksum Calculation.
0x2E= Vector Remap.
0x61= FLASH 64-bit Program.
The other commands are invalid.

Definition at line 2338 of file M471M_R1_S.h.

◆ ISPCTL

FMC_T::ISPCTL

Offset: 0x00 ISP Control Register

Bits Field Descriptions
[0] ISPEN ISP Enable Bit (Write Protect)
ISP function enable bit. Set this bit to enable ISP function.
0 = ISP function Disabled.
1 = ISP function Enabled.
[1] BS Boot Select (Write Protect)
When MBS in CONFIG0 is 1, set/clear this bit to select next booting from LDROM/APROM, respectively.
This bit also functions as chip booting status flag, which can be used to check where chip booted from.
This bit is initiated with the inverted value of CBS[1] (CONFIG0[7]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
0 = Booting from APROM when MBS (CONFIG0[5]) is 1.
1 = Booting from LDROM when MBS (CONFIG0[5]) is 1.
[3] APUEN APROM Update Enable Bit (Write Protect)
0 = APROM cannot be updated when the chip runs in APROM.
1 = APROM can be updated when the chip runs in APROM.
[4] CFGUEN CONFIG Update Enable Bit (Write Protect)
0 = CONFIG cannot be updated.
1 = CONFIG can be updated.
[5] LDUEN LDROM Update Enable Bit (Write Protect)
LDROM update enable bit.
0 = LDROM cannot be updated.
1 = LDROM can be updated.
[6] ISPFF ISP Fail Flag (Write Protect)
This bit is set by hardware when a triggered ISP meets any of the following conditions:
This bit needs to be cleared by writing 1 to it.
(1) APROM writes to itself if APUEN is set to 0.
(2) LDROM writes to itself if LDUEN is set to 0.
(3) CONFIG is erased/programmed if CFGUEN is set to 0.
(4) SPROM is erased/programmed if SPUEN is set to 0
(5) SPROM is programmed at SPROM secured mode.
(6) Page Erase command at LOCK mode with ICE connection
(7) Erase or Program command at brown-out detected
(8) Destination address is illegal, such as over an available range.
(9) Invalid ISP commands
[16] BL Boot Loader Booting (Write Protect)
This bit is initiated with the inverted value of MBS (CONFIG0[5]).
Any reset, except CPU reset (CPU is 1) or system reset (SYS), BL will be reloaded.
This bit is used to check chip boot from Boot Loader or not.
User should keep original value of this bit when updating FMC_ISPCTL register.
0 = Booting from APROM or LDROM.
1 = Booting from Boot Loader.

Definition at line 2335 of file M471M_R1_S.h.

◆ ISPDAT

FMC_T::ISPDAT

Offset: 0x08 ISP Data Register

Bits Field Descriptions
[31:0] ISPDAT ISP Data
Write data to this register before ISP program operation.
Read data from this register after ISP read operation.
For Run Checksum Calculation command, ISPDAT is the memory size (byte) and 2 Kbytes alignment.
For ISP Read Checksum command, ISPDAT is the checksum result.
If ISPDAT = 0x0000_0000, it means that (1) the checksum calculation is in progress, (2) the memory range for checksum calculation is incorrect, or (3) all of data are 0.

Definition at line 2337 of file M471M_R1_S.h.

◆ ISPSTS

FMC_T::ISPSTS

Offset: 0x40 ISP Status Register

Bits Field Descriptions
[0] ISPBUSY ISP Busy Flag (Read Only)
Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
0 = ISP operation is finished.
1 = ISP is progressed.
[2:1] CBS Boot Selection Of CONFIG (Read Only)
This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened.
The following function is valid when MBS (FMC_ISPSTS[3])= 1.
00 = LDROM with IAP mode.
01 = LDROM without IAP mode.
10 = APROM with IAP mode.
11 = APROM without IAP mode.
[3] MBS Boot From Boot Loader Selection Flag (Read Only)
This bit is initiated with the MBS (CONFIG0[5]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened
0 = Booting from Boot Loader.
1 = Booting
from LDROM/APROM.(see CBS bit setting)
[5] PGFF Flash Program With Fast Verification Flag (Read Only)
This bit is set if data is mismatched at ISP programming verification.
This bit is clear by performing ISP flash erase or ISP read CID operation.
0 = Flash Program is success.
1 = Flash Program is fail. Program data is different with data in the flash memory
[6] ISPFF ISP Fail Flag (Write Protect)
This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6].
This bit is set by hardware when a triggered ISP meets any of the following conditions:
(1) APROM writes to itself if APUEN is set to 0.
(2) LDROM writes to itself if LDUEN is set to 0.
(3) CONFIG is erased/programmed if CFGUEN is set to 0.
(4) SPROM is erased/programmed if SPUEN is set to 0
(5) SPROM is programmed at SPROM secured mode.
(6) Page Erase command at LOCK mode with ICE connection
(7) Erase or Program command at brown-out detected
(8) Destination address is illegal, such as over an available range.
(9) Invalid ISP commands
[23:9] VECMAP Vector Page Mapping Address (Read Only)
All access to 0x0000_0000~0x0000_01FF is remapped to the flash memory address {VECMAP[14:0], 9'h000} ~ {VECMAP[14:0], 9'h1FF}

Definition at line 2343 of file M471M_R1_S.h.

◆ ISPTRG

FMC_T::ISPTRG

Offset: 0x10 ISP Trigger Control Register

Bits Field Descriptions
[0] ISPGO ISP Start Trigger (Write Protect)
Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
0 = ISP operation is finished.
1 = ISP is progressed.

Definition at line 2339 of file M471M_R1_S.h.

◆ IVSCTL

SYS_T::IVSCTL

Offset: 0x1C Internal Voltage Source Control Register

Bits Field Descriptions
[0] VTEMPEN Temperature Sensor Enable Bit
This bit is used to enable/disable temperature sensor function.
0 = Temperature sensor function Disabled (default).
1 = Temperature sensor function Enabled.
Note: After this bit is set to 1, the value of temperature sensor output can be obtained from ADC conversion result.
Please refer to ADC function chapter for details.
[1] VBATUGEN VBAT Unity Gain Buffer Enable Bit
This bit is used to enable/disable VBAT unity gain buffer function.
0 = VBAT unity gain buffer function Disabled (default).
1 = VBAT unity gain buffer function Enabled.
Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result

Definition at line 10315 of file M471M_R1_S.h.

◆ LEAPYEAR

RTC_T::LEAPYEAR

Offset: 0x24 RTC Leap Year Indicator Register

Bits Field Descriptions
[0] LEAPYEAR Leap Year Indication Register (Read Only)
0 = This year is not a leap year.
1 = This year is leap year.

Definition at line 7646 of file M471M_R1_S.h.

◆ LINE

UART_T::LINE

Offset: 0x0C UART Line Control Register

Bits Field Descriptions
[1:0] WLS Word Length Selection
This field sets UART word length.
00 = 5 bits.
01 = 6 bits.
10 = 7 bits.
11 = 8 bits.
[2] NSB Number Of "STOP Bit"
0 = One "STOP bit" is generated in the transmitted data.
1 = When select 5-bit word length, 1.5 "STOP bit" is generated in the transmitted data.
When select 6-, 7- and 8-bit word length, 2 "STOP bit" is generated in the transmitted data.
[3] PBE Parity Bit Enable Bit
0 = No parity bit generated Disabled.
1 = Parity bit generated Enabled.
Note : Parity bit is generated on each outgoing character and is checked on each incoming data.
[4] EPE Even Parity Enable Bit
0 = Odd number of logic 1's is transmitted and checked in each word.
1 = Even number of logic 1's is transmitted and checked in each word.
Note:This bit has effect only when PBE (UART_LINE[3]) is set.
[5] SPE Stick Parity Enable Bit
0 = Stick parity Disabled.
1 = Stick parity Enabled.
Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1, the parity bit is transmitted and checked as logic 0.
If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1.
[6] BCB Break Control Bit
0 = Break Control Disabled.
1 = Break Control Enabled.
Note: When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0).
This bit acts only on TX line and has no effect on the transmitter logic.

Definition at line 11886 of file M471M_R1_S.h.

◆ LOAD

PWM_T::LOAD

Offset: 0x28 PWM Load Register

Bits Field Descriptions
[5:0] LOADn Re-Load PWM Comparator Register (CMPDAT) Control Bit
This bit is software write, hardware clear when current PWM period end.
Each bit n controls the corresponding PWM channel n.
Write Operation:
0 = No effect.
1 = Set load window of window loading mode.
Read Operation:
0 = No load window is set.
1 = Load window is set.
Note: This bit only use in window loading mode, WINLDENn(PWM_CTL0[13:8]) = 1.

Definition at line 5825 of file M471M_R1_S.h.

◆ LXTCTL

RTC_T::LXTCTL

Offset: 0x100 RTC 32.768 kHz Oscillator Control Register

Bits Field Descriptions
[0] LXTEN Backup Domain 32K Oscillator Enable Bit
0 = Oscillator is Disabled.
1 = Oscillator is Enabled.
This bit controls 32 kHz oscillator on/off.
User can set either LXTEN in RTC domain or system manager control register CLK_PWRCTL[1] (LXTEN) to enable 32 kHz oscillator.
If this bit is set 1, X32 kHz oscillator keep running after system power is turned off, if this bit is clear to 0, oscillator is turned off when system power is turned off.
[3:1] GAIN Oscillator Gain Option
User can select oscillator gain according to crystal external loading and operating temperature range.
The larger gain value corresponding to stronger driving capability and higher power consumption.
000 = L0 mode.
001 = L1 mode.
010 = L2 mode.
011 = L3 mode.
100 = L4 mode.
101 = L5 mode.
110 = L6 mode.
111 = L7 mode (Default).

Definition at line 7655 of file M471M_R1_S.h.

◆ LXTICTL

RTC_T::LXTICTL

Offset: 0x108 X32KI Pin Control Register

Bits Field Descriptions
[1:0] OPMODE IO Operation Mode
00 = X32KI (PF.1) is input only mode, without pull-up resistor.
01 = X32KI (PF.1) is output push pull mode.
10 = X32KI (PF.1) is open drain mode.
11 = X32KI (PF.1) is input only mode with internal pull up.
[2] DOUT IO Output Data
0 = X32KI (PF.1) output low.
1 = X32KI (PF.1) output high.
[3] CTLSEL IO Pin State Backup Selection
When low speed 32 kHz oscillator is disabled, X32KI (PF.1) pin can be used as GPIO function.
User can program CTLSEL bit to decide X32KI (PF.1) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTICTL control register.
0 = X32KI (PF.1) pin I/O function is controlled by GPIO module.
It becomes floating state when system power is turned off.
1 = X32KI (PF.1) pin I/O function is controlled by VBAT power domain, X32KI (PF.1) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1.
I/O pin keeps the previous state after system power is turned off.

Definition at line 7657 of file M471M_R1_S.h.

◆ LXTOCTL

RTC_T::LXTOCTL

Offset: 0x104 X32KO Pin Control Register

Bits Field Descriptions
[1:0] OPMODE GPF0 Operation Mode
00 = X32KO (PF.0) is input only mode, without pull-up resistor.
01 = X32KO (PF.0) is output push pull mode.
10 = X32KO (PF.0) is open drain mode.
11 = X32KO (PF.0) is input only mode with internal pull up.
[2] DOUT IO Output Data
0 = X32KO (PF.0) output low.
1 = X32KO (PF.0) output high.
[3] CTLSEL IO Pin State Backup Selection
When low speed 32 kHz oscillator is disabled, X32KO (PF.0) pin can be used as GPIO function.
User can program CTLSEL bit to decide X32KO (PF.0) I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_LXTOCTL control register.
0 = X32KO (PF.0) pin I/O function is controlled by GPIO module.
It becomes floating when system power is turned off.
1 = X32KO (PF.0) pin I/O function is controlled by VBAT power domain, X32KO (PF.0) pin function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1.
I/O pin keeps the previous state after system power is turned off.

Definition at line 7656 of file M471M_R1_S.h.

◆ MODE

GPIO_T::MODE

Offset: 0x00/0x40/0x80/0xC0/0x100/0x140 Port A-F I/O Mode Control

Bits Field Descriptions
[2n+1:2n] MODEn Port A-F I/O Pin[n] Mode Control
Determine each I/O mode of Px.n pins.
00 = Px.n is in Input mode.
01 = Px.n is in Push-pull Output mode.
10 = Px.n is in Open-drain Output mode.
11 = Px.n is in Quasi-bidirectional mode.
Note1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).
If CIOINI is set to 0, the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional mode after chip powered on.
If CIOINI is set to 1, the default value is 0x0000_0000 and all pins will be
input mode after chip powered on.
Note2:
n=0~15 for port A/B/C/D.
n=0~14 for port E.
n=0~7 for port F.

Definition at line 2652 of file M471M_R1_S.h.

◆ MODEM

UART_T::MODEM

Offset: 0x10 UART Modem Control Register

Bits Field Descriptions
[1] RTS nRTS (Request-To-Send) Signal Control
This bit is direct control internal nRTS signal active or not, and then drive the nRTS pin output with RTSACTLV bit configuration.
0 = nRTS signal is active.
1 = nRTS signal is inactive.
Note1: This nRTS signal control bit is not effective when nRTS auto-flow control is enabled in UART function mode.
Note2: This nRTS signal control bit is not effective when RS-485 auto direction mode (AUD) is enabled in RS-485 function mode.
[9] RTSACTLV nRTS Pin Active Level
This bit defines the active level state of nRTS pin output.
0 =n RTS pin output is high level active.
1 = nRTS pin output is low level active. (Default)
Note1: Refer to Figure 6.21-10 and Figure 6.21-11 for UART function mode.
Note2: Refer to Figure 6.21-21 and Figure 6.21-22 for RS-485 function mode.
[13] RTSSTS nRTS Pin Status (Read Only)
This bit mirror from nRTS pin output of voltage logic status.
0 = nRTS pin output is low level voltage logic state.
1 = nRTS pin output is high level voltage logic state.

Definition at line 11887 of file M471M_R1_S.h.

◆ MODEMSTS

UART_T::MODEMSTS

Offset: 0x14 UART Modem Status Register

Bits Field Descriptions
[0] CTSDETF Detect nCTS State Change Flag (Read Only)
This bit is set whenever nCTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.
0 = nCTS input has not change state.
1 = nCTS input has change state.
Note: This bit is read only, but can be cleared by writing "1" to it.
[4] CTSSTS nCTS Pin Status (Read Only)
This bit mirror from nCTS pin input of voltage logic status.
0 = nCTS pin input is low level voltage logic state.
1 = nCTS pin input is high level voltage logic state.
Note: This bit echoes when UART Controller peripheral clock is enabled, and nCTS multi-function port is selected.
[8] CTSACTLV nCTS Pin Active Level
This bit defines the active level state of nCTS pin input.
0 = nCTS pin input is high level active.
1 = nCTS pin input is low level active. (Default)

Definition at line 11888 of file M471M_R1_S.h.

◆ MPADDR

FMC_T::MPADDR

Offset: 0xC4 ISP Multi-Program Address Register

Bits Field Descriptions
[31:0] MPADDR ISP Multi-Word Program Address
MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.
MPADDR will keep the final ISP address when ISP multi-word program is complete.

Definition at line 2351 of file M471M_R1_S.h.

◆ MPDAT0

FMC_T::MPDAT0

Offset: 0x80 ISP Data0 Register

Bits Field Descriptions
[31:0] ISPDAT0 ISP Data 0
This register is the first 32-bit data for 32-bit/64-bit/multi-word programming, and it is also the mirror of FMC_ISPDAT, both registers keep the same data

Definition at line 2345 of file M471M_R1_S.h.

◆ MPDAT1

FMC_T::MPDAT1

Offset: 0x84 ISP Data1 Register

Bits Field Descriptions
[31:0] ISPDAT1 ISP Data 1
This register is the second 32-bit data for 64-bit/multi-word programming.

Definition at line 2346 of file M471M_R1_S.h.

◆ MPDAT2

FMC_T::MPDAT2

Offset: 0x88 ISP Data2 Register

Bits Field Descriptions
[31:0] ISPDAT2 ISP Data 2
This register is the third 32-bit data for multi-word programming.

Definition at line 2347 of file M471M_R1_S.h.

◆ MPDAT3

FMC_T::MPDAT3

Offset: 0x8C ISP Data3 Register

Bits Field Descriptions
[31:0] ISPDAT3 ISP Data 3
This register is the fourth 32-bit data for multi-word programming.

Definition at line 2348 of file M471M_R1_S.h.

◆ MPSTS

FMC_T::MPSTS

Offset: 0xC0 ISP Multi-Program Status Register

Bits Field Descriptions
[0] MPBUSY ISP Multi-Word Program Busy Flag (Read Only)
Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.
This bit is the mirror of ISPGO(FMC_ISPTRG[0]).
0 = ISP Multi-Word program operation is finished.
1 = ISP Multi-Word program operation
is progressed.
[1] PPGO ISP Multi-Program Status (Read Only)
0 = ISP multi-word program operation is not active.
1 = ISP multi-word program operation is in progress.
[2] ISPFF ISP Fail Flag (Read Only)
This bit is the mirror of ISPFF (FMC_ISPCTL[6]), it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6].
This bit is set by hardware when a triggered ISP meets any of the following conditions:
(1) APROM writes to itself if APUEN is set to 0.
(2) LDROM writes to itself if LDUEN is set to 0.
(3) CONFIG is erased/programmed if CFGUEN is set to 0.
(4) SPROM is erased/programmed if SPUEN is set to 0
(5) SPROM is programmed at SPROM secured mode.
(6) Page Erase command at LOCK mode with ICE connection
(7) Erase or Program command at brown-out detected
(8) Destination address is illegal, such as over an available range.
(9) Invalid ISP commands
[4] D0 ISP DATA 0 Flag (Read Only)
This bit is set when FMC_MPDAT0 is written and auto-clear to 0 when the FMC_MPDAT0 data is programmed to flash complete.
0 = FMC_MPDAT0 register is empty, or program to flash complete.
1 = FMC_MPDAT0 register has been written, and not program to flash complete.
[5] D1 ISP DATA 1 Flag (Read Only)
This bit is set when FMC_MPDAT1 is written and auto-clear to 0 when the FMC_MPDAT1 data is programmed to flash complete.
0 = FMC_MPDAT1 register is empty, or program to flash complete.
1 = FMC_MPDAT1 register has been written, and not program to flash complete.
[6] D2 ISP DATA 2 Flag (Read Only)
This bit is set when FMC_MPDAT2 is written and auto-clear to 0 when the FMC_MPDAT2 data is programmed to flash complete.
0 = FMC_MPDAT2 register is empty, or program to flash complete.
1 = FMC_MPDAT2 register has been written, and not program to flash complete.
[7] D3 ISP DATA 3 Flag (Read Only)
This bit is set when FMC_MPDAT3 is written and auto-clear to 0 when the FMC_MPDAT3 data is programmed to flash complete.
0 = FMC_MPDAT3 register is empty, or program to flash complete.
1 = FMC_MPDAT3 register has been written, and not program to flash complete.

Definition at line 2350 of file M471M_R1_S.h.

◆ MSK

PWM_T::MSK

Offset: 0xBC PWM Mask Data Register

Bits Field Descriptions
[5:0] MSKDATn PWM Mask Data Bit
This data bit control the state of PWMn output pin, if corresponding mask function is enabled.
Each bit n controls the corresponding PWM channel n.
0 = Output logic low to PWMn.
1 = Output logic high to PWMn.

Definition at line 5844 of file M471M_R1_S.h.

◆ MSKEN

PWM_T::MSKEN

Offset: 0xB8 PWM Mask Enable Register

Bits Field Descriptions
[5:0] MSKENn PWM Mask Enable
Each bit n controls the corresponding PWM channel n.
The PWM output signal will be masked when this bit is enabled.
The corresponding PWM channel n will output MSKDATn (PWM_MSK[5:0]) data.
0 = PWM output signal is non-masked.
1 = PWM output signal is masked and output MSKDATn data.

Definition at line 5843 of file M471M_R1_S.h.

◆ MXPLD

USBD_EP_T::MXPLD

Offset: 0x504/0x514/0x524/0x534/0x544/0x554/0x564/0x574 Endpoint 0~7 Maximal Payload Register

Bits Field Descriptions
[8:0] MXPLD Maximal Payload
Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token).
It also used to indicate that the endpoint is ready to be transmitted in IN token or received in OUT token.
(1) When the register is written by CPU,
For IN token, the value of MXPLD is used to define the data length to be transmitted and indicate the data buffer is ready.
For OUT token, it means that the controller is ready to receive data from the host and the value of MXPLD is the maximal data length comes from host.
(2) When the register is read by CPU,
For IN token, the value of MXPLD is indicated by the data length be transmitted to host
For OUT token, the value of MXPLD is indicated the actual data length receiving from host.
Note: Once MXPLD is written, the data packets will be transmitted/received immediately after IN/OUT token arrived.

Definition at line 12272 of file M471M_R1_S.h.

◆ NEXT

DSCT_T::NEXT

Offset: 0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C/0x8C/0x9C/0xAC/0xBC First Scatter-Gather Descriptor Table Offset Address of PDMA Channel 0~11

Bits Field Descriptions
[15:2] NEXT PDMA Next Descriptor Table Offset Address Register
This field indicates the offset of next descriptor table address in system memory.
The system memory based address is 0x2000_0000 (PDMA_SCATBA), if the next descriptor table is 0x2000_0100, then this field must fill in 0x0100.
Note1: The next descriptor table address must be word boundary.
Note2: Before filled transfer task in the descriptor table, user must check if the descriptor table is complete.

Definition at line 3995 of file M471M_R1_S.h.

◆ NMIEN

SYS_INT_T::NMIEN

Offset: 0x00 NMI Source Interrupt Enable Register

Bits Field Descriptions
[0] BODOUT BOD NMI Source Enable (Write Protect)
0 = BOD NMI source Disabled.
1 = BOD NMI source Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[1] IRC_INT IRC TRIM NMI Source Enable (Write Protect)
0 = IRC TRIM NMI source Disabled.
1 = IRC TRIM NMI source Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[2] PWRWU_INT Power-Down Mode Wake-Up NMI Source Enable (Write Protect)
0 = Power-down mode wake-up NMI source Disabled.
1 = Power-down mode wake-up NMI source Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[4] CLKFAIL Clock Fail Detected NMI Source Enable (Write Protect)
0 = Clock fail detected interrupt NMI source Disabled.
1 = Clock fail detected interrupt NMI source Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[6] RTC_INT RTC NMI Source Enable (Write Protect)
0 = RTC NMI source Disabled.
1 = RTC NMI source Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[7] TAMPER_INT TAMPER_INT NMI Source Enable (Write Protect)
0 = Backup register tamper detected interrupt.NMI source Disabled.
1 = Backup register tamper detected interrupt.NMI source Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[8] EINT0 External Interrupt From PA.0, PD.2 Or PE.4 Pin NMI Source Enable (Write Protect)
0 = External interrupt from PA.0, PD.2 or PE.4 pin NMI source Disabled.
1 = External interrupt from PA.0, PD.2 or PE.4 pin NMI source Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[9] EINT1 External Interrupt From PB.0, PD.3 Or PE.5 Pin NMI Source Enable (Write Protect)
0 = External interrupt from PB.0, PD.3 or PE.5 pin NMI source Disabled.
1 = External interrupt from PB.0, PD.3 or PE.5 pin NMI source Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[10] EINT2 External Interrupt From PC.0 Pin NMI Source Enable (Write Protect)
0 = External interrupt from PC.0 pin NMI source Disabled.
1 = External interrupt from PC.0 pin NMI source Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[11] EINT3 External Interrupt From PD.0 Pin NMI Source Enable (Write Protect)
0 = External interrupt from PD.0 pin NMI source Disabled.
1 = External interrupt from PD.0 pin NMI source Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[12] EINT4 External Interrupt From PE.0 Pin NMI Source Enable (Write Protect)
0 = External interrupt from PE.0 pin NMI source Disabled.
1 = External interrupt from PE.0 pin NMI source Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[13] EINT5 External Interrupt From PF.0 Pin NMI Source Enable (Write Protect)
0 = External interrupt from PF.0 pin NMI source Disabled.
1 = External interrupt from PF.0 pin NMI source Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[14] UART0_INT UART0 NMI Source Enable (Write Protect)
0 = UART0 NMI source Disabled.
1 = UART0 NMI source Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[15] UART1_INT UART1 NMI Source Enable (Write Protect)
0 = UART1 NMI source Disabled.
1 = UART1 NMI source Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 10975 of file M471M_R1_S.h.

◆ NMISTS

SYS_INT_T::NMISTS

Offset: 0x04 NMI source interrupt Status Register

Bits Field Descriptions
[0] BODOUT BOD Interrupt Flag (Read Only)
0 = BOD interrupt is deasserted.
1 = BOD interrupt is asserted.
[1] IRC_INT IRC TRIM Interrupt Flag (Read Only)
0 = HIRC TRIM interrupt is deasserted.
1 = HIRC TRIM interrupt is asserted.
[2] PWRWU_INT Power-Down Mode Wake-Up Interrupt Flag (Read Only)
0 = Power-down mode wake-up interrupt is deasserted.
1 = Power-down mode wake-up interrupt is asserted.
[4] CLKFAIL Clock Fail Detected Interrupt Flag (Read Only)
0 = Clock fail detected interrupt is deasserted.
1 = Clock fail detected interrupt is asserted.
[6] RTC_INT RTC Interrupt Flag (Read Only)
0 = RTC interrupt is deasserted.
1 = RTC interrupt is asserted.
[7] TAMPER_INT TAMPER_INT Interrupt Flag (Read Only)
0 = Backup register tamper detected interrupt is deasserted.
1 = Backup register tamper detected interrupt is asserted.
[8] EINT0 External Interrupt From PA.0, PD.2 Or PE.4 Pin Interrupt Flag (Read Only)
0 = External Interrupt from PA.0, PD.2 or PE.4 interrupt is deasserted.
1 = External Interrupt from PA.0, PD.2 or PE.4 interrupt is asserted.
[9] EINT1 External Interrupt From PB.0, PD.3 Or PE.5 Pin Interrupt Flag (Read Only)
0 = External Interrupt from PB.0, PD.3 or PE.5 interrupt is deasserted.
1 = External Interrupt from PB.0, PD.3 or PE.5 interrupt is asserted.
[10] EINT2 External Interrupt From PC.0 Pin Interrupt Flag (Read Only)
0 = External Interrupt from PC.0 interrupt is deasserted.
1 = External Interrupt from PC.0 interrupt is asserted.
[11] EINT3 External Interrupt From PD.0 Pin Interrupt Flag (Read Only)
0 = External Interrupt from PD.0 interrupt is deasserted.
1 = External Interrupt from PD.0 interrupt is asserted.
[12] EINT4 External Interrupt From PE.0 Pin Interrupt Flag (Read Only)
0 = External Interrupt from PE.0 interrupt is deasserted.
1 = External Interrupt from PE.0 interrupt is asserted.
[13] EINT5 External Interrupt From PF.0 Pin Interrupt Flag (Read Only)
0 = External Interrupt from PF.0 interrupt is deasserted.
1 = External Interrupt from PF.0 interrupt is asserted.
[14] UART0_INT UART0 Interrupt Flag (Read Only)
0 = UART1 interrupt is deasserted.
1 = UART1 interrupt is asserted.
[15] UART1_INT UART1 Interrupt Flag (Read Only)
0 = UART1 interrupt is deasserted.
1 = UART1 interrupt is asserted.

Definition at line 10976 of file M471M_R1_S.h.

◆ OVSTS

EADC_T::OVSTS

Offset: 0x5C A/D Sample Module Start of Conversion Overrun Flag Register

Bits Field Descriptions
[18:0] SPOVF A/D SAMPLE0~18 Overrun Flag
0 = No sample module event overrun.
1 = Indicates a new sample module event is generated while an old one event is pending.
Note: This bit is cleared by writing 1 to it.

Definition at line 726 of file M471M_R1_S.h.

◆ PBUF

PWM_T::PBUF

Offset: 0x304~0x318 PWM PERIOD0~5 Buffer

Bits Field Descriptions
[15:0] PBUF PWM Period Register Buffer
(Read Only)
Used as PERIOD active register.

Definition at line 5893 of file M471M_R1_S.h.

◆ PDID

SYS_T::PDID

Offset: 0x00 Part Device Identification Number Register

Bits Field Descriptions
[31:0] PDID Part Device Identification Number (Read Only)
This register reflects device part number code.
Software can read this register to identify which device is used.

Definition at line 10308 of file M471M_R1_S.h.

◆ PDMACAP0_1

PWM_T::PDMACAP0_1

Offset: 0x240 PWM Capture Channel 01 PDMA Register

Bits Field Descriptions
[15:0] CAPBUF PWM Capture PDMA Register
(Read Only)
This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.

Definition at line 5886 of file M471M_R1_S.h.

◆ PDMACAP2_3

PWM_T::PDMACAP2_3

Offset: 0x244 PWM Capture Channel 23 PDMA Register

Bits Field Descriptions
[15:0] CAPBUF PWM Capture PDMA Register
(Read Only)
This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.

Definition at line 5887 of file M471M_R1_S.h.

◆ PDMACAP4_5

PWM_T::PDMACAP4_5

Offset: 0x248 PWM Capture Channel 45 PDMA Register

Bits Field Descriptions
[15:0] CAPBUF PWM Capture PDMA Register
(Read Only)
This register is use as a buffer to transfer PWM capture rising or falling data to memory by PDMA.

Definition at line 5888 of file M471M_R1_S.h.

◆ PDMACTL [1/2]

PWM_T::PDMACTL

Offset: 0x23C PWM PDMA Control Register

Bits Field Descriptions
[0] CHEN0_1 Channel 0/1 PDMA Enable
0 = Channel 0/1 PDMA function Disabled.
1 = Channel 0/1 PDMA function Enabled for the channel 0/1 captured data and transfer to memory.
[2:1] CAPMOD0_1 Select PWM_RCAPDAT0/1 Or PWM_FCAPDAT0/1 To Do PDMA Transfer
00 = Reserved.
01 = PWM_RCAPDAT0/1.
10 = PWM_FCAPDAT0/1.
11 = Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1.
[3] CAPORD0_1 Capture Channel 0/1 Rising/Falling Order
Set this bit to determine whether the PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 is the first captured data transferred to memory through PDMA when CAPMOD0_1 = 11.
0 = PWM_FCAPDAT0/1 is the first captured data to memory.
1 = PWM_RCAPDAT0/1 is the first captured data to memory.
[4] CHSEL0_1 Select Channel 0/1 To Do PDMA Transfer
0 = Channel0.
1 = Channel1.
[8] CHEN2_3 Channel 2/3 PDMA Enable
0 = Channel 2/3 PDMA function Disabled.
1 = Channel 2/3 PDMA function Enabled for the channel 2/3 captured data and transfer to memory.
[10:9] CAPMOD2_3 Select PWM_RCAPDAT2/3 Or PWM_FCAODAT2/3 To Do PDMA Transfer
00 = Reserved.
01 = PWM_RCAPDAT2/3.
10 = PWM_FCAPDAT2/3.
11 = Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3.
[11] CAPORD2_3 Capture Channel 2/3 Rising/Falling Order
Set this bit to determine whether the PWM_RCAPDAT2/3 or PWM_FCAPDAT2/3 is the first captured data transferred to memory through PDMA when CAPMOD2_3 = 11.
0 = PWM_FCAPDAT2/3 is the first captured data to memory.
1 = PWM_RCAPDAT2/3 is the first captured data to memory.
[12] CHSEL2_3 Select Channel 2/3 To Do PDMA Transfer
0 = Channel2.
1 = Channel3.
[16] CHEN4_5 Channel 4/5 PDMA Enable
0 = Channel 4/5 PDMA function Disabled.
1 = Channel 4/5 PDMA function Enabled for the channel 4/5 captured data and transfer to memory.
[18:17] CAPMOD4_5 Select PWM_RCAPDAT4/5 Or PWM_FCAPDAT4/5 To Do PDMA Transfer
00 = Reserved.
01 = PWM_RCAPDAT4/5.
10 = PWM_FCAPDAT4/5.
11 = Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5.
[19] CAPORD4_5 Capture Channel 4/5 Rising/Falling Order
Set this bit to determine whether the PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 is the first captured data transferred to memory through PDMA when CAPMOD4_5 = 11.
0 = PWM_FCAPDAT4/5 is the first captured data to memory.
1 = PWM_RCAPDAT4/5 is the first captured data to memory.
[20] CHSEL4_5 Select Channel 4/5 To Do PDMA Transfer
0 = Channel4.
1 = Channel5.

Definition at line 5885 of file M471M_R1_S.h.

◆ PDMACTL [2/2]

SPI_T::PDMACTL

Offset: 0x0C SPI PDMA Control Register

Bits Field Descriptions
[0] TXPDMAEN Transmit PDMA Enable Bit
0 = Transmit PDMA function Disabled.
1 = Transmit PDMA function Enabled.
Note: In SPI master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function.
User can enable TX PDMA function firstly or enable both functions simultaneously.
[1] RXPDMAEN Receive PDMA Enable Bit
0 = Receiver PDMA function Disabled.
1 = Receiver PDMA function Enabled.
[2] PDMARST PDMA Reset
0 = No effect.
1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0.

Definition at line 9308 of file M471M_R1_S.h.

◆ PENDSTS

EADC_T::PENDSTS

Offset: 0x58 A/D Start of Conversion Pending Flag Register

Bits Field Descriptions
[18:0] STPF A/D Sample Module 0~18 Start Of Conversion Pending Flag
Read:
0 = There is no pending conversion for sample module.
1 = Sample module ADC start of conversion is pending.
Write:
1 = clear pending flag and cancel the conversion for sample module.
Note: This bit remains 1 during pending state, when the respective ADC conversion is end, the STPFn (n=0~18) bit is automatically cleared to 0

Definition at line 725 of file M471M_R1_S.h.

◆ PERIOD

PWM_T::PERIOD

Offset: 0x30~0x44 PWM Period Register 0~5

Bits Field Descriptions
[15:0] PERIOD PWM Period Register
Up-Count mode: In this mode, PWM counter counts from 0 to PERIOD, and restarts from 0.
Down-Count mode: In this mode, PWM counter counts from PERIOD to 0, and restarts from PERIOD.
PWM period time = (PERIOD+1) * PWM_CLK period.
Up-Down-Count mode: In this mode, PWM counter counts from 0 to PERIOD, then decrements to 0 and repeats again.
PWM period time = 2 * PERIOD * PWM_CLK period.

Definition at line 5827 of file M471M_R1_S.h.

◆ PHS0_1

PWM_T::PHS0_1

Offset: 0x80 PWM Counter Phase Register 0

Bits Field Descriptions
[15:0] PHS PWM Synchronous Start Phase Bits
PHS determines the PWM synchronous start phase value. These bits only use in synchronous function.

Definition at line 5835 of file M471M_R1_S.h.

◆ PHS2_3

PWM_T::PHS2_3

Offset: 0x84 PWM Counter Phase Register 2

Bits Field Descriptions
[15:0] PHS PWM Synchronous Start Phase Bits
PHS determines the PWM synchronous start phase value. These bits only use in synchronous function.

Definition at line 5836 of file M471M_R1_S.h.

◆ PHS4_5

PWM_T::PHS4_5

Offset: 0x88 PWM Counter Phase Register 4

Bits Field Descriptions
[15:0] PHS PWM Synchronous Start Phase Bits
PHS determines the PWM synchronous start phase value. These bits only use in synchronous function.

Definition at line 5837 of file M471M_R1_S.h.

◆ PIN

GPIO_T::PIN

Offset: 0x10/0x50/0x90/0xD0/0x110/0x150 Port A-F Pin Value

Bits Field Descriptions
[n] PINn Port A-F Pin[n] Pin Value
Each bit of the register reflects the actual status of the respective Px.n pin.
If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
Note:
n=0~15 for port A/B/C/D.
n=0~14 for port E.
n=0~7 for port F.

Definition at line 2656 of file M471M_R1_S.h.

◆ PINCTL

SC_T::PINCTL

Offset: 0x24 SC Pin Control State Register.

Bits Field Descriptions
[0] PWREN SC_PWREN Pin Signal
Software can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11])to decide SC_PWR pin is in high or low level.
Write this field to drive SC_PWR pin
Refer PWRINV (SC_PINCTL[11]) description for programming SC_PWR pin voltage level.
Read this field to get SC_PWR pin status.
0 = SC_PWR pin status is low.
1 = SC_PWR pin status is high.
Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
So don't fill this field when operating in these modes.
[1] SCRST SC_RST Pin Signal
This bit is the pin status of SC_RST but user can drive SC_RST pin to high or low by setting this bit.
Write this field to drive SC_RST pin.
0 = Drive SC_RST pin to low.
1 = Drive SC_RST pin to high.
Read this field to get SC_RST pin status.
0 = SC_RST pin status is low.
1 = SC_RST pin status is high.
Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
So don't fill this field when operating in these modes.
[5] CSTOPLV SC Clock Stop Level
This field indicates the clock polarity control in clock stop mode.
0 = SC_CLK stopped in low level.
1 = SC_CLK stopped in high level.
[6] CLKKEEP SC Clock Enable Bit
0 = SC clock generation Disabled.
1 = SC clock always keeps free running.
Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically.
So don't fill this field when operating in these modes.
[9] SCDOUT SC Data Output Pin
This bit is the pin status of SCDATOUT but user can drive SCDATOUT pin to high or low by setting this bit.
0 = Drive SCDATOUT pin to low.
1 = Drive SCDATOUT pin to high.
Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically.
So don't fill this field when SC is in these modes.
[11] PWRINV SC_POW Pin Inverse
This bit is used for inverse the SC_POW pin.
There are four kinds of combination for SC_POW pin setting by PWRINV(SC_PINCTL[11]) and PWREN(SC_PINCTL[0]).
PWRINV (SC_PINCTL[11]) is bit 1 and PWREN(SC_PINCTL[0]) is bit 0 for SC_POW_Pin as high or low voltage selection.
00 = SC_POW_ Pin is 0.
01 = SC_POW _Pin is 1.
10 = SC_POW _Pin is 1.
11 = SC_POW_ Pin is 0.
Note: Software must select PWRINV (SC_PINCTL[11]) before Smart Card is enabled by SCEN (SC_CTL[0]).
[12] SCDOSTS SC Data Pin Output Status
This bit is the pin status of SCDATOUT
0 = SCDATOUT pin to low.
1 = SCDATOUT pin to high.
Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
This bit is not allowed to program when SC is operated at these modes.
[16] DATSTS This bit is the pin status of SC_DAT
0 = The SC_DAT pin is low.
1 = The SC_DAT pin is high.
[17] PWRSTS SC_PWR Pin Signal
This bit is the pin status of SC_PWR
0 = SC_PWR pin to low.
1 = SC_PWR pin to high.
Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
This bit is not allowed to program when SC is operated at these modes.
[18] RSTSTS SCRST Pin Signals
This bit is the pin status of SC_RST
0 = SC_RST pin is low.
1 = SC_RST pin is high.
Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
This bit is not allowed to program when SC is operated at these modes.
[30] SYNC SYNC Flag Indicator
Due to synchronization, software should check this bit when writing a new value to SC_PINCTL register.
0 = Synchronizing is completion, user can write new data to SC_PINCTL register.
1 = Last value is synchronizing.
Note: This bit is read only.
[31] LOOPBK Loop Back Test
0 = loop back test Disabled.
1 = Enabling loop back test and the internal SCDATOUT will connect to internal SC_DATA_I.

Definition at line 8501 of file M471M_R1_S.h.

◆ PKTCRC

I2C_T::PKTCRC

Offset: 0x54 I2C Packet Error Checking Byte Value Register

Bits Field Descriptions
[7:0] PECCRC Packet Error Checking Byte Value
This byte indicates the packet error checking content after transmission or receive byte count by using the C(x) = X8 + X2 + X + 1.
I t is read only.

Definition at line 3721 of file M471M_R1_S.h.

◆ PKTSIZE

I2C_T::PKTSIZE

Offset: 0x50 I2C Packet Error Checking Byte Number Register

Bits Field Descriptions
[7:0] PLDSIZE Transfer Byte Number
The transmission or receive byte number in one transaction when the PECEN is set.
The maximum transaction or receive byte is 255 Bytes.

Definition at line 3720 of file M471M_R1_S.h.

◆ PLLCTL

CLK_T::PLLCTL

Offset: 0x40 PLL Control Register

Bits Field Descriptions
[8:0] FBDIV PLL Feedback Divider Control Pins (Write Protect)
Refer to the formulas below the table.
[13:9] INDIV PLL Input Divider Control Pins (Write Protect)
Refer to the formulas below the table.
[15:14] OUTDIV PLL Output Divider Control Pins (Write Protect)
Refer to the formulas below the table.
[16] PD Power-Down Mode (Write Protect)
If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.
0 = PLL is in normal mode.
1 = PLL is in Power-down mode (default).
[17] BP PLL Bypass Control (Write Protect)
0 = PLL is in normal mode (default).
1 = PLL clock output is same as PLL input clock FIN.
[18] OE PLL OE (FOUT Enable) Pin Control (Write Protect)
0 = PLL FOUT Enabled.
1 = PLL FOUT is fixed low.
[19] PLLSRC PLL Source Clock Selection (Write Protect)
0 = PLL source clock from external 4~24 MHz high-speed crystal (HXT).
1 = PLL source clock from internal 22.1184 MHz high-speed oscillator (HIRC).
[23] STBSEL PLL Stable Counter Selection (Write Protect)
0 = PLL stable time is 6144 PLL source clock (suitable for source clock is equal to or less than 12MHz).
1 = PLL stable time is 12288 PLL source clock (suitable for source clock is larger than 12MHz).

Definition at line 1424 of file M471M_R1_S.h.

◆ POEN

PWM_T::POEN

Offset: 0xD8 PWM Output Enable Register

Bits Field Descriptions
[5:0] POENn PWM Pin Output Enable
Each bit n controls the corresponding PWM channel n.
0 = PWM pin at tri-state.
1 = PWM pin in output mode.

Definition at line 5851 of file M471M_R1_S.h.

◆ POLCTL

PWM_T::POLCTL

Offset: 0xD4 PWM Pin Polar Inverse Register

Bits Field Descriptions
[5:0] PINVn PWM PIN Polar Inverse Control
The register controls polarity state of PWM output.
Each bit n controls the corresponding PWM channel n.
0 = PWM output polar inverse Disabled.
1 = PWM output polar inverse Enabled.

Definition at line 5850 of file M471M_R1_S.h.

◆ PORCTL

SYS_T::PORCTL

Offset: 0x24 Power-On-Reset Controller Register

Bits Field Descriptions
[15:0] POROFF Power-On-Reset Enable Bit (Write Protect)
When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again.
User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function
Note: This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 10317 of file M471M_R1_S.h.

◆ PRICLR

PDMA_T::PRICLR

Offset: 0x414 PDMA Fixed Priority Clear Register

Bits Field Descriptions
[11:0] FPRICLRn PDMA Fixed Priority Clear Register (Write Only)
Set this bit to 1 to clear fixed priority level.
0 = No effect.
1 = Clear PDMA channel [n] fixed priority setting.
Note: User can read PDMA_PRISET register to know the channel priority.

Definition at line 4330 of file M471M_R1_S.h.

◆ PRISET

PDMA_T::PRISET

Offset: 0x410 PDMA Fixed Priority Setting Register

Bits Field Descriptions
[11:0] FPRISETn PDMA Fixed Priority Setting Register
Set this bit to 1 to enable fixed priority level.
Write Operation:
0 = No effect.
1 = Set PDMA channel [n] to fixed priority channel.
Read Operation:
0 = Corresponding PDMA channel is round-robin priority.
1 = Corresponding PDMA channel is fixed priority.
Note: This field only set to fixed priority, clear fixed priority use PDMA_PRICLR register.

Definition at line 4329 of file M471M_R1_S.h.

◆ PWRCTL

CLK_T::PWRCTL

Offset: 0x00 System Power-down Control Register

Bits Field Descriptions
[0] HXTEN External 4~24 MHz High-Speed Crystal Enable Bit (Write Protect)
The bit default value is set by flash controller user configuration register CONFIG0 [26:24].
When the default clock source is from external 4~24 MHz high-speed crystal, this bit is set to 1 automatically.
0 = External 4 ~ 24 MHz high speed crystal oscillator (HXT) Disabled.
1 = External 4 MH~ 24 z high speed crystal oscillator (HXT) Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[1] LXTEN External 32.768 KHz Low-Speed Crystal Enable Bit (Write Protect)
0 = External 32.768 kHz low-speed crystal oscillator (LXT) Disabled.
1 = External 32.768 kHz low-speed crystal oscillator (LXT) Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[2] HIRCEN Internal 22.1184 MHz High-Speed Oscillator Enable Bit (Write Protect)
0 = Internal 22.1184 MHz high-speed RC oscillator (HIRC) Disabled.
1 = Internal 22.1184 MHz high-speed RC oscillator (HIRC) Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[3] LIRCEN Internal 10 KHz Low-Speed Oscillator Enable Bit (Write Protect)
0 = Internal 10 kHz low speed RC oscillator (LIRC) Disabled.
1 = Internal 10 kHz low speed RC oscillator (LIRC) Enabled.
[4] PDWKDLY Enable The Wake-Up Delay Counter (Write Protect)
When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
The delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high-speed crystal, and 256 clock cycles when chip work at internal 22.1184 MHz high-speed oscillator.
0 = Clock cycles delay Disabled.
1 = Clock cycles delay Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[5] PDWKIEN Power-Down Mode Wake-Up Interrupt Enable Bit (Write Protect)
0 = Power-down Mode Wake-up Interrupt Disabled.
1 = Power-down Mode Wake-up Interrupt Enabled.
Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high.
Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
[6] PDWKIF Power-Down Mode Wake-Up Interrupt Status
Set by "Power-down wake-up event", it indicates that resume from Power-down mode
The flag is set if the EINT0~5, GPIO, USBH, USBD, UART0~3, WDT, BOD, RTC, TMR0~3, I2C0~1 or wake-up occurred.
Note1: Write 1 to clear the bit to 0.
Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
[7] PDEN System Power-Down Enable (Write Protect)
When this bit is set to 1, Power-down mode is enabled and chip Power-down behavior will depend on the PDWTCPU bit.
(a) If the PDWTCPU is 0, then the chip enters Power-down mode immediately after the PDEN bit set.(default)
(b) if the PDWTCPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.
When chip wakes up from Power-down mode, this bit is auto cleared.
Users need to set this bit again for next Power-down.
In Power-down mode, external 4~24 MHz high-speed crystal and the internal 22.1184 MHz high-speed oscillator will be disabled in this mode, but the external 32.768 kHz low-speed crystal and internal 10 kHz low-speed oscillator are not controlled by Power-down mode.
In Power-down mode, the PLL and system clock are disabled, and ignored the clock source selection.
The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from external 32.768 kHz low-speed crystal or the internal 10 kHz low-speed oscillator.
0 = Chip operating normally or chip in idle mode because of WFI command.
1 = Chip enters Power-down mode instant or wait CPU sleep command WFI.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[8] PDWTCPU This Bit Control The Power-Down Entry Condition (Write Protect)
0 = Chip enters Power-down mode when the PDEN bit is set to 1.
1 = Chip enters Power-down mode when the both PDWTCPU and PDEN bits are set to 1 and CPU run WFI instruction.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[11:10] HXTGAIN 4~24 MHz High-Speed Crystal Gain Control Bit
(Write Protect)
This is a protected register. Please refer to open lock sequence to program it.
Gain control is used to enlarge the gain of crystal to make sure crystal work normally.
If gain control is enabled, crystal will consume more power than gain control off.
00 = HXT frequency is lower than from 8 MHz.
01 = HXT frequency is from 8 MHz to 12 MHz.
10 = HXT frequency is from 12 MHz to 16 MHz.
11 = HXT frequency is higher than 16 MHz.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[12] HXTSELTYP 4~24 MHz High-Speed Crystal Type Select Bit (Write Protect)
This is a protected register. Please refer to open lock sequence to program it.
0 = Select INV type.
1 = Select GM type.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[24] HIRC48MEN Internal 48 MHz High-Speed Oscillator Enable Bit (Write Protect)
0 = Internal 48 MHz high-speed RC oscillator (HIRC) Disabled.
1 = Internal 48 MHz high-speed RC oscillator (HIRC) Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 1413 of file M471M_R1_S.h.

◆ RCAPDAT0

PWM_T::RCAPDAT0

Offset: 0x20C PWM Rising Capture Data Register 0

Bits Field Descriptions
[15:0] RCAPDAT PWM Rising Capture Data Register (Read Only)
When rising capture condition happened, the PWM counter value will be saved in this register.

Definition at line 5873 of file M471M_R1_S.h.

◆ RCAPDAT1

PWM_T::RCAPDAT1

Offset: 0x214 PWM Rising Capture Data Register 1

Bits Field Descriptions
[15:0] RCAPDAT PWM Rising Capture Data Register (Read Only)
When rising capture condition happened, the PWM counter value will be saved in this register.

Definition at line 5875 of file M471M_R1_S.h.

◆ RCAPDAT2

PWM_T::RCAPDAT2

Offset: 0x21C PWM Rising Capture Data Register 2

Bits Field Descriptions
[15:0] RCAPDAT PWM Rising Capture Data Register (Read Only)
When rising capture condition happened, the PWM counter value will be saved in this register.

Definition at line 5877 of file M471M_R1_S.h.

◆ RCAPDAT3

PWM_T::RCAPDAT3

Offset: 0x224 PWM Rising Capture Data Register 3

Bits Field Descriptions
[15:0] RCAPDAT PWM Rising Capture Data Register (Read Only)
When rising capture condition happened, the PWM counter value will be saved in this register.

Definition at line 5879 of file M471M_R1_S.h.

◆ RCAPDAT4

PWM_T::RCAPDAT4

Offset: 0x22C PWM Rising Capture Data Register 4

Bits Field Descriptions
[15:0] RCAPDAT PWM Rising Capture Data Register (Read Only)
When rising capture condition happened, the PWM counter value will be saved in this register.

Definition at line 5881 of file M471M_R1_S.h.

◆ RCAPDAT5

PWM_T::RCAPDAT5

Offset: 0x234 PWM Rising Capture Data Register 5

Bits Field Descriptions
[15:0] RCAPDAT PWM Rising Capture Data Register (Read Only)
When rising capture condition happened, the PWM counter value will be saved in this register.

Definition at line 5883 of file M471M_R1_S.h.

◆ REGLCTL

SYS_T::REGLCTL

Offset: 0x100 Register Lock Control Register

Bits Field Descriptions
[7:0] REGLCTL Register Lock Control Code
Write operation:
Some registers have write-protection function.
Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field.
After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
Read operation:
0 = Write-protection Enabled for writing protected registers.
Any write to the protected register is ignored.
1 = Write-protection Disabled for writing protected registers.
The Protected registers are:
SYS_IPRST0: address 0x4000_0008
SYS_BODCTL: address 0x4000_0018
SYS_PORCTL: address 0x4000_0024
SYS_VREFCTL: address 0x4000_0028
SYS_USBPHY: address 0x4000_002C
CLK_PWRCTL: address 0x4000_0200 (bit[6] is not protected for power wake-up interrupt clear)
SYS_SRAM_BISTCTL: address 0x4000_00D0
CLK_APBCLK0 [0]: address 0x4000_0208 (bit[0] is watchdog clock enable)
CLK_CLKSEL0: address 0x4000_0210 (for HCLK and CPU STCLK clock source select)
CLK_CLKSEL1 [1:0]: address 0x4000_0214 (for watchdog clock source select)
CLK_CLKSEL1 [31:30]: address 0x4000_0214 (for window watchdog clock source select)
CLK_CLKDSTS: address 0x4000_0274
NMIEN: address 0x4000_0300
FMC_ISPCTL: address 0x4000_C000 (Flash ISP Control register)
FMC_ISPTRG: address 0x4000_C010 (ISP Trigger Control register)
FMC_ISPSTS: address 0x4000_C040
WDT_CTL: address 0x4004_0000
FMC_FTCTL: address 0x4000_5018
FMC_ICPCMD: address 0x4000_501C
CLK_PLLCTL: address 0x40000240
PWM_CTL0: address 0x4005_8000
PWM_CTL0: address 0x4005_9000
PWM_DTCTL0_1: address 0x4005_8070
PWM_DTCTL0_1: address 0x4005_9070
PWM_DTCTL2_3: address 0x4005_8074
PWM_DTCTL2_3: address 0x4005_9074
PWM_DTCTL4_5: address 0x4005_8078
PWM_DTCTL4_5: address 0x4005_9078
PWM_BRKCTL0_1: address 0x4005_80C8
PWM_BRKCTL0_1: address 0x4005_90C8
PWM_BRKCTL2_3: address0x4005_80CC
PWM_BRKCTL2_3: address0x4005_90CC
PWM_BRKCTL4_5: address0x4005_80D0
PWM_BRKCTL4_5: address0x4005_90D0
PWM_INTEN1: address0x4005_80E4
PWM_INTEN1: address0x4005_90E4
PWM_INTSTS1: address0x4005_80EC
PWM_INTSTS1: address0x4005_90EC

Definition at line 10339 of file M471M_R1_S.h.

◆ REQSEL0_3

PDMA_T::REQSEL0_3

Offset: 0x480 PDMA Request Source Select Register 0

Bits Field Descriptions
[4:0] REQSRC0 Channel 0 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 0.
User can configure the peripheral by setting REQSRC0.
1 = Channel connects to SPI0_TX.
2 = Channel connects to SPI1_TX.
4 = Channel connects to UART0_TX.
5 = Channel connects to UART1_TX.
6 = Channel connects to UART2_TX.
7 = Channel connects to UART3_TX.
9 = Channel connects to ADC_RX.
11 = Channel connects to PWM0_P1_RX.
12 = Channel connects to PWM0_P2_RX.
13 = Channel connects to PWM0_P3_RX.
14 = Channel connects to PWM1_P1_RX.
15 = Channel connects to PWM1_P2_RX.
16 = Channel connects to PWM1_P3_RX.
17 = Channel connects to SPI0_RX.
18 = Channel connects to SPI1_RX.
20 = Channel connects to UART0_RX.
21 = Channel connects to UART1_RX.
22 = Channel connects to UART2_RX.
23 = Channel connects to UART3_RX.
31 = Disable PDMA.
Others = Reserved.
Note 1: A peripheral can't assign to two channels at the same time.
Note 2: This field is useless when transfer between memory and memory.
[12:8] REQSRC1 Channel 1 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 1.
User can configure the peripheral setting by REQSRC1.
Note: The channel configuration is the same as REQSRC0 field.
Please refer to the explanation of REQSRC0.
[20:16] REQSRC2 Channel 2 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 2.
User can configure the peripheral setting by REQSRC2.
Note: The channel configuration is the same as REQSRC0 field.
Please refer to the explanation of REQSRC0.
[28:24] REQSRC3 Channel 3 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 3.
User can configure the peripheral setting by REQSRC3.
Note: The channel configuration is the same as REQSRC0 field.
Please refer to the explanation of REQSRC0.

Definition at line 4346 of file M471M_R1_S.h.

◆ REQSEL4_7

PDMA_T::REQSEL4_7

Offset: 0x484 PDMA Request Source Select Register 1

Bits Field Descriptions
[4:0] REQSRC4 Channel 4 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 4.
User can configure the peripheral setting by REQSRC4.
Note: The channel configuration is the same as REQSRC0 field.
Please refer to the explanation of REQSRC0.
[12:8] REQSRC5 Channel 5 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 5.
User can configure the peripheral setting by REQSRC5.
Note: The channel configuration is the same as REQSRC0 field.
Please refer to the explanation of REQSRC0.
[20:16] REQSRC6 Channel 6 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 6.
User can configure the peripheral setting by REQSRC6.
Note: The channel configuration is the same as REQSRC0 field.
Please refer to the explanation of REQSRC0.
[28:24] REQSRC7 Channel 7 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 7.
User can configure the peripheral setting by REQSRC7.
Note: The channel configuration is the same as REQSRC0 field.
Please refer to the explanation of REQSRC0.

Definition at line 4347 of file M471M_R1_S.h.

◆ REQSEL8_11

PDMA_T::REQSEL8_11

Offset: 0x488 PDMA Request Source Select Register 2

Bits Field Descriptions
[4:0] REQSRC8 Channel 8 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 8.
User can configure the peripheral setting by REQSRC8.
Note: The channel configuration is the same as REQSRC0 field.
Please refer to the explanation of REQSRC0.
[12:8] REQSRC9 Channel 9 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 9.
User can configure the peripheral setting by REQSRC9.
Note: The channel configuration is the same as REQSRC0 field.
Please refer to the explanation of REQSRC0.
[20:16] REQSRC10 Channel 10 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 10.
User can configure the peripheral setting by REQSRC10.
Note: The channel configuration is the same as REQSRC0 field.
Please refer to the explanation of REQSRC0.
[28:24] REQSRC11 Channel 11 Request Source Selection
This filed defines which peripheral is connected to PDMA channel 11.
User can configure the peripheral setting by REQSRC11.
Note: The channel configuration is the same as REQSRC0 field.
Please refer to the explanation of REQSRC0.

Definition at line 4348 of file M471M_R1_S.h.

◆ RESERVE0 [1/12]

__I uint32_t USBH_T::RESERVE0[105]

Definition at line 13234 of file M471M_R1_S.h.

◆ RESERVE0 [2/12]

__I uint32_t PDMA_T::RESERVE0[196]

Definition at line 4324 of file M471M_R1_S.h.

◆ RESERVE0 [3/12]

__I uint32_t PWM_T::RESERVE0[1]

Definition at line 5826 of file M471M_R1_S.h.

◆ RESERVE0 [4/12]

__I uint32_t SYS_T::RESERVE0[1]

Definition at line 10313 of file M471M_R1_S.h.

◆ RESERVE0 [5/12]

__I uint32_t RTC_T::RESERVE0[28]

Definition at line 7654 of file M471M_R1_S.h.

◆ RESERVE0 [6/12]

__I uint32_t USBD_T::RESERVE0[29]

Definition at line 12516 of file M471M_R1_S.h.

◆ RESERVE0 [7/12]

__I uint32_t EBI_T::RESERVE0[2]

Definition at line 1998 of file M471M_R1_S.h.

◆ RESERVE0 [8/12]

__I uint32_t I2C_T::RESERVE0[2]

Definition at line 3714 of file M471M_R1_S.h.

◆ RESERVE0 [9/12]

__I uint32_t SPI_T::RESERVE0[2]

Definition at line 9311 of file M471M_R1_S.h.

◆ RESERVE0 [10/12]

__I uint32_t CLK_T::RESERVE0[6]

Definition at line 1423 of file M471M_R1_S.h.

◆ RESERVE0 [11/12]

__I uint32_t EADC_T::RESERVE0[8]

Definition at line 727 of file M471M_R1_S.h.

◆ RESERVE0 [12/12]

__I uint32_t FMC_T::RESERVE0[9]

Definition at line 2342 of file M471M_R1_S.h.

◆ RESERVE1 [1/8]

__I uint32_t FMC_T::RESERVE1[15]

Definition at line 2344 of file M471M_R1_S.h.

◆ RESERVE1 [2/8]

__I uint32_t EADC_T::RESERVE1[1]

Definition at line 729 of file M471M_R1_S.h.

◆ RESERVE1 [3/8]

__I uint32_t PDMA_T::RESERVE1[1]

Definition at line 4337 of file M471M_R1_S.h.

◆ RESERVE1 [4/8]

__I uint32_t SYS_T::RESERVE1[1]

Definition at line 10316 of file M471M_R1_S.h.

◆ RESERVE1 [5/8]

__I uint32_t USBD_T::RESERVE1[283]

Definition at line 12518 of file M471M_R1_S.h.

◆ RESERVE1 [6/8]

__I uint32_t PWM_T::RESERVE1[2]

Definition at line 5828 of file M471M_R1_S.h.

◆ RESERVE1 [7/8]

__I uint32_t CLK_T::RESERVE1[3]

Definition at line 1425 of file M471M_R1_S.h.

◆ RESERVE1 [8/8]

__I uint32_t SPI_T::RESERVE1[3]

Definition at line 9313 of file M471M_R1_S.h.

◆ RESERVE10

__I uint32_t PWM_T::RESERVE10[1]

Definition at line 5889 of file M471M_R1_S.h.

◆ RESERVE11

__I uint32_t PWM_T::RESERVE11[43]

Definition at line 5892 of file M471M_R1_S.h.

◆ RESERVE12

__I uint32_t PWM_T::RESERVE12[3]

Definition at line 5895 of file M471M_R1_S.h.

◆ RESERVE2 [1/6]

__I uint32_t SPI_T::RESERVE2[11]

Definition at line 9315 of file M471M_R1_S.h.

◆ RESERVE2 [2/6]

__I uint32_t FMC_T::RESERVE2[12]

Definition at line 2349 of file M471M_R1_S.h.

◆ RESERVE2 [3/6]

__I uint32_t PDMA_T::RESERVE2[12]

Definition at line 4345 of file M471M_R1_S.h.

◆ RESERVE2 [4/6]

__I uint32_t SYS_T::RESERVE2[29]

Definition at line 10331 of file M471M_R1_S.h.

◆ RESERVE2 [5/6]

__I uint32_t PWM_T::RESERVE2[2]

Definition at line 5830 of file M471M_R1_S.h.

◆ RESERVE2 [6/6]

__I uint32_t CLK_T::RESERVE2[3]

Definition at line 1427 of file M471M_R1_S.h.

◆ RESERVE3 [1/3]

__I uint32_t PWM_T::RESERVE3[1]

Definition at line 5834 of file M471M_R1_S.h.

◆ RESERVE3 [2/3]

__I uint32_t CLK_T::RESERVE3[3]

Definition at line 1429 of file M471M_R1_S.h.

◆ RESERVE3 [3/3]

__I uint32_t SYS_T::RESERVE3[6]

Definition at line 10334 of file M471M_R1_S.h.

◆ RESERVE4 [1/2]

__I uint32_t PWM_T::RESERVE4[1]

Definition at line 5838 of file M471M_R1_S.h.

◆ RESERVE4 [2/2]

__I uint32_t SYS_T::RESERVE4[1]

Definition at line 10338 of file M471M_R1_S.h.

◆ RESERVE5 [1/2]

__I uint32_t SYS_T::RESERVE5[11]

Definition at line 10340 of file M471M_R1_S.h.

◆ RESERVE5 [2/2]

__I uint32_t PWM_T::RESERVE5[2]

Definition at line 5840 of file M471M_R1_S.h.

◆ RESERVE6

__IO uint32_t PWM_T::RESERVE6[1]

Definition at line 5858 of file M471M_R1_S.h.

◆ RESERVE7

__I uint32_t PWM_T::RESERVE7[1]

Definition at line 5864 of file M471M_R1_S.h.

◆ RESERVE8

__I uint32_t PWM_T::RESERVE8[2]

Definition at line 5867 of file M471M_R1_S.h.

◆ RESERVE9

__I uint32_t PWM_T::RESERVE9[55]

Definition at line 5869 of file M471M_R1_S.h.

◆ RLDCNT

WWDT_T::RLDCNT

Offset: 0x00 WWDT Reload Counter Register

Bits Field Descriptions
[31:0] WWDT_RLDCNT WWDT Reload Counter Register
Writing 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.
Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT (WWDT_CTL[21:16]).
If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT , WWDT reset signal will generate immediately.

Definition at line 13701 of file M471M_R1_S.h.

◆ RSTSTS

SYS_T::RSTSTS

Offset: 0x04 System Reset Status Register

Bits Field Descriptions
[0] PORF POR Reset Flag
The POR reset flag is set by the "Reset Signal" from the Power-On Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.
0 = No reset from POR or CHIPRST.
1 = Power-On Reset (POR) or CHIPRST had issued the reset signal to reset the system.
Note: Write 1 to clear this bit to 0.
[1] PINRF nRESET Pin Reset Flag
The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source.
0 = No reset from nRESET pin.
1 = Pin nRESET had issued the reset signal to reset the system.
Note: Write 1 to clear this bit to 0.
[2] WDTRF WDT Reset Flag
The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.
0 = No reset from watchdog timer or window watchdog timer.
1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system.
Note1:
Write 1 to clear this bit to 0.
Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset.
Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset.
[3] LVRF LVR Reset Flag
The LVR reset flag is set by the "Reset Signal" from the Low-Voltage-Reset Controller to indicate the previous reset source.
0 = No reset from LVR.
1 = LVR controller had issued the reset signal to reset the system.
Note: Write 1 to clear this bit to 0.
[4] BODRF BOD Reset Flag
The BOD reset flag is set by the "Reset Signal" from the Brown-Out-Detector to indicate the previous reset source.
0 = No reset from BOD.
1 = The BOD had issued the reset signal to reset the system.
Note: Write 1 to clear this bit to 0.
[5] SYSRF System Reset Flag
The system reset flag is set by the "Reset Signal" from the Cortex-M4 Core to indicate the previous reset source.
0 = No reset from Cortex-M4.
1 = The Cortex-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M4 core.
Note: Write 1 to clear this bit to 0.
[7] CPURF CPU Reset Flag
The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M4 Core and Flash Memory Controller (FMC).
0 = No reset from CPU.
1 = The Cortex-M4 Core and FMC are reset by software setting CPURST to 1.
Note: Write 1 to clear this bit to 0.
[8] CPULKRF CPU Lockup Reset Flag
The CPU reset flag is set by hardware if Cortex-M4 lockup happened.
0 = No reset from CPU lockup happened.
1 = The Cortex-M4 lockup happened and chip is reset.
Note: Write 1 to clear this bit to 0.

Definition at line 10309 of file M471M_R1_S.h.

◆ RWEN

RTC_T::RWEN

Offset: 0x04 RTC Access Enable Register

Bits Field Descriptions
[15:0] RWEN RTC Register Access Enable Password (Write Only)
Writing 0xA965 to this register will enable RTC access and keep 1024 RTC clock.
[16] RWENF RTC Register Access Enable Flag (Read Only)
0 = RTC register read/write Disabled.
1 = RTC register read/write Enabled.
This bit will be set after RTC_RWEN[15:0] register is load a 0xA965, and be cleared automatically after 1024 RTC clock.

Definition at line 7638 of file M471M_R1_S.h.

◆ RX

SPI_T::RX

Offset: 0x30 Data Receive Register

Bits Field Descriptions
[31:0] RX Data Receive Register
There are 8-/4-level FIFO buffers in this controller.
The data receive register holds the data received from SPI data input pin.
If the RXEMPTY (SPI_STATUS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register.
This is a read only register.

Definition at line 9314 of file M471M_R1_S.h.

◆ RXTOUT

SC_T::RXTOUT

Offset: 0x10 SC Receive buffer Time-out Register.

Bits Field Descriptions
[8:0] RFTM SC Receiver FIFO Time-out (ETU Base)
The time-out counter resets and starts counting whenever the RX buffer received a new data word.
Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SC_DAT buffer, a receiver time-out interrupt INT_RTMR will be generated(if RXTOIF(SC_INTEN[9]) = 1 ).
Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5.
Note2:
Filling all 0 to this field indicates to disable this function.

Definition at line 8496 of file M471M_R1_S.h.

◆ SA

DSCT_T::SA

Offset: 0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74/0x84/0x94/0xA4/0xB4 Source Address Register of PDMA Channel 0~11

Bits Field Descriptions
[31:0] SA PDMA Transfer Source Address Register
This field indicates a 32-bit source address of PDMA controller.

Definition at line 3993 of file M471M_R1_S.h.

◆ SCATBA

PDMA_T::SCATBA

Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register

Bits Field Descriptions
[31:16] SCATBA PDMA Scatter-Gather Descriptor Table Address Register
In Scatter-Gather mode, this is the base address for calculating the next link - list address.
The next link address equation is.
Next Link Address = PDMA_SCATBA + PDMA_DSCT_NEXT.
Note: Only useful in Scatter-Gather mode.

Definition at line 4340 of file M471M_R1_S.h.

◆ SCATSTS

PDMA_T::SCATSTS

Offset: 0x428 PDMA Scatter-Gather Table Empty Status Register

Bits Field Descriptions
[11:0] TEMPTYFn Scatter-Gather Table Empty Flag Register
This bit indicates which PDMA channel n Scatter Gather table is empty when SWREQn set to high or channel has finished transmission and the operation mode is Stop mode.
User can write 1 to clear these bits.
0 = PDMA channel scatter-gather table is not empty.
1 = PDMA channel scatter-gather table is empty and PDMA SWREQ has be set.

Definition at line 4335 of file M471M_R1_S.h.

◆ SCTL

EADC_T::SCTL

Offset: 0x80-0x8C A/D Sample Module n Control Register, n=0~3

Bits Field Descriptions
[3:0] CHSEL A/D Sample Module Channel Selection
00H = EADC_CH0.
01H = EADC_CH1.
02H = EADC_CH2.
03H = EADC_CH3.
04H = EADC_CH4.
05H = EADC_CH5.
06H = EADC_CH6.
07H = EADC_CH7.
08H = EADC_CH8.
09H = EADC_CH9.
0AH = EADC_CH10.
0BH = EADC_CH11.
0CH = EADC_CH12.
0DH = EADC_CH13.
0EH = EADC_CH14.
0FH = EADC_CH15.
[4] EXTREN A/D External Trigger Rising Edge Enable Bit
0 = Rising edge Disabled when A/D selects STADC as trigger source.
1 = Rising edge Enabled when A/D selects STADC as trigger source.
[5] EXTFEN A/D External Trigger Falling Edge Enable Bit
0 = Falling edge Disabled when A/D selects STADC as trigger source.
1 = Falling edge Enabled when A/D selects STADC as trigger source.
[7:6] TRGDLYDIV A/D Sample Module Start Of Conversion Trigger Delay Clock Divider Selection
Trigger delay clock frequency:
00 = ADC_CLK/1.
01 = ADC_CLK/2.
10 = ADC_CLK/4.
11 = ADC_CLK/16.
[15:8] TRGDLYCNT A/D Sample Module Start Of Conversion Trigger Delay Time
Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting).
[20:16] TRGSEL A/D Sample Module Start Of Conversion Trigger Source Selection
0H = Disable trigger.
1H = External trigger from STADC pin input.
2H = ADC ADINT0 interrupt EOC (End of conversion) pulse trigger.
3H = ADC ADINT1 interrupt EOC (End of conversion) pulse trigger.
4H = Timer0 overflow pulse trigger.
5H = Timer1 overflow pulse trigger.
6H = Timer2 overflow pulse trigger.
7H = Timer3 overflow pulse trigger.
8H = PWM0TG0.
9H = PWM0TG1.
AH = PWM0TG2.
BH = PWM0TG3.
CH = PWM0TG4.
DH = PWM0TG5.
EH = PWM1TG0.
FH = PWM1TG1.
10H = PWM1TG2.
11H = PWM1TG3.
12H = PWM1TG4.
13H = PWM1TG5.
other = Reserved.
[22] INTPOS Interrupt Flag Position Select
0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D end of conversion.
1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D start of conversion.
[23] DBMEN Double Buffer Mode Enable Bit
0 = Sample has one sample result register. (default).
1 = Sample has two sample result registers.
[31:24] EXTSMPT ADC Sampling Time Extend
When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend A/D sampling time after trigger source is coming to get enough sampling time.
The range of start delay time is from 0~255 ADC clock.

Offset: 0x90-0xBC A/D Sample Module n Control Register, n=4~15

Bits Field Descriptions
[3:0] CHSEL A/D Sample Module Channel Selection
00H = EADC_CH0.
01H = EADC_CH1.
02H = EADC_CH2.
03H = EADC_CH3.
04H = EADC_CH4.
05H = EADC_CH5.
06H = EADC_CH6.
07H = EADC_CH7.
08H = EADC_CH8.
09H = EADC_CH9.
0AH = EADC_CH10.
0BH = EADC_CH11.
0CH = EADC_CH12.
0DH = EADC_CH13.
0EH = EADC_CH14.
0FH = EADC_CH15.
[4] EXTREN A/D External Trigger Rising Edge Enable Bit
0 = Rising edge Disabled when A/D selects STADC as trigger source.
1 = Rising edge Enabled when A/D selects STADC as trigger source.
[5] EXTFEN A/D External Trigger Falling Edge Enable Bit
0 = Falling edge Disabled when A/D selects STADC as trigger source.
1 = Falling edge Enabled when A/D selects STADC as trigger source.
[7:6] TRGDLYDIV[1:0] A/D Sample Module Start Of Conversion Trigger Delay Clock Divider Selection
Trigger delay clock frequency:
00 = ADC_CLK/1.
01 = ADC_CLK/2.
10 = ADC_CLK/4.
11 = ADC_CLK/16.
[15:8] TRGDLYCNT[7:0] A/D Sample Module Start Of Conversion Trigger Delay Time
Trigger delay time = TRGDLYCNT x ADC_CLK x n (n=1,2,4,16 from TRGDLYDIV setting).
[20:16] TRGSEL A/D Sample Module Start Of Conversion Trigger Source Selection
0H = Disable trigger.
1H = External trigger from STADC pin input.
2H = ADC ADINT0 interrupt EOC pulse trigger.
3H = ADC ADINT1 interrupt EOC pulse trigger.
4H = Timer0 overflow pulse trigger.
5H = Timer1 overflow pulse trigger.
6H = Timer2 overflow pulse trigger.
7H = Timer3 overflow pulse trigger.
8H = PWM0TG0.
9H = PWM0TG1.
AH = PWM0TG2.
BH = PWM0TG3.
CH = PWM0TG4.
DH = PWM0TG5.
EH = PWM1TG0.
FH = PWM1TG1.
10H = PWM1TG2.
11H = PWM1TG3.
12H = PWM1TG4.
13H = PWM1TG5.
other = Reserved.
[22] INTPOS Interrupt Flag Position Select
0 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D end of conversion.
1 = Set ADIFn (EADC_STATUS2[n], n=0~3) at A/D start of conversion.
[31:24] EXTSMPT ADC Sampling Time Extend
When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.
The range of start delay time is from 0~255 ADC clock.

Offset: 0xC0~0xC8 A/D Sample Module n Control Register, n=16~18

Bits Field Descriptions
[31:24] EXTSMPT ADC Sampling Time Extend
When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.
The range of start delay time is from 0~255 ADC clock.

Definition at line 728 of file M471M_R1_S.h.

◆ SE0

USBD_T::SE0

Offset: 0x90 USB Drive SE0 Control Register

Bits Field Descriptions
[0] DRVSE0 Drive Single Ended Zero In USB Bus
The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low.
0 = None.
1 = Force USB PHY transceiver to drive SE0.

Definition at line 12517 of file M471M_R1_S.h.

◆ SEED

CRC_T::SEED

Offset: 0x08 CRC Seed Register

Bits Field Descriptions
[31:0] SEED CRC Seed Value
This field indicates the CRC seed value.

Definition at line 1810 of file M471M_R1_S.h.

◆ SLEWCTL

GPIO_T::SLEWCTL

Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168 Port A-F High Slew Rate Control Register

Bits Field Descriptions
[n] HSRENn Port A-F Pin[n] High Slew Rate Control
0 = Px.n output with basic slew rate.
1 = Px.n output with higher slew rate.
Note:
n=0~15 for port A/B/C/D.
n=0~14 for port E.
n=0~7 for port F.

Definition at line 2662 of file M471M_R1_S.h.

◆ SMTEN

GPIO_T::SMTEN

Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164 Port A-F Input Schmitt Trigger Enable Register

Bits Field Descriptions
[n] SMTENn Port A-F Pin[n] Input Schmitt Trigger Enable Bit
0 = Px.n input Schmitt trigger function Disabled.
1 = Px.n input Schmitt trigger function Enabled.
Note:
n=0~15 for port A/B/C/D.
n=0~14 for port E.
n=0~7 for port F.

Definition at line 2661 of file M471M_R1_S.h.

◆ SPR

RTC_T::SPR

Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19

Bits Field Descriptions
[31:0] SPARE Spare Register
This field is used to store back-up information defined by user.
This field will be cleared by hardware automatically once a snooper pin event is detected.
Before storing back-up information in to RTC_SPRx register, user should write 0xA965 to RTC_RWEN[15:0] to make sure register read/write enable bit REWNF (RTC_RWEN[16]) is enabled.

Definition at line 7653 of file M471M_R1_S.h.

◆ SPRCTL

RTC_T::SPRCTL

Offset: 0x3C RTC Spare Functional Control Register

Bits Field Descriptions
[0] SNPDEN Snoop Detection Enable Bit
0 = TAMPER pin detection is Disabled.
1 = TAMPER pin detection is Enabled.
[1] SNPTYPE0 Snoop Detection Level
This bit controls TAMPER detect event is high level/rising edge or low level/falling edge.
0 = Low level/Falling edge detection.
1 = High level/Rising edge detection.
[2] SPRRWEN Spare Register Enable Bit
0 = Spare register is Disabled.
1 = Spare register is Enabled.
Note: When spare register is disabled, RTC_SPR0 ~ RTC_SPR19 cannot be accessed.
[3] SNPTYPE1 Snoop Detection Mode
This bit controls TAMPER pin is edge or level detection
0 = Level detection.
1 = Edge detection.
[5] SPRCSTS SPR Clear Flag
This bit indicates if the RTC_SPR0 ~RTC_SPR19 content is cleared when specify snoop event is detected.
0 = Spare register content is not cleared.
1 = Spare register content is cleared.
Writes 1 to clear this bit.
[7] SPRRWRDY SPR Register Ready
This bit indicates if the registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 are ready to be accessed.
After user writing registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19, read this bit to check if these registers are updated done is necessary.
0 = RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 updating is in progress.
1 = RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR19 are updated done and ready to be accessed.
Note: This bit is read only and any write to it won't take any effect.

Definition at line 7652 of file M471M_R1_S.h.

◆ SRAM_BISTCTL

SYS_T::SRAM_BISTCTL

Offset: 0xD0 System SRAM BIST Test Control Register

Bits Field Descriptions
[0] SRBIST0 1st
SRAM BIST Enable Bit
This bit enables BIST test for SRAM located in address 0x2000_0000 ~0x2000_3FFF
0 = system SRAM BIST Disabled.
1 = system SRAM BIST Enabled.
[1] SRBIST1 2nd
SRAM BIST Enable Bit
This bit enables BIST test for SRAM located in address 0x2000_4000 ~0x2000_7FFF
0 = system SRAM BIST Disabled.
1 = system SRAM BIST Enabled.
[2] CRBIST CACHE BIST Enable Bit
This bit enables BIST test for CACHE RAM
0 = system CACHE BIST Disabled.
1 = system CACHE BIST Enabled.
[4] USBBIST USB BIST Enable Bit
This bit enables BIST test for USB RAM
0 = system USB BIST Disabled.
1 = system USB BIST Enabled.

Definition at line 10332 of file M471M_R1_S.h.

◆ SRAM_BISTSTS

SYS_T::SRAM_BISTSTS

Offset: 0xD4 System SRAM BIST Test Status Register

Bits Field Descriptions
[0] SRBISTEF0 1st System SRAM BIST Fail Flag
0 = 1st system SRAM BIST test pass.
1 = 1st system SRAM BIST test fail.
[1] SRBISTEF1 2nd System SRAM BIST Fail Flag
0 = 2nd system SRAM BIST test pass.
1 = 2nd system SRAM BIST test fail.
[2] CRBISTEF CACHE SRAM BIST Fail Flag
0 = System CACHE RAM BIST test pass.
1 = System CACHE RAM BIST test fail.
[4] USBBEF USB SRAM BIST Fail Flag
0 = USB SRAM BIST test pass.
1 = USB SRAM BIST test fail.
[16] SRBEND0 1st SRAM BIST Test Finish
0 = 1st system SRAM BIST active.
1 = 1st system SRAM BIST finish.
[17] SRBEND1 2nd SRAM BIST Test Finish
0 = 2nd system SRAM BIST is active.
1 = 2nd system SRAM BIST finish.
[18] CRBEND CACHE SRAM BIST Test Finish
0 = System CACHE RAM BIST is active.
1 = System CACHE RAM BIST test finish.
[20] USBBEND USB SRAM BIST Test Finish
0 = USB SRAM BIST is active.
1 = USB SRAM BIST test finish.

Definition at line 10333 of file M471M_R1_S.h.

◆ SSCTL [1/2]

PWM_T::SSCTL

Offset: 0x110 PWM Synchronous Start Control Register

Bits Field Descriptions
[5:0] SSENn PWM Synchronous Start Function Enable
When synchronous start function is enabled, the PWM counter enable register (PWM_CNTEN) can be enabled by writing PWM synchronous start trigger bit (CNTSEN).
Each bit n controls the corresponding PWM channel n.
0 = PWM synchronous start function Disabled.
1 = PWM synchronous start function Enabled.

Definition at line 5865 of file M471M_R1_S.h.

◆ SSCTL [2/2]

SPI_T::SSCTL

Offset: 0x08 Slave Select Control Register

Bits Field Descriptions
[0] SS Slave Selection Control (Master Only)
If AUTOSS bit is cleared to 0,
0 = set the SPIn_SS line to inactive state.
1 = set the SPIn_SS line to active state
If the AUTOSS bit is set to 1,
0 = Keep the SPIn_SS line at inactive state.
1 = SPIn_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time.
The active state of SPIn_SS is specified in SSACTPOL (SPI_SSCTL[2]).
[2] SSACTPOL Slave Selection Active Polarity
This bit defines the active polarity of slave selection signal (SPIn_SS).
0 = The slave selection signal SPIn_SS is active low.
1 = The slave selection signal SPIn_SS is active high.
[3] AUTOSS Automatic Slave Selection Function Enable Bit (Master Only)
0 = Automatic slave selection function Disabled.
Slave selection signal will be asserted/de-asserted according to SS (SPI_SSCTL[0]).
1 = Automatic slave selection function Enabled.
[4] SLV3WIRE Slave 3-Wire Mode Enable Bit
Slave 3-wire mode is only available in SPI0.
In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPI0_CLK, SPI0_MISO, and SPI0_MOSI.
0 = 4-wire bi-direction interface.
1 = 3-wire bi-direction interface.
[5] SLVTOIEN Slave Mode Time-Out Interrupt Enable Bit (Only Supported in SPI0)
0 = Slave mode time-out interrupt Disabled.
1 = Slave mode time-out interrupt Enabled.
[6] SLVTORST Slave Mode Time-Out Reset Control (Only Supported in SPI0)
0 = When Slave mode time-out event occurs, the TX and RX control circuit will not be reset.
1 = When Slave mode time-out event occurs, the TX and RX control circuit will be reset by hardware.
[8] SLVBEIEN Slave Mode Bit Count Error Interrupt Enable Bit
0 = Slave mode bit count error interrupt Disabled.
1 = Slave mode bit count error interrupt Enabled.
[9] SLVURIEN Slave Mode TX Under Run Interrupt Enable Bit
0 = Slave mode TX under run interrupt Disabled.
1 = Slave mode TX under run interrupt Enabled.
[12] SSACTIEN Slave Select Active Interrupt Enable Bit
0 = Slave select active interrupt Disabled.
1 = Slave select active interrupt Enabled.
[13] SSINAIEN Slave Select Inactive Interrupt Enable Bit
0 = Slave select inactive interrupt Disabled.
1 = Slave select inactive interrupt Enabled.
[31:16] SLVTOCNT Slave Mode Time-Out Period (Only Supported in SPI0)
In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active.
The clock source of the time-out counter is Slave peripheral clock.
If the value is 0, it indicates the slave mode time-out function is disabled.

Definition at line 9307 of file M471M_R1_S.h.

◆ SSTRG

PWM_T::SSTRG

Offset: 0x114 PWM Synchronous Start Trigger Register

Bits Field Descriptions
[0] CNTSEN PWM Counter Synchronous Start Enable (Write Only)
PMW counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx and PWM1_CHx) start counting at the same time.
Writing this bit to 1 will also set the counter enable bit (CNTENn, n denotes channel 0 to 5) if correlated PWM channel counter synchronous start function is enabled.
Note: This bit only present in PWM0_BA.

Definition at line 5866 of file M471M_R1_S.h.

◆ STATUS [1/6]

CLK_T::STATUS

Offset: 0x50 Clock Status Monitor Register

Bits Field Descriptions
[0] HXTSTB External 4~24 MHz High-Speed Crystal Clock Source Stable Flag (Read Only)
0 = External 4~24 MHz high-speed crystal clock is not stable or disabled.
1 = External 4~24 MHz high-speed crystal clock is stable and enabled.
[1] LXTSTB External 32.768 kHz Low-Speed Crystal Clock Source Stable Flag (Read Only)
0 = External 32.768 kHz low-speed crystal clock is not stable or disabled.
1 = External 32.768 kHz low-speed crystal clock is stabled and enabled.
[2] PLLSTB Internal PLL Clock Source Stable Flag (Read Only)
0 = Internal PLL clock is not stable or disabled.
1 = Internal PLL clock is stable and enabled.
[3] LIRCSTB Internal 10 KHz Low-Speed Oscillator Clock Source Stable Flag (Read Only)
0 = Internal 10 kHz low-speed oscillator clock is not stable or disabled.
1 = Internal 10 kHz low-speed oscillator clock is stable and enabled.
[4] HIRCSTB Internal 22.1184 MHz High-Speed Oscillator Clock Source Stable Flag (Read Only)
0 = Internal 22.1184 MHz high-speed oscillator clock is not stable or disabled.
1 = Internal 22.1184 MHz high-speed oscillator clock is stable and enabled.
[7] CLKSFAIL Clock Switching Fail Flag (Read Only)
This bit is updated when software switches system clock source.
If switch target clock is stable, this bit will be set to 0.
If switch target clock is not stable, this bit will be set to 1.
0 = Clock switching success.
1 = Clock switching failure.
Note: Write 1 to clear the bit to 0.

Definition at line 1426 of file M471M_R1_S.h.

◆ STATUS [2/6]

I2C_T::STATUS

Offset: 0x0C I2C Status Register

Bits Field Descriptions
[7:0] STATUS I2C Status
The three least significant bits are always 0.
The five most significant bits contain the status code.
There are 28 possible status codes.
When the content of I2C_STATUS is F8H, no serial interrupt is requested.
Others I2C_STATUS values correspond to defined I2C states.
When each of these states is entered, a status interrupt is requested (SI = 1).
A valid status code is present in I2C_STATUS one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software.
In addition, states 00H stands for a Bus Error.
A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame.
Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.
Note:
1.
If the BUSEN and ACKMEN are enabled in slave received mode, there is SI interrupt in the 8th clock.
The user can read the I2C_STATUS = 0xf0 for the function condition has done.
2.
If the BUSEN and PECEN are enabled, the status of PECERR, I2C_BUSSTS[3], is used to substitute for I2C_STATUS to check the ACK status in the last frame when the byte count done interrupt has active and the PEC frame has been transformed.

Definition at line 3704 of file M471M_R1_S.h.

◆ STATUS [3/6]

PWM_T::STATUS

Offset: 0x120 PWM Status Register

Bits Field Descriptions
[5:0] CNTMAXFn Time-Base Counter Equal To 0xFFFF Latched Flag
Each bit n controls the corresponding PWM channel n.
0 = indicates the time-base counter never reached its maximum value 0xFFFF.
1 = indicates the time-base counter reached its maximum value, software can write 1 to clear this bit.
[10:8] SYNCINFn Input Synchronization Latched Flag
Each bit n controls the corresponding PWM channel n.
0 = Indicates no SYNC_IN event has occurred.
1 = Indicates an SYNC_IN event has occurred, software can write 1 to clear this bit.
[21:16] ADCTRGFn EADC Start Of Conversion Flag
Each bit n controls the corresponding PWM channel n.
0 = Indicates no EADC start of conversion trigger event has occurred.
1 = Indicates an EADC start of conversion trigger event has occurred, software can write 1 to clear this bit.

Definition at line 5868 of file M471M_R1_S.h.

◆ STATUS [4/6]

SC_T::STATUS

Offset: 0x20 SC Status Register.

Bits Field Descriptions
[0] RXOV RX Overflow Error Status Flag (Read Only)
This bit is set when RX buffer overflow.
If the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.
Note: This bit is read only, but it can be cleared by writing 1 to it.
[1] RXEMPTY Receiver Buffer Empty Status Flag(Read Only)
This bit indicates RX buffer empty or not.
When the last byte of Rx buffer has been read by CPU, hardware sets this bit high.
It will be cleared when SC receives any new data.
[2] RXFULL Receiver Buffer Full Status Flag (Read Only)
This bit indicates RX buffer full or not.
This bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
[4] PEF Receiver Parity Error Status Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid
"parity bit".
Note1:
This bit is read only, but it can be cleared by writing 1 to it.
Note2:
If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
[5] FEF Receiver Frame Error Status Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as logic 0).
Note1:
This bit is read only, but it can be cleared by writing 1 to it.
Note2:
If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
[6] BEF Receiver Break Error Status Flag (Read Only)
This bit is set to logic 1 whenever the received data input (RX) held in the "spacing state" (logic 0) is longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits).
.
Note1:
This bit is read only, but it can be cleared by writing 1 to it.
Note2:
If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
[8] TXOV TX Overflow Error Interrupt Status Flag (Read Only)
If TX buffer is full, an additional write to DAT(SC_DAT[7:0]) will cause this bit be set to "1" by hardware.
Note: This bit is read only, but it can be cleared by writing 1 to it.
[9] TXEMPTY Transmit Buffer Empty Status Flag (Read Only)
This bit indicates TX buffer empty or not.
When the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high.
It will be cleared when writing data into DAT(SC_DAT[7:0]) (TX buffer not empty).
[10] TXFULL Transmit Buffer Full Status Flag (Read Only)
This bit indicates TX buffer full or not.This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
[11] CREMOVE Card Detect Removal Status Of SC_CD Pin (Read Only)
This bit is set whenever card has been removal.
0 = No effect.
1 = Card removed.
Note1: This bit is read only, but it can be cleared by writing "1" to it.
Note2: Card detect engine will start after SCEN (SC_CTL[0])set.
[12] CINSERT Card Detect Insert Status Of SC_CD Pin (Read Only)
This bit is set whenever card has been inserted.
0 = No effect.
1 = Card insert.
Note1: This bit is read only, but it can be cleared by writing "1" to it.
Note2: The
card detect engine will start after SCEN (SC_CTL[0]) set.
[13] CDPINSTS Card Detect Status Of SC_CD Pin Status (Read Only)
This bit is the pin status flag of SC_CD
0 = The SC_CD pin state at low.
1 = The SC_CD pin state at high.
[17:16] RXPOINT Receiver Buffer Pointer Status Flag (Read Only)
This field indicates the RX buffer pointer status flag.
When SC receives one byte from external device, RXPOINT(SC_STATUS[17:16]) increases one.
When one byte of RX buffer is read by CPU, RXPOINT(SC_STATUS[17:16]) decreases one.
[21] RXRERR Receiver Retry Error (Read Only)
This bit is set by hardware when RX has any error and retries transfer.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2 This bit is a flag and cannot generate any interrupt to CPU.
Note3: If CPU enables receiver retry function by setting RXRTYEN (SC_CTL[19]) , the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
[22] RXOVERR Receiver Over Retry Error (Read Only)
This bit is set by hardware when RX transfer error retry over retry number limit.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2: If CPU enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
[23] RXACT Receiver In Active Status Flag (Read Only)
This bit is set by hardware when RX transfer is in active.
This bit is cleared automatically when RX transfer is finished.
[25:24] TXPOINT Transmit Buffer Pointer Status Flag (Read Only)
This field indicates the TX buffer pointer status flag.
When CPU writes data into SC_DAT, TXPOINT increases one.
When one byte of TX Buffer is transferred to transmitter shift register, TXPOINT decreases one.
[29] TXRERR Transmitter Retry Error (Read Only)
This bit is set by hardware when transmitter re-transmits.
Note1: This bit is read only, but it can be cleared by writing 1 to it.
Note2 This bit is a flag and cannot generate any interrupt to CPU.
[30] TXOVERR Transmitter Over Retry Error (Read Only)
This bit is set by hardware when transmitter re-transmits over retry number limitation.
Note: This bit is read only, but it can be cleared by writing 1 to it.
[31] TXACT Transmit In Active Status Flag (Read Only)
0 = This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed.
1 = This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted.

Definition at line 8500 of file M471M_R1_S.h.

◆ STATUS [5/6]

SPI_T::STATUS

Offset: 0x14 SPI Status Register

Bits Field Descriptions
[0] BUSY Busy Status (Read Only)
0 = SPI controller is in idle state.
1 = SPI controller is in busy state.
The following listing are the bus busy conditions:
a. SPI_CTL[0] = 1 and the TXEMPTY = 0.
b. For SPI Master mode, the TXEMPTY = 1 but the current transaction is not finished yet.
c. For SPI Slave mode, the SPI_CTL[0] = 1 and there is serial clock input into the SPI core logic when slave select is active.
d. For SPI Slave mode, the SPI_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive.
[1] UNITIF Unit Transfer Interrupt Flag
0 = No transaction has been finished since this bit was cleared to 0.
1 = SPI controller has finished one unit transfer.
Note: This bit will be cleared by writing 1 to it.
[2] SSACTIF Slave Select Active Interrupt Flag
0 = Slave select active interrupt was cleared or not occurred.
1 = Slave select active interrupt event occurred.
Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
[3] SSINAIF Slave Select Inactive Interrupt Flag
0 = Slave select inactive interrupt was cleared or not occurred.
1 = Slave select inactive interrupt event occurred.
Note: Only available in Slave mode. This bit will be cleared by writing 1 to it.
[4] SSLINE Slave Select Line Bus Status (Read Only)
0 = The slave select line status is 0.
1 = The slave select line status is 1.
Note: This bit is only available in Slave mode.
If SSACTPOL (SPI_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
[5] SLVTOIF Slave Time-Out Interrupt Flag (Only Supported in SPI0)
When the Slave Select is active and the value of SLVTOCNT is not 0, as the bus clock is detected, the slave time-out counter in SPI controller logic will be started.
When the value of time-out counter is greater than or equal to the value of SLVTOCNT (SPI_SSCTL[31:16]) before one transaction is done, the slave time-out interrupt event will be asserted.
0 = Slave time-out is not active.
1 = Slave time-out is active.
Note: This bit will be cleared by writing 1 to it.
[6] SLVBEIF Slave Mode Bit Count Error Interrupt Flag
In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1.
0 = No Slave mode bit count error event.
1 = Slave mode bit count error event occurs.
Note: If the slave select active but there is no any bus clock input, the SLVBCEIF also active when the slave select goes to inactive state.
This bit will be cleared by writing 1 to it.
[7] SLVURIF Slave Mode TX Under Run Interrupt Flag
In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1.
0 = No Slave TX under run event.
1 = Slave TX under run occurs.
Note: This bit will be cleared by writing 1 to it.
[8] RXEMPTY Receive FIFO Buffer Empty Indicator (Read Only)
0 = Receive FIFO buffer is not empty.
1 = Receive FIFO buffer is empty.
[9] RXFULL Receive FIFO Buffer Full Indicator (Read Only)
0 = Receive FIFO buffer is not full.
1 = Receive FIFO buffer is full.
[10] RXTHIF Receive FIFO Threshold Interrupt Flag (Read Only)
0 = The valid data count within the RX FIFO buffer is smaller than or equal to the setting value of RXTH.
1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
[11] RXOVIF Receive FIFO Overrun Interrupt Flag
When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
0 = No FIFO is over run.
1 = Receive FIFO over run.
Note: This bit will be cleared by writing 1 to it.
[12] RXTOIF Receive Time-Out Interrupt Flag
0 = No receive FIFO time-out event.
1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode.
When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
Note: This bit will be cleared by writing 1 to it.
[15] SPIENSTS SPI Enable Status (Read Only)
0 = The SPI controller is disabled.
1 = The SPI controller is enabled.
Note: The SPI peripheral clock is asynchronous with the system clock.
In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller.
[16] TXEMPTY Transmit FIFO Buffer Empty Indicator (Read Only)
0 = Transmit FIFO buffer is not empty.
1 = Transmit FIFO buffer is empty.
[17] TXFULL Transmit FIFO Buffer Full Indicator (Read Only)
0 = Transmit FIFO buffer is not full.
1 = Transmit FIFO buffer is full.
[18] TXTHIF Transmit FIFO Threshold Interrupt Flag (Read Only)
0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
[19] TXUFIF TX Underflow Interrupt Flag
When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL.
0 = No effect.
1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active.
Note 1: This bit will be cleared by writing 1 to it.
Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done.
[23] TXRXRST TX or RX Reset Status (Read Only)
0 = The reset function of TXRST or RXRST is done.
1 = Doing the reset function of TXRST or RXRST.
Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles.
User can check the status of this bit to monitor the reset function is doing or done.
[27:24] RXCNT Receive FIFO Data Count (Read Only)
This bit field indicates the valid data count of receive FIFO buffer.
[31:28] TXCNT Transmit FIFO Data Count (Read Only)
This bit field indicates the valid data count of transmit FIFO buffer.

Definition at line 9310 of file M471M_R1_S.h.

◆ STATUS [6/6]

WWDT_T::STATUS

Offset: 0x08 WWDT Status Register

Bits Field Descriptions
[0] WWDTIF WWDT Compare Match Interrupt Flag
This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).
0 = No effect.
1 = WWDT counter value matches CMPDAT.
Note: This bit is cleared by writing 1 to it.
[1] WWDTRF WWDT Timer-Out Reset Flag
This bit indicates the system has been reset by WWDT time-out reset or not.
0 = WWDT time-out reset did not occur.
1 = WWDT time-out reset occurred.
Note: This bit is cleared by writing 1 to it.

Definition at line 13703 of file M471M_R1_S.h.

◆ STATUS0

EADC_T::STATUS0

Offset: 0xF0 A/D Status Register 0

Bits Field Descriptions
[15:0] VALID EADC_DAT0~15 Data Valid Flag
It is a mirror of VALID bit in sample module A/D result data register EADC_DATn. (n=0~18).
[31:16] OV EADC_DAT0~15 Overrun Flag
It is a mirror to OV bit in sample module A/D result data register EADC_DATn. (n=0~18).

Definition at line 732 of file M471M_R1_S.h.

◆ STATUS1

EADC_T::STATUS1

Offset: 0xF4 A/D Status Register 1

Bits Field Descriptions
[2:0] VALID EADC_DAT16~18 Data Valid Flag
It is a mirror of VALID bit in sample module A/D result data register EADC_DATn. (n=0~18).
[18:16] OV EADC_DAT16~18 Overrun Flag
It is a mirror to OV bit in sample module A/D result data register EADC_DATn. (n=0~18).

Definition at line 733 of file M471M_R1_S.h.

◆ STATUS2

EADC_T::STATUS2

Offset: 0xF8 A/D Status Register 2

Bits Field Descriptions
[0] ADIF0 A/D ADINT0 Interrupt Flag
0 = No ADINT0 interrupt pulse received.
1 = ADINT0 interrupt pulse has been received.
Note1: This bit is cleared by writing 1 to it.
Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
[1] ADIF1 A/D ADINT1 Interrupt Flag
0 = No ADINT1 interrupt pulse received.
1 = ADINT1 interrupt pulse has been received.
Note1: This bit is cleared by writing 1 to it.
Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
[2] ADIF2 A/D ADINT2 Interrupt Flag
0 = No ADINT2 interrupt pulse received.
1 = ADINT2 interrupt pulse has been received.
Note1: This bit is cleared by writing 1 to it.
Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
[3] ADIF3 A/D ADINT3 Interrupt Flag
0 = No ADINT3 interrupt pulse received.
1 = ADINT3 interrupt pulse has been received.
Note1: This bit is cleared by writing 1 to it.
Note2:This bit indicates whether an A/D conversion of specific sample module has been completed
[4] ADCMPF0 ADC Compare 0 Flag
When the specific sample module A/D conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.
0 = Conversion result in EADC_DAT does not meet EADC_CMP0 register setting.
1 = Conversion result in EADC_DAT meets EADC_CMP0 register setting.
Note: This bit is cleared by writing 1 to it.
[5] ADCMPF1 ADC Compare 1 Flag
When the specific sample module A/D conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.
0 = Conversion result in EADC_DAT does not meet EADC_CMP1 register setting.
1 = Conversion result in EADC_DAT meets EADC_CMP1 register setting.
Note: This bit is cleared by writing 1 to it.
[6] ADCMPF2 ADC Compare 2 Flag
When the specific sample module A/D conversion result meets setting condition in EADC_CMP2 then this bit is set to 1.
0 = Conversion result in EADC_DAT does not meet EADC_CMP2 register setting.
1 = Conversion result in EADC_DAT meets EADC_CMP2 register setting.
Note: This bit is cleared by writing 1 to it.
[7] ADCMPF3 ADC Compare 3 Flag
When the specific sample module A/D conversion result meets setting condition in EADC_CMP3 then this bit is set to 1.
0 = Conversion result in EADC_DAT does not meet EADC_CMP3 register setting.
1 = Conversion result in EADC_DAT meets EADC_CMP3 register setting.
Note: This bit is cleared by writing 1 to it.
[8] ADOVIF0 A/D ADINT0 Interrupt Flag Overrun
0 = ADINT0 interrupt flag is not overwritten to 1.
1 = ADINT0 interrupt flag is overwritten to 1.
Note: This bit is cleared by writing 1 to it.
[9] ADOVIF1 A/D ADINT1 Interrupt Flag Overrun
0 = ADINT1 interrupt flag is not overwritten to 1.
1 = ADINT1 interrupt flag is overwritten to 1.
Note: This bit is cleared by writing 1 to it.
[10] ADOVIF2 A/D ADINT2 Interrupt Flag Overrun
0 = ADINT2 interrupt flag is not overwritten to 1.
1 = ADINT2 interrupt flag is s overwritten to 1.
Note: This bit is cleared by writing 1 to it.
[11] ADOVIF3 A/D ADINT3 Interrupt Flag Overrun
0 = ADINT3 interrupt flag is not overwritten to 1.
1 = ADINT3 interrupt flag is overwritten to 1.
Note: This bit is cleared by writing 1 to it.
[12] ADCMPO0 ADC Compare 0 Output Status
The 12 bits compare0 data CMPDAT0 (EADC_CMP0[27:16]) is used to compare with conversion result of specified sample module.
User can use it to monitor the external analog input pin voltage status.
0 = Conversion result in EADC_DAT less than CMPDAT0 setting.
1 = Conversion result in EADC_DAT great than or equal CMPDAT0
setting.
[13] ADCMPO1 ADC Compare 1 Output Status
The 12 bits compare1 data CMPDAT1 (EADC_CMP1[27:16]) is used to compare with conversion result of specified sample module.
User can use it to monitor the external analog input pin voltage status.
0 = Conversion result in EADC_DAT less than CMPDAT1 setting.
1 = Conversion result in EADC_DAT great than or equal CMPDAT1
setting.
[14] ADCMPO2 ADC Compare 2 Output Status
The 12 bits compare2 data CMPDAT2 (EADC_CMP2[27:16]) is used to compare with conversion result of specified sample module.
User can use it to monitor the external analog input pin voltage status.
0 = Conversion result in EADC_DAT less than CMPDAT2 setting.
1 = Conversion result in EADC_DAT great than or equal CMPDAT2
setting.
[15] ADCMPO3 ADC Compare 3 Output Status
The 12 bits compare3 data CMPDAT3 (EADC_CMP3[27:16]) is used to compare with conversion result of specified sample module.
User can use it to monitor the external analog input pin voltage status.
0 = Conversion result in EADC_DAT less than CMPDAT3 setting.
1 = Conversion result in EADC_DAT great than or equal CMPDAT3
setting.
[20:16] CHANNEL Current Conversion Channel
This filed reflects ADC current conversion channel when BUSY=1.
It is read only.
00H = EADC_CH0.
01H = EADC_CH1.
02H = EADC_CH2.
03H = EADC_CH3.
04H = EADC_CH4.
05H = EADC_CH5.
06H = EADC_CH6.
07H = EADC_CH7.
08H = EADC_CH8.
09H = EADC_CH9.
0AH = EADC_CH10.
0BH = EADC_CH11.
0CH = EADC_CH12.
0DH = EADC_CH13.
0EH = EADC_CH14.
0FH = EADC_CH15.
10H = VBG.
11H = VTEMP.
12H = VBAT.
[23] BUSY Busy/Idle
0 = EADC is in idle state.
1 = EADC is busy at conversion.
Note: This bit is read only.
[24] ADOVIF All A/D Interrupt Flag Overrun Bits Check
n=0~3.
0 = None of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
1 = Any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
Note: This bit will keep 1 when any ADOVIFn Flag is equal to 1.
[25] STOVF For All A/D Sample Module Start Of Conversion Overrun Flags Check
n=0~18.
0 = None of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
1 = Any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
Note: This bit will keep 1 when any SPOVFn Flag is equal to 1.
[26] AVALID For All Sample Module A/D Result Data Register EADC_DAT Data Valid Flag Check
n=0~18.
0 = None of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
1 = Any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
Note: This bit will keep 1 when any VALIDn Flag is equal to 1.
[27] AOV For All Sample Module A/D Result Data Register Overrun Flags Check
n=0~18.
0 = None of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
1 = Any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
Note: This bit will keep 1 when any OVn Flag is equal to 1.

Definition at line 734 of file M471M_R1_S.h.

◆ STATUS3

EADC_T::STATUS3

Offset: 0xFC A/D Status Register 3

Bits Field Descriptions
[4:0] CURSPL ADC Current Sample Module
This register show the current ADC is controlled by which sample module control logic modules.
If the ADC is Idle, this bit filed will set to 0x1F.
This is a read only register.

Definition at line 735 of file M471M_R1_S.h.

◆ STBUFSEG

USBD_T::STBUFSEG

Offset: 0x18 Setup Token Buffer Segmentation Register

Bits Field Descriptions
[8:3] STBUFSEG Setup Token Buffer Segmentation
It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is
USB_SRAM address + {STBUFSEG[8:3], 3'b000}
Where the USB_SRAM address = USBD_BA+0x100h.
Note: It is used for SETUP token only.

Definition at line 12515 of file M471M_R1_S.h.

◆ STOP

PDMA_T::STOP

Offset: 0x404 PDMA Transfer Stop Control Register

Bits Field Descriptions
[11:0] STOPn PDMA Transfer Stop Control Register (Write Only)
User can stop the PDMA transfer by STOPn bit field or by software reset (writing '0xFFFF_FFFF' to PDMA_STOP register).
By bit field:
0 = No effect.
1 = Stop PDMA transfer[n].
When software set PDMA_STOP bit, the operation will finish the on-going transfer channel and then clear the channel enable bit (PDMA_CHCTL [CHEN]) and request active flag.
By write 0xFFFF_FFFF to PDMA_STOP:
Setting all PDMA_STOP bit to "1" will generate software reset to reset internal state machine (the DSCT will not be reset).
When software reset, the operation will be stopped imminently that include the on-going transfer and the channel enable bit (PDMA_CHCTL [CHEN]) and request active flag will be cleared to '0'.
Note: User can poll channel enable bit to know if the on-going transfer is finished.

Definition at line 4326 of file M471M_R1_S.h.

◆ SWBRK

PWM_T::SWBRK

Offset: 0xDC PWM Software Brake Control Register

Bits Field Descriptions
[2:0] BRKETRGn PWM Edge Brake Software Trigger (Write Only) (Write Protect)
Each bit n controls the corresponding PWM pair n.
Write 1 to this bit will trigger edge brake, and set BRKEIFn to 1 in PWM_INTSTS1 register.
Note: This register is write protected. Refer to SYS_REGLCTL register.
[10:8] BRKLTRGn PWM Level Brake Software Trigger (Write Only) (Write Protect)
Each bit n controls the corresponding PWM pair n.
Write 1 to this bit will trigger level brake, and set BRKLIFn to 1 in PWM_INTSTS1 register.
Note: This register is write protected. Refer to SYS_REGLCTL register.

Definition at line 5852 of file M471M_R1_S.h.

◆ SWREQ

PDMA_T::SWREQ

Offset: 0x408 PDMA Software Request Register

Bits Field Descriptions
[11:0] SWREQn PDMA Software Request Register (Write Only)
Set this bit to 1 to generate a software request to PDMA [n].
0 = No effect.
1 = Generate a software request.
Note1: User can read PDMA_TRGSTS register to know which channel is on active.
Active flag may be triggered by software request or peripheral request.
Note2: If user does not enable each PDMA channel, the software request will be ignored.

Definition at line 4327 of file M471M_R1_S.h.

◆ SWSYNC

PWM_T::SWSYNC

Offset: 0x0C PWM Software Control Synchronization Register

Bits Field Descriptions
[2:0] SWSYNCn Software SYNC Function
Each bit n controls corresponding PWM channel n.
When SINSRCn (PWM_SYNC[13:8]) is selected to 0, SYNC_OUT source is come from SYNC_IN or this bit.

Definition at line 5818 of file M471M_R1_S.h.

◆ SWTRG

EADC_T::SWTRG

Offset: 0x54 A/D Sample Module Software Start Register

Bits Field Descriptions
[18:0] SWTRG A/D Sample Module
0~18 Software Force To Start ADC Conversion
0 = No effect.
1 = Cause an ADC conversion when the priority is given to sample module.
Note: After write this register to start ADC conversion, the EADC_PENDSTS register will show which sample module will conversion.
If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.

Definition at line 724 of file M471M_R1_S.h.

◆ SYNC

PWM_T::SYNC

Offset: 0x08 PWM Synchronization Register

Bits Field Descriptions
[2:0] PHSENn SYNC Phase Enable
Each bit n controls corresponding PWM channel n.
0 = PWM counter disable to load PHS value.
1 = PWM counter enable to load PHS value.
[13:8] SINSRCn PWM_SYNC_IN Source Selection
Each bit n controls corresponding PWM channel n.
00 = Synchronize source from SYNC_IN or SWSYNC.
01 = Counter equal to 0.
10 = Counter equal to PWM_CMPDATm, m denotes 1, 3, 5.
11 = SYNC_OUT will not be generated.
[16] SNFLTEN PWM_SYNC_IN Noise Filter Enable
0 = Noise filter of input pin PWM_SYNC_IN is Disabled.
1 = Noise filter of input pin PWM_SYNC_IN is Enabled.
[19:17] SFLTCSEL SYNC Edge Detector Filter Clock Selection
000 = Filter clock = HCLK.
001 = Filter clock = HCLK/2.
010 = Filter clock = HCLK/4.
011 = Filter clock = HCLK/8.
100 = Filter clock = HCLK/16.
101 = Filter clock = HCLK/32.
110 = Filter clock = HCLK/64.
111 = Filter clock = HCLK/128.
[22:20] SFLTCNT SYNC Edge Detector Filter Count
The register bits control the counter number of edge detector.
[23] SINPINV SYNC Input Pin Inverse
0 = The state of pin SYNC is passed to the negative edge detector.
1 = The inverted state of pin SYNC is passed to the negative edge detector.
[26:24] PHSDIRn PWM Phase Direction Control
Each bit n controls corresponding PWM channel n.
0 = Control PWM counter count decrement after synchronizing.
1 = Control PWM counter count increment after synchronizing.

Definition at line 5817 of file M471M_R1_S.h.

◆ TACTSTS

PDMA_T::TACTSTS

Offset: 0x42C PDMA Transfer Active Flag Register

Bits Field Descriptions
[11:0] TXACTFn Transfer On Active Flag Register (Read Only)
This bit indicates which PDMA channel is in active.
0 = PDMA channel is not finished.
1 = PDMA channel is active.

Definition at line 4336 of file M471M_R1_S.h.

◆ TALM

RTC_T::TALM

Offset: 0x1C Time Alarm Register

Bits Field Descriptions
[3:0] SEC 1-Sec Time Digit of Alarm Setting (0~9)
[6:4] TENSEC 10-Sec Time Digit of Alarm Setting (0~5)
[11:8] MIN 1-Min Time Digit of Alarm Setting (0~9)
[14:12] TENMIN 10-Min Time Digit of Alarm Setting (0~5)
[19:16] HR 1-Hour Time Digit of Alarm Setting (0~9)
[21:20] TENHR 10-Hour Time Digit of Alarm Setting (0~2)

Definition at line 7644 of file M471M_R1_S.h.

◆ TAMPCTL

RTC_T::TAMPCTL

Offset: 0x10C TAMPER Pin Control Register

Bits Field Descriptions
[1:0] OPMODE IO Operation Mode
00 = TAMPER (PF.2) is input only mode, without pull-up resistor.
01 = TAMPER (PF.2) is output push pull mode.
10 = TAMPER (PF.2) is open drain mode.
11 = TAMPER (PF.2) is input only mode with internal pull up.
[2] DOUT IO Output Data
0 = TAMPER (PF.2) output low.
1 = TAMPER (PF.2) output high.
[3] CTLSEL IO Pin State Backup Selection
When tamper function is disabled, TAMPER pin can be used as GPIO function.
User can program CTLSEL bit to decide PF.2 I/O function is controlled by system power domain GPIO module or VBAT power domain RTC_TAMPCTL control register.
0 =TAMPER (PF.2) I/O function is controlled by GPIO module.
It becomes floating state when system power is turned off.
1 =TAMPER (PF.2) I/O function is controlled by VBAT power domain.
PF.2 function and I/O status are controlled by OPMODE[1:0] and DOUT after CTLSEL it set to 1.
I/O pin state keeps previous state after system power is turned off.

Definition at line 7658 of file M471M_R1_S.h.

◆ TAMSK

RTC_T::TAMSK

Offset: 0x34 Time Alarm Mask Register

Bits Field Descriptions
[0] MSEC Mask 1-Sec Time Digit of Alarm Setting (0~9)
[1] MTENSEC Mask 10-Sec Time Digit of Alarm Setting (0~5)
[2] MMIN Mask 1-Min Time Digit of Alarm Setting (0~9)
[3] MTENMIN Mask 10-Min Time Digit of Alarm Setting (0~5)
[4] MHR Mask 1-Hour Time Digit of Alarm Setting (0~9)
[5] MTENHR Mask 10-Hour Time Digit of Alarm Setting (0~2)

Definition at line 7650 of file M471M_R1_S.h.

◆ TCTL0

EBI_T::TCTL0

Offset: 0x04 External Bus Interface Bank0 Timing Control Register

Bits Field Descriptions
[7:3] TACC EBI Data Access Time
TACC define data access time (tACC).
tACC = (TACC +1) * EBI_MCLK.
[10:8] TAHD EBI Data Access Hold Time
TAHD define data access hold time (tAHD).
tAHD = (TAHD +1) * EBI_MCLK.
[15:12] W2X Idle Cycle After Write
This field defines the number of W2X idle cycle.
W2X idle cycle = (W2X * EBI_MCLK).
When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
[22] RAHDOFF Access Hold Time Disable Control When Read
0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
[23] WAHDOFF Access Hold Time Disable Control When Write
0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
[27:24] R2R Idle Cycle Between Read-To-Read
This field defines the number of R2R idle cycle.
R2R idle cycle = (R2R * EBI_MCLK).
When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.

Definition at line 1997 of file M471M_R1_S.h.

◆ TCTL1

EBI_T::TCTL1

Offset: 0x14 External Bus Interface Bank1 Timing Control Register

Bits Field Descriptions
[7:3] TACC EBI Data Access Time
TACC define data access time (tACC).
tACC = (TACC +1) * EBI_MCLK.
[10:8] TAHD EBI Data Access Hold Time
TAHD define data access hold time (tAHD).
tAHD = (TAHD +1) * EBI_MCLK.
[15:12] W2X Idle Cycle After Write
This field defines the number of W2X idle cycle.
W2X idle cycle = (W2X * EBI_MCLK).
When write action is finish, W2X idle cycle is inserted and EBI_nCS return to idle state.
[22] RAHDOFF Access Hold Time Disable Control When Read
0 = The Data Access Hold Time (tAHD) during EBI reading is Enabled.
1 = The Data Access Hold Time (tAHD) during EBI reading is Disabled.
[23] WAHDOFF Access Hold Time Disable Control When Write
0 = The Data Access Hold Time (tAHD) during EBI writing is Enabled.
1 = The Data Access Hold Time (tAHD) during EBI writing is Disabled.
[27:24] R2R Idle Cycle Between Read-To-Read
This field defines the number of R2R idle cycle.
R2R idle cycle = (R2R * EBI_MCLK).
When read action is finish and next action is going to read, R2R idle cycle is inserted and EBI_nCS return to idle state.

Definition at line 2000 of file M471M_R1_S.h.

◆ TDSTS

PDMA_T::TDSTS

Offset: 0x424 PDMA Channel Transfer Done Flag Register

Bits Field Descriptions
[11:0] TDIFn Transfer Done Flag Register
This bit indicates whether PDMA controller channel transfer has been finished or not, user can write 1 to clear these bits.
0 = PDMA channel transfer has not finished.
1 = PDMA channel has finished transmission.

Definition at line 4334 of file M471M_R1_S.h.

◆ TICK

RTC_T::TICK

Offset: 0x30 RTC Time Tick Register

Bits Field Descriptions
[2:0] TICK Time Tick Register
These bits are used to select RTC time tick period for Periodic Time Tick Interrupt request.
000 = Time tick is 1 second.
001 = Time tick is 1/2 second.
010 = Time tick is 1/4 second.
011 = Time tick is 1/8 second.
100 = Time tick is 1/16 second.
101 = Time tick is 1/32 second.
110 = Time tick is 1/64 second.
111 = Time tick is 1/28 second.
Note: This register can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active.

Definition at line 7649 of file M471M_R1_S.h.

◆ TIME

RTC_T::TIME

Offset: 0x0C Time Loading Register

Bits Field Descriptions
[3:0] SEC 1-Sec Time Digit (0~9)
[6:4] TENSEC 10-Sec Time Digit (0~5)
[11:8] MIN 1-Min Time Digit (0~9)
[14:12] TENMIN 10-Min Time Digit (0~5)
[19:16] HR 1-Hour Time Digit (0~9)
[21:20] TENHR 10-Hour Time Digit (0~2)

Definition at line 7640 of file M471M_R1_S.h.

◆ TMRCTL0

SC_T::TMRCTL0

Offset: 0x28 SC Internal Timer Control Register 0.

Bits Field Descriptions
[23:0] CNT Timer 0 Counter Value (ETU Base)
This field indicates the internal timer operation values.
[27:24] OPMODE Timer 0 Operation Mode Selection
This field indicates the internal 24-bit timer operation selection.
Refer to 6.17.5.4 for programming Timer0

Definition at line 8502 of file M471M_R1_S.h.

◆ TMRCTL1

SC_T::TMRCTL1

Offset: 0x2C SC Internal Timer Control Register 1.

Bits Field Descriptions
[7:0] CNT Timer 1 Counter Value (ETU Base)
This field indicates the internal timer operation values.
[27:24] OPMODE Timer 1 Operation Mode Selection
This field indicates the internal 8-bit timer operation selection.
Refer to 6.17.5.4 for programming Timer1

Definition at line 8503 of file M471M_R1_S.h.

◆ TMRCTL2

SC_T::TMRCTL2

Offset: 0x30 SC Internal Timer Control Register 2.

Bits Field Descriptions
[7:0] CNT Timer 2 Counter Value (ETU Base)
This field indicates the internal timer operation values.
[27:24] OPMODE Timer 2 Operation Mode Selection
This field indicates the internal 8-bit timer operation selection
Refer to 6.17.5.4 for programming Timer2

Definition at line 8504 of file M471M_R1_S.h.

◆ TMRDAT0

SC_T::TMRDAT0

Offset: 0x38 SC Timer Current Data Register A.

Bits Field Descriptions
[23:0] CNT0 Timer0 Current Data Value (Read Only)
This field indicates the current count values of timer0.

Definition at line 8506 of file M471M_R1_S.h.

◆ TMRDAT1_2

SC_T::TMRDAT1_2

Offset: 0x3C SC Timer Current Data Register B.

Bits Field Descriptions
[7:0] CNT1 Timer1 Current Data Value (Read Only)
This field indicates the current count values of timer1.
[15:8] CNT2 Timer2 Current Data Value (Read Only)
This field indicates the current count values of timer2.

Definition at line 8507 of file M471M_R1_S.h.

◆ TOC0_1

PDMA_T::TOC0_1

Offset: 0x440 PDMA Time-out Counter Ch1 and Ch0 Register

Bits Field Descriptions
[31:16] TOC1 Time-Out Counter For Channel 1
This controls the period of time-out function for channel 1. The calculation unit is based on 10 kHz clock.
[15:0] TOC0 Time-Out Counter For Channel 0
This controls the period of time-out function for channel 0. The calculation unit is based on 10 kHz clock.

Definition at line 4341 of file M471M_R1_S.h.

◆ TOC2_3

PDMA_T::TOC2_3

Offset: 0x444 PDMA Time-out Counter Ch3 and Ch2 Register

Bits Field Descriptions
[31:16] TOC3 Time-Out Counter For Channel 3
This controls the period of time-out function for channel 3. The calculation unit is based on 10 kHz clock.
[15:0] TOC2 Time-Out Counter For Channel 2
This controls the period of time-out function for channel 2. The calculation unit is based on 10 kHz clock.

Definition at line 4342 of file M471M_R1_S.h.

◆ TOC4_5

PDMA_T::TOC4_5

Offset: 0x448 PDMA Time-out Counter Ch5 and Ch4 Register

Bits Field Descriptions
[31:16] TOC5 Time-Out Counter For Channel 5
This controls the period of time-out function for channel 5. The calculation unit is based on 10 kHz clock.
[15:0] TOC4 Time-Out Counter For Channel 4
This controls the period of time-out function for channel 4. The calculation unit is based on 10 kHz clock.

Definition at line 4343 of file M471M_R1_S.h.

◆ TOC6_7

PDMA_T::TOC6_7

Offset: 0x44C PDMA Time-out Counter Ch7 and Ch6 Register

Bits Field Descriptions
[31:16] TOC7 Time-Out Counter For Channel 7
This controls the period of time-out function for channel 7. The calculation unit is based on 10 kHz clock.
[15:0] TOC6 Time-Out Counter For Channel 6
This controls the period of time-out function for channel 6. The calculation unit is based on 10 kHz clock.

Definition at line 4344 of file M471M_R1_S.h.

◆ TOCTL

I2C_T::TOCTL

Offset: 0x14 I2C Time-out Control Register

Bits Field Descriptions
[0] TOIF Time-Out Flag
This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.
Note: Software can write 1 to clear this bit.
[1] TOCDIV4 Time-Out Counter Input Clock Divided By 4
When Enabled, The time-out period is extend 4 times.
0 = Disabled.
1 = Enabled.
[2] TOCEN Time-Out Counter Enable Bit
When Enabled, the 14-bit time-out counter will start counting when SI is clear.
Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared.
0 = Disabled.
1 = Enabled.

Definition at line 3706 of file M471M_R1_S.h.

◆ TOUT

UART_T::TOUT

Offset: 0x20 UART Time-out Register

Bits Field Descriptions
[7:0] TOIC Time-Out Interrupt Comparator
The time-out counter resets and starts counting (the counting clock = baud rate) whenever the RX FIFO receives a new data word.
Once the content of time-out counter is equal to that of time-out interrupt comparator (TOIC (UART_TOUT[7:0])), a receiver time-out interrupt (RXTOINT(UART_INTSTS[12])) is generated if RXTOIEN (UART_INTEN [4]) enabled.
A new incoming data word or RX FIFO empty will clear RXTOINT(UART_INTSTS[12]).
In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255.
So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer.
[15:8] DLY TX Delay Time Value
This field is used to programming the transfer delay time between the last stop bit and next start bit.
The unit is bit time.

Definition at line 11891 of file M471M_R1_S.h.

◆ TOUTEN

PDMA_T::TOUTEN

Offset: 0x434 PDMA Time-out Enable register

Bits Field Descriptions
[7:0] TOUTENn PDMA Time-Out Enable Bits
0 = PDMA Channel n time-out function Disable.
1 = PDMA Channel n time-out function Enable.

Definition at line 4338 of file M471M_R1_S.h.

◆ TOUTIEN

PDMA_T::TOUTIEN

Offset: 0x438 PDMA Time-out Interrupt Enable register

Bits Field Descriptions
[7:0] TOUTIENn PDMA Time-Out Interrupt Enable Bits
0 = PDMA Channel n time-out interrupt Disable.
1 = PDMA Channel n time-out interrupt Enable.

Definition at line 4339 of file M471M_R1_S.h.

◆ TRGSTS

PDMA_T::TRGSTS

Offset: 0x40C PDMA Channel Request Status Register

Bits Field Descriptions
[11:0] REQSTSn PDMA Channel Request Status (Read Only)
This flag indicates whether channel[n] have a request or not, no matter request from software or peripheral.
When PDMA controller finishes channel transfer, this bit will be cleared automatically.
0 = PDMA Channel n has no request.
1 = PDMA Channel n has a request.
Note1: If software stops each PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer.
Note2: Software reset (writing 0xFFFF_FFFF to PDMA_STOP register) will also clear this bit.

Definition at line 4328 of file M471M_R1_S.h.

◆ TX

SPI_T::TX

Offset: 0x20 Data Transmit Register

Bits Field Descriptions
[31:0] TX Data Transmit Register
The data transmit registers pass through the transmitted data into the 8-/4-level transmit FIFO buffer.
The number of valid bits depends on the setting of DWIDTH (SPI_CTL[12:8]).
For example, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted.
If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.
Note: In Master mode, SPI controller will start to transfer after 5 peripheral clock cycles after user writes to this register.

Definition at line 9312 of file M471M_R1_S.h.

◆ UARTCTL

SC_T::UARTCTL

Offset: 0x34 SC UART Mode Control Register.

Bits Field Descriptions
[0] UARTEN UART Mode Enable Bit
0 = Smart Card mode.
1 = UART mode.
Note1: When operating in UART mode, user must set CONSEL (SC_CTL[5:4]) = 00 and AUTOCEN(SC_CTL[3]) = 0.
Note2: When operating in Smart Card mode, user must set UARTEN(SC_UARTCTL [0]) = 00.
Note3: When UART is enabled, hardware will generate a reset to reset FIFO and internal state machine.
[5:4] WLS10 Word Length Selection
00 = Word length is 8 bits.
01 = Word length is 7 bits.
10 = Word length is 6 bits.
11 = Word length is 5 bits.
Note: In smart card mode, this WLS must be '00'
[6] PBOFF Parity Bit Disable Control
0 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data.
1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer.
Note: In smart card mode, this field must be '0' (default setting is with parity bit)
[7] OPE Odd Parity Enable Bit
0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
Note: This bit has effect only when PBOFF bit is '0'.

Definition at line 8505 of file M471M_R1_S.h.

◆ USBPHY

SYS_T::USBPHY

Offset: 0x2C USB PHY Control Register

Bits Field Descriptions
[1:0] USBROLE USB Role Option (Write Protect)
These two bits are used to select the role of USB.
00 = Standard USB Device mode.
01 = Standard USB Host mode.
10 = ID dependent mode.
11 = On-The-Go device mode.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.
[8] LDO33EN USB LDO33 Enable Bit (Write Protect)
0 = USB LDO33 Disabled.
1 = USB LDO33 Enabled.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 10319 of file M471M_R1_S.h.

◆ VBUSDET

USBD_T::VBUSDET

Offset: 0x14 USB Device VBUS Detection Register

Bits Field Descriptions
[0] FLDET Device VBUS Detected
0 = Controller is not attached into the USB host.
1 =Controller is attached into the BUS.

Definition at line 12514 of file M471M_R1_S.h.

◆ VREFCTL

SYS_T::VREFCTL

Offset: 0x28 VREF Control Register

Bits Field Descriptions
[4:0] VREFCTL VREF Control Bits (Write Protect)
00011 = VREF is internal 2.65V.
00111 = VREF is internal 2.048V.
01011 = VREF is internal 3.072V.
01111 = VREF is internal 4.096V.
Others = Reserved.
Note: This bit is write protected. Refer to the SYS_REGLCTL register.

Definition at line 10318 of file M471M_R1_S.h.

◆ WEEKDAY

RTC_T::WEEKDAY

Offset: 0x18 Day of the Week Register

Bits Field Descriptions
[2:0] WEEKDAY Day Of The Week Register
000 = Sunday.
001 = Monday.
010 = Tuesday.
011 = Wednesday.
100 = Thursday.
101 = Friday.
110 = Saturday.
111 = Reserved.

Definition at line 7643 of file M471M_R1_S.h.

◆ WGCTL0

PWM_T::WGCTL0

Offset: 0xB0 PWM Generation Register 0

Bits Field Descriptions
[11:0] ZPCTLn PWM Zero Point Control
Each bit n controls the corresponding PWM channel n.
00 = Do nothing.
01 = PWM zero point output Low.
10 = PWM zero point output High.
11 = PWM zero point output Toggle.
PWM can control output level when PWM counter count to zero.
[27:16] PRDPCTLn PWM Period (Center) Point Control
Each bit n controls the corresponding PWM channel n.
00 = Do nothing.
01 = PWM period (center) point output Low.
10 = PWM period (center) point output High.
11 = PWM period (center) point output Toggle.
PWM can control output level when PWM counter count to (PERIODn+1).
Note: This bit is center point control when PWM counter operating in up-down counter type.

Definition at line 5841 of file M471M_R1_S.h.

◆ WGCTL1

PWM_T::WGCTL1

Offset: 0xB4 PWM Generation Register 1

Bits Field Descriptions
[11:0] CMPUCTLn PWM Compare Up Point Control
Each bit n controls the corresponding PWM channel n.
00 = Do nothing.
01 = PWM compare up point output Low.
10 = PWM compare up point output High.
11 = PWM compare up point output Toggle.
PWM can control output level when PWM counter up count to CMPDAT.
Note: In complementary mode, CMPUCTL1, 3, 5 use as another CMPUCTL for channel 0, 2, 4.
[27:16] CMPDCTLn PWM Compare Down Point Control
Each bit n controls the corresponding PWM channel n.
00 = Do nothing.
01 = PWM compare down point output Low.
10 = PWM compare down point output High.
11 = PWM compare down point output Toggle.
PWM can control output level when PWM counter down count to CMPDAT.
Note: In complementary mode, CMPDCTL1, 3, 5 use as another CMPDCTL for channel 0, 2, 4.

Definition at line 5842 of file M471M_R1_S.h.

◆ WKCTL

I2C_T::WKCTL

Offset: 0x3C I2C Wake-up Control Register

Bits Field Descriptions
[0] WKEN I2C Wake-Up Enable Bit
0 = I2C wake-up function Disabled.
1= I2C wake-up function Enabled.

Definition at line 3715 of file M471M_R1_S.h.

◆ WKSTS

I2C_T::WKSTS

Offset: 0x40 I2C Wake-up Status Register

Bits Field Descriptions
[0] WKIF I2C Wake-Up Flag
When chip is woken up from Power-down mode by I2C, this bit is set to 1.
Software can write 1 to clear this bit.

Definition at line 3716 of file M471M_R1_S.h.