M471M/R1/S BSP V3.01.000
The Board Support Package for M4521
Functions
Collaboration diagram for CLK Exported Functions:

Functions

__STATIC_INLINE uint32_t CLK_GetPLLClockFreq (void)
 Get PLL clock frequency. More...
 
__STATIC_INLINE uint32_t CLK_SysTickDelay (uint32_t us)
 This function execute delay function. More...
 
void CLK_DisableCKO (void)
 Disable clock divider output function. More...
 
void CLK_EnableCKO (uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
 This function enable clock divider output module clock, enable clock divider output function and set frequency selection. More...
 
void CLK_PowerDown (void)
 Enter to Power-down mode. More...
 
void CLK_Idle (void)
 Enter to Idle mode. More...
 
uint32_t CLK_GetHXTFreq (void)
 Get external high speed crystal clock frequency. More...
 
uint32_t CLK_GetLXTFreq (void)
 Get external low speed crystal clock frequency. More...
 
uint32_t CLK_GetHCLKFreq (void)
 Get HCLK frequency. More...
 
uint32_t CLK_GetPCLK0Freq (void)
 Get PCLK0 frequency. More...
 
uint32_t CLK_GetPCLK1Freq (void)
 Get PCLK1 frequency. More...
 
uint32_t CLK_GetCPUFreq (void)
 Get CPU frequency. More...
 
uint32_t CLK_SetCoreClock (uint32_t u32Hclk)
 Set HCLK frequency. More...
 
void CLK_SetHCLK (uint32_t u32ClkSrc, uint32_t u32ClkDiv)
 This function set HCLK clock source and HCLK clock divider. More...
 
void CLK_SetModuleClock (uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
 This function set selected module clock source and module clock divider. More...
 
void CLK_SetSysTickClockSrc (uint32_t u32ClkSrc)
 Set SysTick clock source. More...
 
void CLK_EnableXtalRC (uint32_t u32ClkMask)
 Enable clock source. More...
 
void CLK_DisableXtalRC (uint32_t u32ClkMask)
 Disable clock source. More...
 
void CLK_EnableModuleClock (uint32_t u32ModuleIdx)
 Enable module clock. More...
 
void CLK_DisableModuleClock (uint32_t u32ModuleIdx)
 Disable module clock. More...
 
uint32_t CLK_EnablePLL (uint32_t u32PllClkSrc, uint32_t u32PllFreq)
 Set PLL frequency. More...
 
void CLK_DisablePLL (void)
 Disable PLL. More...
 
uint32_t CLK_WaitClockReady (uint32_t u32ClkMask)
 This function check selected clock source status. More...
 
void CLK_EnableSysTick (uint32_t u32ClkSrc, uint32_t u32Count)
 Enable System Tick counter. More...
 
void CLK_DisableSysTick (void)
 Disable System Tick counter. More...
 

Detailed Description

Function Documentation

◆ CLK_DisableCKO()

void CLK_DisableCKO ( void  )

Disable clock divider output function.

Parameters
None
Returns
None

This function disable clock divider output function.

Definition at line 29 of file clk.c.

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◆ CLK_DisableModuleClock()

void CLK_DisableModuleClock ( uint32_t  u32ModuleIdx)

Disable module clock.

Parameters
[in]u32ModuleIdxis module index. Including :
Returns
None

This function is used to disable module clock.

Definition at line 503 of file clk.c.

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◆ CLK_DisablePLL()

void CLK_DisablePLL ( void  )

Disable PLL.

Parameters
None
Returns
None

This function set PLL in Power-down mode.
The register write-protection function should be disabled before using this function.

Definition at line 643 of file clk.c.

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◆ CLK_DisableSysTick()

void CLK_DisableSysTick ( void  )

Disable System Tick counter.

Parameters
None
Returns
None

This function disable System Tick counter.

Definition at line 715 of file clk.c.

◆ CLK_DisableXtalRC()

void CLK_DisableXtalRC ( uint32_t  u32ClkMask)

Disable clock source.

Parameters
[in]u32ClkMaskis clock source mask. Including :
Returns
None

This function disable clock source.
The register write-protection function should be disabled before using this function.

Definition at line 431 of file clk.c.

◆ CLK_EnableCKO()

void CLK_EnableCKO ( uint32_t  u32ClkSrc,
uint32_t  u32ClkDiv,
uint32_t  u32ClkDivBy1En 
)

This function enable clock divider output module clock, enable clock divider output function and set frequency selection.

Parameters
[in]u32ClkSrcis frequency divider function clock source. Including :
[in]u32ClkDivis divider output frequency selection. It could be 0~15.
[in]u32ClkDivBy1Enis clock divided by one enabled.
Returns
None

Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv.
The formula is:
CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1)
This function is just used to set CKO clock. User must enable I/O for CKO clock output pin by themselves.

Definition at line 52 of file clk.c.

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◆ CLK_EnableModuleClock()

void CLK_EnableModuleClock ( uint32_t  u32ModuleIdx)

Enable module clock.

Parameters
[in]u32ModuleIdxis module index. Including :
Returns
None

This function is used to enable module clock.

Definition at line 467 of file clk.c.

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◆ CLK_EnablePLL()

uint32_t CLK_EnablePLL ( uint32_t  u32PllClkSrc,
uint32_t  u32PllFreq 
)

Set PLL frequency.

Parameters
[in]u32PllClkSrcis PLL clock source. Including :
[in]u32PllFreqis PLL frequency.
Returns
PLL frequency

This function is used to configure PLLCTL register to set specified PLL frequency.
The register write-protection function should be disabled before using this function.

Definition at line 519 of file clk.c.

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◆ CLK_EnableSysTick()

void CLK_EnableSysTick ( uint32_t  u32ClkSrc,
uint32_t  u32Count 
)

Enable System Tick counter.

Parameters
[in]u32ClkSrcis System Tick clock source. Including:
[in]u32Countis System Tick reload value. It could be 0~0xFFFFFF.
Returns
None

This function set System Tick clock source, reload value, enable System Tick counter and interrupt.
The register write-protection function should be disabled before using this function.

Definition at line 688 of file clk.c.

◆ CLK_EnableXtalRC()

void CLK_EnableXtalRC ( uint32_t  u32ClkMask)

Enable clock source.

Parameters
[in]u32ClkMaskis clock source mask. Including :
Returns
None

This function enable clock source.
The register write-protection function should be disabled before using this function.

Definition at line 415 of file clk.c.

◆ CLK_GetCPUFreq()

uint32_t CLK_GetCPUFreq ( void  )

Get CPU frequency.

Parameters
None
Returns
CPU frequency

This function get CPU frequency. The frequency unit is Hz.

Definition at line 182 of file clk.c.

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◆ CLK_GetHCLKFreq()

uint32_t CLK_GetHCLKFreq ( void  )

Get HCLK frequency.

Parameters
None
Returns
HCLK frequency

This function get HCLK frequency. The frequency unit is Hz.

Definition at line 169 of file clk.c.

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◆ CLK_GetHXTFreq()

uint32_t CLK_GetHXTFreq ( void  )

Get external high speed crystal clock frequency.

Parameters
None
Returns
External high frequency crystal frequency

This function get external high frequency crystal frequency. The frequency unit is Hz.

Definition at line 108 of file clk.c.

◆ CLK_GetLXTFreq()

uint32_t CLK_GetLXTFreq ( void  )

Get external low speed crystal clock frequency.

Parameters
None
Returns
External low speed crystal clock frequency

This function get external low frequency crystal frequency. The frequency unit is Hz.

Definition at line 123 of file clk.c.

◆ CLK_GetPCLK0Freq()

uint32_t CLK_GetPCLK0Freq ( void  )

Get PCLK0 frequency.

Parameters
None
Returns
PCLK0 frequency

This function get PCLK0 frequency. The frequency unit is Hz.

Definition at line 137 of file clk.c.

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◆ CLK_GetPCLK1Freq()

uint32_t CLK_GetPCLK1Freq ( void  )

Get PCLK1 frequency.

Parameters
None
Returns
PCLK1 frequency

This function get PCLK1 frequency. The frequency unit is Hz.

Definition at line 153 of file clk.c.

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◆ CLK_GetPLLClockFreq()

__STATIC_INLINE uint32_t CLK_GetPLLClockFreq ( void  )

Get PLL clock frequency.

Parameters
None
Returns
PLL frequency

This function get PLL frequency. The frequency unit is Hz.

Definition at line 326 of file clk.h.

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◆ CLK_Idle()

void CLK_Idle ( void  )

Enter to Idle mode.

Parameters
None
Returns
None

This function let system enter to Idle mode.
The register write-protection function should be disabled before using this function.

Definition at line 90 of file clk.c.

◆ CLK_PowerDown()

void CLK_PowerDown ( void  )

Enter to Power-down mode.

Parameters
None
Returns
None

This function is used to let system enter to Power-down mode.
The register write-protection function should be disabled before using this function.

Definition at line 71 of file clk.c.

◆ CLK_SetCoreClock()

uint32_t CLK_SetCoreClock ( uint32_t  u32Hclk)

Set HCLK frequency.

Parameters
[in]u32Hclkis HCLK frequency. The range of u32Hclk is 25 MHz ~ 72 MHz.
Returns
HCLK frequency

This function is used to set HCLK frequency. The frequency unit is Hz.
It would configure PLL frequency to 50MHz ~ 144MHz, set HCLK clock divider as 2 and switch HCLK clock source to PLL.
The register write-protection function should be disabled before using this function.

Definition at line 198 of file clk.c.

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◆ CLK_SetHCLK()

void CLK_SetHCLK ( uint32_t  u32ClkSrc,
uint32_t  u32ClkDiv 
)

This function set HCLK clock source and HCLK clock divider.

Parameters
[in]u32ClkSrcis HCLK clock source. Including :
[in]u32ClkDivis HCLK clock divider. Including :
Returns
None

This function set HCLK clock source and HCLK clock divider.
The register write-protection function should be disabled before using this function.

Definition at line 258 of file clk.c.

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◆ CLK_SetModuleClock()

void CLK_SetModuleClock ( uint32_t  u32ModuleIdx,
uint32_t  u32ClkSrc,
uint32_t  u32ClkDiv 
)

This function set selected module clock source and module clock divider.

Parameters
[in]u32ModuleIdxis module index.
[in]u32ClkSrcis module clock source.
[in]u32ClkDivis module clock divider.
Returns
None

Valid parameter combinations listed in following table:

Module index Clock source Divider
WDT_MODULE CLK_CLKSEL1_WDTSEL_LXT x
WDT_MODULE CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 x
WDT_MODULE CLK_CLKSEL1_WDTSEL_LIRC x
RTC_MODULE CLK_CLKSEL3_RTCSEL_LXT x
RTC_MODULE CLK_CLKSEL3_RTCSEL_LIRC x
TMR0_MODULE CLK_CLKSEL1_TMR0SEL_HXT x
TMR0_MODULE CLK_CLKSEL1_TMR0SEL_LXT x
TMR0_MODULE CLK_CLKSEL1_TMR0SEL_PCLK0 x
TMR0_MODULE CLK_CLKSEL1_TMR0SEL_EXT_TRG x
TMR0_MODULE CLK_CLKSEL1_TMR0SEL_LIRC x
TMR0_MODULE CLK_CLKSEL1_TMR0SEL_HIRC x
TMR1_MODULE CLK_CLKSEL1_TMR1SEL_HXT x
TMR1_MODULE CLK_CLKSEL1_TMR1SEL_LXT x
TMR1_MODULE CLK_CLKSEL1_TMR1SEL_PCLK0 x
TMR1_MODULE CLK_CLKSEL1_TMR1SEL_EXT_TRG x
TMR1_MODULE CLK_CLKSEL1_TMR1SEL_LIRC x
TMR1_MODULE CLK_CLKSEL1_TMR1SEL_HIRC x
TMR2_MODULE CLK_CLKSEL1_TMR2SEL_HXT x
TMR2_MODULE CLK_CLKSEL1_TMR2SEL_LXT x
TMR2_MODULE CLK_CLKSEL1_TMR2SEL_PCLK1 x
TMR2_MODULE CLK_CLKSEL1_TMR2SEL_EXT_TRG x
TMR2_MODULE CLK_CLKSEL1_TMR2SEL_LIRC x
TMR2_MODULE CLK_CLKSEL1_TMR2SEL_HIRC x
TMR3_MODULE CLK_CLKSEL1_TMR3SEL_HXT x
TMR3_MODULE CLK_CLKSEL1_TMR3SEL_LXT x
TMR3_MODULE CLK_CLKSEL1_TMR3SEL_PCLK1 x
TMR3_MODULE CLK_CLKSEL1_TMR3SEL_EXT_TRG x
TMR3_MODULE CLK_CLKSEL1_TMR3SEL_LIRC x
TMR3_MODULE CLK_CLKSEL1_TMR3SEL_HIRC x
CLKO_MODULE CLK_CLKSEL1_CLKOSEL_HXT x
CLKO_MODULE CLK_CLKSEL1_CLKOSEL_LXT x
CLKO_MODULE CLK_CLKSEL1_CLKOSEL_HCLK x
CLKO_MODULE CLK_CLKSEL1_CLKOSEL_HIRC x
SPI0_MODULE CLK_CLKSEL2_SPI0SEL_HXT x
SPI0_MODULE CLK_CLKSEL2_SPI0SEL_PLL x
SPI0_MODULE CLK_CLKSEL2_SPI0SEL_PCLK0 x
SPI0_MODULE CLK_CLKSEL2_SPI0SEL_HIRC x
SPI1_MODULE CLK_CLKSEL2_SPI1SEL_HXT x
SPI1_MODULE CLK_CLKSEL2_SPI1SEL_PLL x
SPI1_MODULE CLK_CLKSEL2_SPI1SEL_PCLK1 x
SPI1_MODULE CLK_CLKSEL2_SPI1SEL_HIRC x
UART0_MODULE CLK_CLKSEL1_UARTSEL_HXT CLK_CLKDIV0_UART(x)
UART0_MODULE CLK_CLKSEL1_UARTSEL_PLL CLK_CLKDIV0_UART(x)
UART0_MODULE CLK_CLKSEL1_UARTSEL_LXT CLK_CLKDIV0_UART(x)
UART0_MODULE CLK_CLKSEL1_UARTSEL_HIRC CLK_CLKDIV0_UART(x)
UART1_MODULE CLK_CLKSEL1_UARTSEL_HXT CLK_CLKDIV0_UART(x)
UART1_MODULE CLK_CLKSEL1_UARTSEL_PLL CLK_CLKDIV0_UART(x)
UART1_MODULE CLK_CLKSEL1_UARTSEL_LXT CLK_CLKDIV0_UART(x)
UART1_MODULE CLK_CLKSEL1_UARTSEL_HIRC CLK_CLKDIV0_UART(x)
UART2_MODULE CLK_CLKSEL1_UARTSEL_HXT CLK_CLKDIV0_UART(x)
UART2_MODULE CLK_CLKSEL1_UARTSEL_PLL CLK_CLKDIV0_UART(x)
UART2_MODULE CLK_CLKSEL1_UARTSEL_LXT CLK_CLKDIV0_UART(x)
UART2_MODULE CLK_CLKSEL1_UARTSEL_HIRC CLK_CLKDIV0_UART(x)
UART3_MODULE CLK_CLKSEL1_UARTSEL_HXT CLK_CLKDIV0_UART(x)
UART3_MODULE CLK_CLKSEL1_UARTSEL_LXT CLK_CLKDIV0_UART(x)
UART3_MODULE CLK_CLKSEL1_UARTSEL_PLL CLK_CLKDIV0_UART(x)
UART3_MODULE CLK_CLKSEL1_UARTSEL_HIRC CLK_CLKDIV0_UART(x)
USBD_MODULE x CLK_CLKDIV0_USB(x)
EADC_MODULE x CLK_CLKDIV0_EADC(x)
SC0_MODULE CLK_CLKSEL3_SC0SEL_HXT CLK_CLKDIV1_SC0(x)
SC0_MODULE CLK_CLKSEL3_SC0SEL_PLL CLK_CLKDIV1_SC0(x)
SC0_MODULE CLK_CLKSEL3_SC0SEL_PCLK0 CLK_CLKDIV1_SC0(x)
SC0_MODULE CLK_CLKSEL3_SC0SEL_HIRC CLK_CLKDIV1_SC0(x)
PWM0_MODULE CLK_CLKSEL2_PWM0SEL_PLL x
PWM0_MODULE CLK_CLKSEL2_PWM0SEL_PCLK0 x
PWM1_MODULE CLK_CLKSEL2_PWM1SEL_PLL x
PWM1_MODULE CLK_CLKSEL2_PWM1SEL_PCLK1 x
WWDT_MODULE CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 x
WWDT_MODULE CLK_CLKSEL1_WWDTSEL_LIRC x

Definition at line 364 of file clk.c.

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◆ CLK_SetSysTickClockSrc()

void CLK_SetSysTickClockSrc ( uint32_t  u32ClkSrc)

Set SysTick clock source.

Parameters
[in]u32ClkSrcis module clock source. Including:
Returns
None

This function set SysTick clock source.
The register write-protection function should be disabled before using this function.

Definition at line 398 of file clk.c.

◆ CLK_SysTickDelay()

__STATIC_INLINE uint32_t CLK_SysTickDelay ( uint32_t  us)

This function execute delay function.

Parameters
usDelay time. The Max value is 2^24 / CPU Clock(MHz). Ex: 72MHz => 233016us, 50MHz => 335544us, 48MHz => 349525us, 28MHz => 699050us ...
Return values
0clock is not stable
1clock is stable

Use the SysTick to generate the delay time and the unit is in us. The SysTick clock source is from HCLK, i.e the same as system core clock.

Definition at line 366 of file clk.h.

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◆ CLK_WaitClockReady()

uint32_t CLK_WaitClockReady ( uint32_t  u32ClkMask)

This function check selected clock source status.

Parameters
[in]u32ClkMaskis selected clock source. Including :
Return values
0clock is not stable
1clock is stable

To wait for clock ready by specified clock source stable flag or timeout (~300ms)

Definition at line 661 of file clk.c.

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