M471M/R1/S BSP V3.01.000
The Board Support Package for M4521
M471M_R1_S.h
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1/******************************************************************************
2 * @file M471M_R1_S.h
3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for M471M/R1/S
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 * @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
7 *****************************************************************************/
47#ifndef __M471M_R1_S_H__
48#define __M471M_R1_S_H__
49
50#ifdef __cplusplus
51extern "C" {
52#endif
53
54/******************************************************************************/
55/* Processor and Core Peripherals */
56/******************************************************************************/
62/*
63 * ==========================================================================
64 * ---------- Interrupt Number Definition -----------------------------------
65 * ==========================================================================
66 */
67
68typedef enum IRQn
69{
70 /****** Cortex-M4 Processor Exceptions Numbers *************************************************/
80 /****** M471M/R1/S Specific Interrupt Numbers **************************************************/
81
96 GPA_IRQn = 16,
97 GPB_IRQn = 17,
98 GPC_IRQn = 18,
99 GPD_IRQn = 19,
100 GPE_IRQn = 20,
101 GPF_IRQn = 21,
129 SC0_IRQn = 58,
131
132
133/*
134 * ==========================================================================
135 * ----------- Processor and Core Peripheral Section ------------------------
136 * ==========================================================================
137 */
138
139/* Configuration of the Cortex-M# Processor and Core Peripherals */
140#define __CM4_REV 0x0201
141#define __NVIC_PRIO_BITS 4
142#define __Vendor_SysTickConfig 0
143#define __MPU_PRESENT 1
144#define __FPU_PRESENT 1 /* end of group CMSIS */
147
148#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
149#include "system_M471M_R1_S.h" /* M471M/R1/S System include file */
150#include <stdint.h>
151
152
153
154/******************************************************************************/
155/* Device Specific Peripheral registers structures */
156/******************************************************************************/
157
165/*---------------------- Enhanced Analog to Digital Converter -------------------------*/
172typedef struct
173{
174
175
721 __I uint32_t DAT[19]; /* Offset: 0x00-0x48 A/D Data Register n for Sample Module n, n=0~18 */
722 __I uint32_t CURDAT; /* Offset: 0x4C EADC PDMA Current Transfer Data Register */
723 __IO uint32_t CTL; /* Offset: 0x50 A/D Control Register */
724 __O uint32_t SWTRG; /* Offset: 0x54 A/D Sample Module Software Start Register */
725 __IO uint32_t PENDSTS; /* Offset: 0x58 A/D Start of Conversion Pending Flag Register */
726 __IO uint32_t OVSTS; /* Offset: 0x5C A/D Sample Module Start of Conversion Overrun Flag Register */
727 __I uint32_t RESERVE0[8];
728 __IO uint32_t SCTL[19]; /* Offset: 0x80-0xC8 A/D Sample Module n Control Register, n=0~3 */
729 __I uint32_t RESERVE1[1];
730 __IO uint32_t INTSRC[4]; /* Offset: 0xDC ADC interrupt n Source Enable Control Register, n=0~3 */
731 __IO uint32_t CMP[4]; /* Offset: 0xEC A/D Result Compare Register n, n=0~3 */
732 __I uint32_t STATUS0; /* Offset: 0xF0 A/D Status Register 0 */
733 __I uint32_t STATUS1; /* Offset: 0xF4 A/D Status Register 1 */
734 __IO uint32_t STATUS2; /* Offset: 0xF8 A/D Status Register 2 */
735 __I uint32_t STATUS3; /* Offset: 0xFC A/D Status Register 3 */
736 __I uint32_t DDAT[4]; /* Offset: 0x100-0x10C A/D Double Data Register n for Sample Module n, n=0~3 */
737
738} EADC_T;
739
740
741
746#define EADC_DAT_RESULT_Pos (0)
747#define EADC_DAT_RESULT_Msk (0xfffful << EADC_DAT_RESULT_Pos)
749#define EADC_DAT_OV_Pos (16)
750#define EADC_DAT_OV_Msk (0x1ul << EADC_DAT_OV_Pos)
752#define EADC_DAT_VALID_Pos (17)
753#define EADC_DAT_VALID_Msk (0x1ul << EADC_DAT_VALID_Pos)
755#define EADC_CURDAT_CURDAT_Pos (0)
756#define EADC_CURDAT_CURDAT_Msk (0x3fffful << EADC_CURDAT_CURDAT_Pos)
758#define EADC_CTL_ADCEN_Pos (0)
759#define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos)
761#define EADC_CTL_ADRST_Pos (1)
762#define EADC_CTL_ADRST_Msk (0x1ul << EADC_CTL_ADRST_Pos)
764#define EADC_CTL_ADCIEN0_Pos (2)
765#define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos)
767#define EADC_CTL_ADCIEN1_Pos (3)
768#define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos)
770#define EADC_CTL_ADCIEN2_Pos (4)
771#define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos)
773#define EADC_CTL_ADCIEN3_Pos (5)
774#define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos)
776#define EADC_CTL_DIFFEN_Pos (8)
777#define EADC_CTL_DIFFEN_Msk (0x1ul << EADC_CTL_DIFFEN_Pos)
779#define EADC_CTL_DMOF_Pos (9)
780#define EADC_CTL_DMOF_Msk (0x1ul << EADC_CTL_DMOF_Pos)
782#define EADC_CTL_PDMAEN_Pos (11)
783#define EADC_CTL_PDMAEN_Msk (0x1ul << EADC_CTL_PDMAEN_Pos)
785#define EADC_CTL_SMPTSEL_Pos (16)
786#define EADC_CTL_SMPTSEL_Msk (0x7ul << EADC_CTL_SMPTSEL_Pos)
788#define EADC_SWTRG_SWTRG_Pos (0)
789#define EADC_SWTRG_SWTRG_Msk (0x7fffful << EADC_SWTRG_SWTRG_Pos)
791#define EADC_PENDSTS_STPF_Pos (0)
792#define EADC_PENDSTS_STPF_Msk (0x7fffful << EADC_PENDSTS_STPF_Pos)
794#define EADC_OVSTS_SPOVF_Pos (0)
795#define EADC_OVSTS_SPOVF_Msk (0x7fffful << EADC_OVSTS_SPOVF_Pos)
797#define EADC_SCTL_CHSEL_Pos (0)
798#define EADC_SCTL_CHSEL_Msk (0xful << EADC_SCTL_CHSEL_Pos)
800#define EADC_SCTL_EXTREN_Pos (4)
801#define EADC_SCTL_EXTREN_Msk (0x1ul << EADC_SCTL_EXTREN_Pos)
803#define EADC_SCTL_EXTFEN_Pos (5)
804#define EADC_SCTL_EXTFEN_Msk (0x1ul << EADC_SCTL_EXTFEN_Pos)
806#define EADC_SCTL_TRGDLYDIV_Pos (6)
807#define EADC_SCTL_TRGDLYDIV_Msk (0x3ul << EADC_SCTL_TRGDLYDIV_Pos)
809#define EADC_SCTL_TRGDLYCNT_Pos (8)
810#define EADC_SCTL_TRGDLYCNT_Msk (0xfful << EADC_SCTL_TRGDLYCNT_Pos)
812#define EADC_SCTL_TRGSEL_Pos (16)
813#define EADC_SCTL_TRGSEL_Msk (0x1ful << EADC_SCTL_TRGSEL_Pos)
815#define EADC_SCTL_INTPOS_Pos (22)
816#define EADC_SCTL_INTPOS_Msk (0x1ul << EADC_SCTL_INTPOS_Pos)
818#define EADC_SCTL_DBMEN_Pos (23)
819#define EADC_SCTL_DBMEN_Msk (0x1ul << EADC_SCTL_DBMEN_Pos)
821#define EADC_SCTL_EXTSMPT_Pos (24)
822#define EADC_SCTL_EXTSMPT_Msk (0xfful << EADC_SCTL_EXTSMPT_Pos)
824#define EADC_INTSRC_SPLIE_Pos (0)
825#define EADC_INTSRC_SPLIE_Msk (0x7FFFFul << EADC_INTSRC_SPLIE_Pos)
827#define EADC_CMP_ADCMPEN_Pos (0)
828#define EADC_CMP_ADCMPEN_Msk (0x1ul << EADC_CMP_ADCMPEN_Pos)
830#define EADC_CMP_ADCMPIE_Pos (1)
831#define EADC_CMP_ADCMPIE_Msk (0x1ul << EADC_CMP_ADCMPIE_Pos)
833#define EADC_CMP_CMPCOND_Pos (2)
834#define EADC_CMP_CMPCOND_Msk (0x1ul << EADC_CMP_CMPCOND_Pos)
836#define EADC_CMP_CMPSPL_Pos (3)
837#define EADC_CMP_CMPSPL_Msk (0x1ful << EADC_CMP_CMPSPL_Pos)
839#define EADC_CMP_CMPMCNT_Pos (8)
840#define EADC_CMP_CMPMCNT_Msk (0xful << EADC_CMP_CMPMCNT_Pos)
842#define EADC_CMP_CMPWEN_Pos (15)
843#define EADC_CMP_CMPWEN_Msk (0x1ul << EADC_CMP_CMPWEN_Pos)
845#define EADC_CMP_CMPDAT_Pos (16)
846#define EADC_CMP_CMPDAT_Msk (0xffful << EADC_CMP_CMPDAT_Pos)
848#define EADC_STATUS0_VALID_Pos (0)
849#define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos)
851#define EADC_STATUS0_OV_Pos (16)
852#define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos)
854#define EADC_STATUS1_VALID_Pos (0)
855#define EADC_STATUS1_VALID_Msk (0x7ul << EADC_STATUS1_VALID_Pos)
857#define EADC_STATUS1_OV_Pos (16)
858#define EADC_STATUS1_OV_Msk (0x7ul << EADC_STATUS1_OV_Pos)
860#define EADC_STATUS2_ADIF0_Pos (0)
861#define EADC_STATUS2_ADIF0_Msk (0x1ul << EADC_STATUS2_ADIF0_Pos)
863#define EADC_STATUS2_ADIF1_Pos (1)
864#define EADC_STATUS2_ADIF1_Msk (0x1ul << EADC_STATUS2_ADIF1_Pos)
866#define EADC_STATUS2_ADIF2_Pos (2)
867#define EADC_STATUS2_ADIF2_Msk (0x1ul << EADC_STATUS2_ADIF2_Pos)
869#define EADC_STATUS2_ADIF3_Pos (3)
870#define EADC_STATUS2_ADIF3_Msk (0x1ul << EADC_STATUS2_ADIF3_Pos)
872#define EADC_STATUS2_ADCMPF0_Pos (4)
873#define EADC_STATUS2_ADCMPF0_Msk (0x1ul << EADC_STATUS2_ADCMPF0_Pos)
875#define EADC_STATUS2_ADCMPF1_Pos (5)
876#define EADC_STATUS2_ADCMPF1_Msk (0x1ul << EADC_STATUS2_ADCMPF1_Pos)
878#define EADC_STATUS2_ADCMPF2_Pos (6)
879#define EADC_STATUS2_ADCMPF2_Msk (0x1ul << EADC_STATUS2_ADCMPF2_Pos)
881#define EADC_STATUS2_ADCMPF3_Pos (7)
882#define EADC_STATUS2_ADCMPF3_Msk (0x1ul << EADC_STATUS2_ADCMPF3_Pos)
884#define EADC_STATUS2_ADOVIF0_Pos (8)
885#define EADC_STATUS2_ADOVIF0_Msk (0x1ul << EADC_STATUS2_ADOVIF0_Pos)
887#define EADC_STATUS2_ADOVIF1_Pos (9)
888#define EADC_STATUS2_ADOVIF1_Msk (0x1ul << EADC_STATUS2_ADOVIF1_Pos)
890#define EADC_STATUS2_ADOVIF2_Pos (10)
891#define EADC_STATUS2_ADOVIF2_Msk (0x1ul << EADC_STATUS2_ADOVIF2_Pos)
893#define EADC_STATUS2_ADOVIF3_Pos (11)
894#define EADC_STATUS2_ADOVIF3_Msk (0x1ul << EADC_STATUS2_ADOVIF3_Pos)
896#define EADC_STATUS2_ADCMPO0_Pos (12)
897#define EADC_STATUS2_ADCMPO0_Msk (0x1ul << EADC_STATUS2_ADCMPO0_Pos)
899#define EADC_STATUS2_ADCMPO1_Pos (13)
900#define EADC_STATUS2_ADCMPO1_Msk (0x1ul << EADC_STATUS2_ADCMPO1_Pos)
902#define EADC_STATUS2_ADCMPO2_Pos (14)
903#define EADC_STATUS2_ADCMPO2_Msk (0x1ul << EADC_STATUS2_ADCMPO2_Pos)
905#define EADC_STATUS2_ADCMPO3_Pos (15)
906#define EADC_STATUS2_ADCMPO3_Msk (0x1ul << EADC_STATUS2_ADCMPO3_Pos)
908#define EADC_STATUS2_CHANNEL_Pos (16)
909#define EADC_STATUS2_CHANNEL_Msk (0x1ful << EADC_STATUS2_CHANNEL_Pos)
911#define EADC_STATUS2_BUSY_Pos (23)
912#define EADC_STATUS2_BUSY_Msk (0x1ul << EADC_STATUS2_BUSY_Pos)
914#define EADC_STATUS2_ADOVIF_Pos (24)
915#define EADC_STATUS2_ADOVIF_Msk (0x1ul << EADC_STATUS2_ADOVIF_Pos)
917#define EADC_STATUS2_STOVF_Pos (25)
918#define EADC_STATUS2_STOVF_Msk (0x1ul << EADC_STATUS2_STOVF_Pos)
920#define EADC_STATUS2_AVALID_Pos (26)
921#define EADC_STATUS2_AVALID_Msk (0x1ul << EADC_STATUS2_AVALID_Pos)
923#define EADC_STATUS2_AOV_Pos (27)
924#define EADC_STATUS2_AOV_Msk (0x1ul << EADC_STATUS2_AOV_Pos)
926#define EADC_STATUS3_CURSPL_Pos (0)
927#define EADC_STATUS3_CURSPL_Msk (0x1ful << EADC_STATUS3_CURSPL_Pos)
929#define EADC_DDAT_RESULT_Pos (0)
930#define EADC_DDAT_RESULT_Msk (0xfffful << EADC_DDAT_RESULT_Pos)
932#define EADC_DDAT_OV_Pos (16)
933#define EADC_DDAT_OV_Msk (0x1ul << EADC_DDAT_OV_Pos)
935#define EADC_DDAT_VALID_Pos (17)
936#define EADC_DDAT_VALID_Msk (0x1ul << EADC_DDAT_VALID_Pos) /* EADC_CONST */ /* end of EADC register group */
941
942
943
944
945/*---------------------- System Clock Controller -------------------------*/
952typedef struct
953{
954
955
956
957
1413 __IO uint32_t PWRCTL; /* Offset: 0x00 System Power-down Control Register */
1414 __IO uint32_t AHBCLK; /* Offset: 0x04 AHB Devices Clock Enable Control Register */
1415 __IO uint32_t APBCLK0; /* Offset: 0x08 APB Devices Clock Enable Control Register 0 */
1416 __IO uint32_t APBCLK1; /* Offset: 0x0C APB Devices Clock Enable Control Register 1 */
1417 __IO uint32_t CLKSEL0; /* Offset: 0x10 Clock Source Select Control Register 0 */
1418 __IO uint32_t CLKSEL1; /* Offset: 0x14 Clock Source Select Control Register 1 */
1419 __IO uint32_t CLKSEL2; /* Offset: 0x18 Clock Source Select Control Register 2 */
1420 __IO uint32_t CLKSEL3; /* Offset: 0x1C Clock Source Select Control Register 3 */
1421 __IO uint32_t CLKDIV0; /* Offset: 0x20 Clock Divider Number Register 0 */
1422 __IO uint32_t CLKDIV1; /* Offset: 0x24 Clock Divider Number Register 1 */
1423 __I uint32_t RESERVE0[6];
1424 __IO uint32_t PLLCTL; /* Offset: 0x40 PLL Control Register */
1425 __I uint32_t RESERVE1[3];
1426 __I uint32_t STATUS; /* Offset: 0x50 Clock Status Monitor Register */
1427 __I uint32_t RESERVE2[3];
1428 __IO uint32_t CLKOCTL; /* Offset: 0x60 Clock Output Control Register */
1429 __I uint32_t RESERVE3[3];
1430 __IO uint32_t CLKDCTL; /* Offset: 0x70 Clock Fail Detector Control Register */
1431 __IO uint32_t CLKDSTS; /* Offset: 0x74 Clock Fail Detector Status Register */
1432 __IO uint32_t CDUPB; /* Offset: 0x78 Clock Frequency Detector Upper Boundary Register */
1433 __IO uint32_t CDLOWB; /* Offset: 0x7C Clock Frequency Detector Low Boundary Register */
1434
1435} CLK_T;
1436
1437
1438
1444#define CLK_PWRCTL_HXTEN_Pos (0)
1445#define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos)
1447#define CLK_PWRCTL_LXTEN_Pos (1)
1448#define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos)
1450#define CLK_PWRCTL_HIRCEN_Pos (2)
1451#define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos)
1453#define CLK_PWRCTL_LIRCEN_Pos (3)
1454#define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos)
1456#define CLK_PWRCTL_PDWKDLY_Pos (4)
1457#define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos)
1459#define CLK_PWRCTL_PDWKIEN_Pos (5)
1460#define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos)
1462#define CLK_PWRCTL_PDWKIF_Pos (6)
1463#define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos)
1465#define CLK_PWRCTL_PDEN_Pos (7)
1466#define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos)
1468#define CLK_PWRCTL_PDWTCPU_Pos (8)
1469#define CLK_PWRCTL_PDWTCPU_Msk (0x1ul << CLK_PWRCTL_PDWTCPU_Pos)
1471#define CLK_PWRCTL_HXTGAIN_Pos (10)
1472#define CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos)
1474#define CLK_PWRCTL_HXTSELTYP_Pos (12)
1475#define CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos)
1477#define CLK_PWRCTL_HIRC48MEN_Pos (24)
1478#define CLK_PWRCTL_HIRC48MEN_Msk (0x1ul << CLK_PWRCTL_HIRC48MEN_Pos)
1480#define CLK_AHBCLK_PDMACKEN_Pos (1)
1481#define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos)
1483#define CLK_AHBCLK_ISPCKEN_Pos (2)
1484#define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos)
1486#define CLK_AHBCLK_EBICKEN_Pos (3)
1487#define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos)
1489#define CLK_AHBCLK_USBHCKEN_Pos (4)
1490#define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos)
1492#define CLK_AHBCLK_CRCCKEN_Pos (7)
1493#define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos)
1495#define CLK_AHBCLK_FMCIDLE_Pos (15)
1496#define CLK_AHBCLK_FMCIDLE_Msk (0x1ul << CLK_AHBCLK_FMCIDLE_Pos)
1498#define CLK_APBCLK0_WDTCKEN_Pos (0)
1499#define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos)
1501#define CLK_APBCLK0_RTCCKEN_Pos (1)
1502#define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos)
1504#define CLK_APBCLK0_TMR0CKEN_Pos (2)
1505#define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos)
1507#define CLK_APBCLK0_TMR1CKEN_Pos (3)
1508#define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos)
1510#define CLK_APBCLK0_TMR2CKEN_Pos (4)
1511#define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos)
1513#define CLK_APBCLK0_TMR3CKEN_Pos (5)
1514#define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos)
1516#define CLK_APBCLK0_CLKOCKEN_Pos (6)
1517#define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos)
1519#define CLK_APBCLK0_I2C0CKEN_Pos (8)
1520#define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos)
1522#define CLK_APBCLK0_I2C1CKEN_Pos (9)
1523#define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos)
1525#define CLK_APBCLK0_SPI0CKEN_Pos (12)
1526#define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos)
1528#define CLK_APBCLK0_SPI1CKEN_Pos (13)
1529#define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos)
1531#define CLK_APBCLK0_UART0CKEN_Pos (16)
1532#define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos)
1534#define CLK_APBCLK0_UART1CKEN_Pos (17)
1535#define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos)
1537#define CLK_APBCLK0_UART2CKEN_Pos (18)
1538#define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos)
1540#define CLK_APBCLK0_UART3CKEN_Pos (19)
1541#define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos)
1543#define CLK_APBCLK0_USBDCKEN_Pos (27)
1544#define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos)
1546#define CLK_APBCLK0_EADCCKEN_Pos (28)
1547#define CLK_APBCLK0_EADCCKEN_Msk (0x1ul << CLK_APBCLK0_EADCCKEN_Pos)
1549#define CLK_APBCLK1_SC0CKEN_Pos (0)
1550#define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos)
1552#define CLK_APBCLK1_PWM0CKEN_Pos (16)
1553#define CLK_APBCLK1_PWM0CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CKEN_Pos)
1555#define CLK_APBCLK1_PWM1CKEN_Pos (17)
1556#define CLK_APBCLK1_PWM1CKEN_Msk (0x1ul << CLK_APBCLK1_PWM1CKEN_Pos)
1558#define CLK_APBCLK1_TKCKEN_Pos (25)
1559#define CLK_APBCLK1_TKCKEN_Msk (0x1ul << CLK_APBCLK1_TKCKEN_Pos)
1561#define CLK_CLKSEL0_HCLKSEL_Pos (0)
1562#define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos)
1564#define CLK_CLKSEL0_STCLKSEL_Pos (3)
1565#define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos)
1567#define CLK_CLKSEL0_PCLK0SEL_Pos (6)
1568#define CLK_CLKSEL0_PCLK0SEL_Msk (0x1ul << CLK_CLKSEL0_PCLK0SEL_Pos)
1570#define CLK_CLKSEL0_PCLK1SEL_Pos (7)
1571#define CLK_CLKSEL0_PCLK1SEL_Msk (0x1ul << CLK_CLKSEL0_PCLK1SEL_Pos)
1573#define CLK_CLKSEL0_USBCKSEL_Pos (8)
1574#define CLK_CLKSEL0_USBCKSEL_Msk (0x1ul << CLK_CLKSEL0_USBCKSEL_Pos)
1576#define CLK_CLKSEL1_WDTSEL_Pos (0)
1577#define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos)
1579#define CLK_CLKSEL1_TMR0SEL_Pos (8)
1580#define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos)
1582#define CLK_CLKSEL1_TMR1SEL_Pos (12)
1583#define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos)
1585#define CLK_CLKSEL1_TMR2SEL_Pos (16)
1586#define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos)
1588#define CLK_CLKSEL1_TMR3SEL_Pos (20)
1589#define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos)
1591#define CLK_CLKSEL1_UARTSEL_Pos (24)
1592#define CLK_CLKSEL1_UARTSEL_Msk (0x3ul << CLK_CLKSEL1_UARTSEL_Pos)
1594#define CLK_CLKSEL1_CLKOSEL_Pos (28)
1595#define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos)
1597#define CLK_CLKSEL1_WWDTSEL_Pos (30)
1598#define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos)
1600#define CLK_CLKSEL2_PWM0SEL_Pos (0)
1601#define CLK_CLKSEL2_PWM0SEL_Msk (0x1ul << CLK_CLKSEL2_PWM0SEL_Pos)
1603#define CLK_CLKSEL2_PWM1SEL_Pos (1)
1604#define CLK_CLKSEL2_PWM1SEL_Msk (0x1ul << CLK_CLKSEL2_PWM1SEL_Pos)
1606#define CLK_CLKSEL2_SPI0SEL_Pos (2)
1607#define CLK_CLKSEL2_SPI0SEL_Msk (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos)
1609#define CLK_CLKSEL2_SPI1SEL_Pos (4)
1610#define CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos)
1612#define CLK_CLKSEL3_SC0SEL_Pos (0)
1613#define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos)
1615#define CLK_CLKSEL3_RTCSEL_Pos (8)
1616#define CLK_CLKSEL3_RTCSEL_Msk (0x1ul << CLK_CLKSEL3_RTCSEL_Pos)
1618#define CLK_CLKDIV0_HCLKDIV_Pos (0)
1619#define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos)
1621#define CLK_CLKDIV0_USBDIV_Pos (4)
1622#define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos)
1624#define CLK_CLKDIV0_UARTDIV_Pos (8)
1625#define CLK_CLKDIV0_UARTDIV_Msk (0xful << CLK_CLKDIV0_UARTDIV_Pos)
1627#define CLK_CLKDIV0_EADCDIV_Pos (16)
1628#define CLK_CLKDIV0_EADCDIV_Msk (0xfful << CLK_CLKDIV0_EADCDIV_Pos)
1630#define CLK_CLKDIV1_SC0DIV_Pos (0)
1631#define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos)
1633#define CLK_PLLCTL_FBDIV_Pos (0)
1634#define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos)
1636#define CLK_PLLCTL_INDIV_Pos (9)
1637#define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos)
1639#define CLK_PLLCTL_OUTDIV_Pos (14)
1640#define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos)
1642#define CLK_PLLCTL_PD_Pos (16)
1643#define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos)
1645#define CLK_PLLCTL_BP_Pos (17)
1646#define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos)
1648#define CLK_PLLCTL_OE_Pos (18)
1649#define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos)
1651#define CLK_PLLCTL_PLLSRC_Pos (19)
1652#define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos)
1654#define CLK_PLLCTL_STBSEL_Pos (23)
1655#define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos)
1657#define CLK_STATUS_HXTSTB_Pos (0)
1658#define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos)
1660#define CLK_STATUS_LXTSTB_Pos (1)
1661#define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos)
1663#define CLK_STATUS_PLLSTB_Pos (2)
1664#define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos)
1666#define CLK_STATUS_LIRCSTB_Pos (3)
1667#define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos)
1669#define CLK_STATUS_HIRCSTB_Pos (4)
1670#define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos)
1672#define CLK_STATUS_CLKSFAIL_Pos (7)
1673#define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos)
1675#define CLK_CLKOCTL_FREQSEL_Pos (0)
1676#define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos)
1678#define CLK_CLKOCTL_CLKOEN_Pos (4)
1679#define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos)
1681#define CLK_CLKOCTL_DIV1EN_Pos (5)
1682#define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos)
1684#define CLK_CLKOCTL_CLK1HZEN_Pos (6)
1685#define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos)
1687#define CLK_CLKDCTL_HXTFDEN_Pos (4)
1688#define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos)
1690#define CLK_CLKDCTL_HXTFIEN_Pos (5)
1691#define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos)
1693#define CLK_CLKDCTL_LXTFDEN_Pos (12)
1694#define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos)
1696#define CLK_CLKDCTL_LXTFIEN_Pos (13)
1697#define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos)
1699#define CLK_CLKDCTL_HXTFQDEN_Pos (16)
1700#define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos)
1702#define CLK_CLKDCTL_HXTFQIEN_Pos (17)
1703#define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos)
1705#define CLK_CLKDSTS_HXTFIF_Pos (0)
1706#define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos)
1708#define CLK_CLKDSTS_LXTFIF_Pos (1)
1709#define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos)
1711#define CLK_CLKDSTS_HXTFQIF_Pos (8)
1712#define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos)
1714#define CLK_CDUPB_UPERBD_Pos (0)
1715#define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos)
1717#define CLK_CDLOWB_LOWERBD_Pos (0)
1718#define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) /* CLK_CONST */ /* end of CLK register group */
1723
1724
1725
1726/*---------------------- Cyclic Redundancy Check Controller -------------------------*/
1733typedef struct
1734{
1735
1736
1737
1738
1808 __IO uint32_t CTL; /* Offset: 0x00 CRC Control Register */
1809 __IO uint32_t DAT; /* Offset: 0x04 CRC Write Data Register */
1810 __IO uint32_t SEED; /* Offset: 0x08 CRC Seed Register */
1811 __I uint32_t CHECKSUM; /* Offset: 0x0C CRC Checksum Register */
1812
1813} CRC_T;
1814
1815
1816
1822#define CRC_CTL_CRCEN_Pos (0)
1823#define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos)
1825#define CRC_CTL_CRCRST_Pos (1)
1826#define CRC_CTL_CRCRST_Msk (0x1ul << CRC_CTL_CRCRST_Pos)
1828#define CRC_CTL_DATREV_Pos (24)
1829#define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos)
1831#define CRC_CTL_CHKSREV_Pos (25)
1832#define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos)
1834#define CRC_CTL_DATFMT_Pos (26)
1835#define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos)
1837#define CRC_CTL_CHKSFMT_Pos (27)
1838#define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos)
1840#define CRC_CTL_DATLEN_Pos (28)
1841#define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos)
1843#define CRC_CTL_CRCMODE_Pos (30)
1844#define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos)
1846#define CRC_DAT_DATA_Pos (0)
1847#define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos)
1849#define CRC_SEED_SEED_Pos (0)
1850#define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos)
1852#define CRC_CHECKSUM_CHECKSUM_Pos (0)
1853#define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /* CRC_CONST */ /* end of CRC register group */
1857
1858
1859
1860/*---------------------- External Bus Interface Controller -------------------------*/
1867typedef struct
1868{
1869
1870
1871
1872
1996 __IO uint32_t CTL0; /* Offset: 0x00 External Bus Interface Bank0 Control Register */
1997 __IO uint32_t TCTL0; /* Offset: 0x04 External Bus Interface Bank0 Timing Control Register */
1998 __I uint32_t RESERVE0[2];
1999 __IO uint32_t CTL1; /* Offset: 0x10 External Bus Interface Bank1 Control Register */
2000 __IO uint32_t TCTL1; /* Offset: 0x14 External Bus Interface Bank1 Timing Control Register */
2001
2002} EBI_T;
2003
2004
2005
2011#define EBI_CTL0_EN_Pos (0)
2012#define EBI_CTL0_EN_Msk (0x1ul << EBI_CTL0_EN_Pos)
2014#define EBI_CTL0_DW16_Pos (1)
2015#define EBI_CTL0_DW16_Msk (0x1ul << EBI_CTL0_DW16_Pos)
2017#define EBI_CTL0_CSPOLINV_Pos (2)
2018#define EBI_CTL0_CSPOLINV_Msk (0x1ul << EBI_CTL0_CSPOLINV_Pos)
2020#define EBI_CTL0_MCLKDIV_Pos (8)
2021#define EBI_CTL0_MCLKDIV_Msk (0x7ul << EBI_CTL0_MCLKDIV_Pos)
2023#define EBI_CTL0_TALE_Pos (16)
2024#define EBI_CTL0_TALE_Msk (0x7ul << EBI_CTL0_TALE_Pos)
2026#define EBI_CTL0_WBUFEN_Pos (24)
2027#define EBI_CTL0_WBUFEN_Msk (0x1ul << EBI_CTL0_WBUFEN_Pos)
2029#define EBI_TCTL0_TACC_Pos (3)
2030#define EBI_TCTL0_TACC_Msk (0x1ful << EBI_TCTL0_TACC_Pos)
2032#define EBI_TCTL0_TAHD_Pos (8)
2033#define EBI_TCTL0_TAHD_Msk (0x7ul << EBI_TCTL0_TAHD_Pos)
2035#define EBI_TCTL0_W2X_Pos (12)
2036#define EBI_TCTL0_W2X_Msk (0xful << EBI_TCTL0_W2X_Pos)
2038#define EBI_TCTL0_RAHDOFF_Pos (22)
2039#define EBI_TCTL0_RAHDOFF_Msk (0x1ul << EBI_TCTL0_RAHDOFF_Pos)
2041#define EBI_TCTL0_WAHDOFF_Pos (23)
2042#define EBI_TCTL0_WAHDOFF_Msk (0x1ul << EBI_TCTL0_WAHDOFF_Pos)
2044#define EBI_TCTL0_R2R_Pos (24)
2045#define EBI_TCTL0_R2R_Msk (0xful << EBI_TCTL0_R2R_Pos)
2047#define EBI_CTL1_EN_Pos (0)
2048#define EBI_CTL1_EN_Msk (0x1ul << EBI_CTL1_EN_Pos)
2050#define EBI_CTL1_DW16_Pos (1)
2051#define EBI_CTL1_DW16_Msk (0x1ul << EBI_CTL1_DW16_Pos)
2053#define EBI_CTL1_CSPOLINV_Pos (2)
2054#define EBI_CTL1_CSPOLINV_Msk (0x1ul << EBI_CTL1_CSPOLINV_Pos)
2056#define EBI_CTL1_MCLKDIV_Pos (8)
2057#define EBI_CTL1_MCLKDIV_Msk (0x7ul << EBI_CTL1_MCLKDIV_Pos)
2059#define EBI_CTL1_TALE_Pos (16)
2060#define EBI_CTL1_TALE_Msk (0x7ul << EBI_CTL1_TALE_Pos)
2062#define EBI_CTL1_WBUFEN_Pos (24)
2063#define EBI_CTL1_WBUFEN_Msk (0x1ul << EBI_CTL1_WBUFEN_Pos)
2065#define EBI_TCTL1_TACC_Pos (3)
2066#define EBI_TCTL1_TACC_Msk (0x1ful << EBI_TCTL1_TACC_Pos)
2068#define EBI_TCTL1_TAHD_Pos (8)
2069#define EBI_TCTL1_TAHD_Msk (0x7ul << EBI_TCTL1_TAHD_Pos)
2071#define EBI_TCTL1_W2X_Pos (12)
2072#define EBI_TCTL1_W2X_Msk (0xful << EBI_TCTL1_W2X_Pos)
2074#define EBI_TCTL1_RAHDOFF_Pos (22)
2075#define EBI_TCTL1_RAHDOFF_Msk (0x1ul << EBI_TCTL1_RAHDOFF_Pos)
2077#define EBI_TCTL1_WAHDOFF_Pos (23)
2078#define EBI_TCTL1_WAHDOFF_Msk (0x1ul << EBI_TCTL1_WAHDOFF_Pos)
2080#define EBI_TCTL1_R2R_Pos (24)
2081#define EBI_TCTL1_R2R_Msk (0xful << EBI_TCTL1_R2R_Pos) /* EBI_CONST */ /* end of EBI register group */
2085
2086
2087/*---------------------- Flash Memory Controller -------------------------*/
2094typedef struct
2095{
2096
2097
2098
2099
2335 __IO uint32_t ISPCTL; /* Offset: 0x00 ISP Control Register */
2336 __IO uint32_t ISPADDR; /* Offset: 0x04 ISP Address Register */
2337 __IO uint32_t ISPDAT; /* Offset: 0x08 ISP Data Register */
2338 __IO uint32_t ISPCMD; /* Offset: 0x0C ISP CMD Register */
2339 __IO uint32_t ISPTRG; /* Offset: 0x10 ISP Trigger Control Register */
2340 __I uint32_t DFBA; /* Offset: 0x14 Data Flash Base Address */
2341 __IO uint32_t FTCTL; /* Offset: 0x18 Flash Access Time Control Register */
2342 __I uint32_t RESERVE0[9];
2343 __I uint32_t ISPSTS; /* Offset: 0x40 ISP Status Register */
2344 __I uint32_t RESERVE1[15];
2345 __IO uint32_t MPDAT0; /* Offset: 0x80 ISP Data0 Register */
2346 __IO uint32_t MPDAT1; /* Offset: 0x84 ISP Data1 Register */
2347 __IO uint32_t MPDAT2; /* Offset: 0x88 ISP Data2 Register */
2348 __IO uint32_t MPDAT3; /* Offset: 0x8C ISP Data3 Register */
2349 __I uint32_t RESERVE2[12];
2350 __I uint32_t MPSTS; /* Offset: 0xC0 ISP Multi-Program Status Register */
2351 __I uint32_t MPADDR; /* Offset: 0xC4 ISP Multi-Program Address Register */
2352
2353} FMC_T;
2354
2355
2356
2357
2363#define FMC_ISPCTL_ISPEN_Pos (0)
2364#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos)
2366#define FMC_ISPCTL_BS_Pos (1)
2367#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos)
2369#define FMC_ISPCTL_APUEN_Pos (3)
2370#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos)
2372#define FMC_ISPCTL_CFGUEN_Pos (4)
2373#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos)
2375#define FMC_ISPCTL_LDUEN_Pos (5)
2376#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos)
2378#define FMC_ISPCTL_ISPFF_Pos (6)
2379#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos)
2381#define FMC_ISPCTL_BL_Pos (16)
2382#define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos)
2384#define FMC_ISPADDR_ISPADDR_Pos (0)
2385#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos)
2387#define FMC_ISPDAT_ISPDAT_Pos (0)
2388#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos)
2390#define FMC_ISPCMD_CMD_Pos (0)
2391#define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos)
2393#define FMC_ISPTRG_ISPGO_Pos (0)
2394#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos)
2396#define FMC_DFBA_DFBA_Pos (0)
2397#define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos)
2399#define FMC_FTCTL_FOM_Pos (4)
2400#define FMC_FTCTL_FOM_Msk (0x7ul << FMC_FTCTL_FOM_Pos)
2402#define FMC_ISPSTS_ISPBUSY_Pos (0)
2403#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos)
2405#define FMC_ISPSTS_CBS_Pos (1)
2406#define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos)
2408#define FMC_ISPSTS_MBS_Pos (3)
2409#define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos)
2411#define FMC_ISPSTS_PGFF_Pos (5)
2412#define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos)
2414#define FMC_ISPSTS_ISPFF_Pos (6)
2415#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos)
2417#define FMC_ISPSTS_VECMAP_Pos (9)
2418#define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos)
2420#define FMC_MPDAT0_ISPDAT0_Pos (0)
2421#define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos)
2423#define FMC_MPDAT1_ISPDAT1_Pos (0)
2424#define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos)
2426#define FMC_MPDAT2_ISPDAT2_Pos (0)
2427#define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos)
2429#define FMC_MPDAT3_ISPDAT3_Pos (0)
2430#define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos)
2432#define FMC_MPSTS_MPBUSY_Pos (0)
2433#define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos)
2435#define FMC_MPSTS_PPGO_Pos (1)
2436#define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos)
2438#define FMC_MPSTS_ISPFF_Pos (2)
2439#define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos)
2441#define FMC_MPSTS_D0_Pos (4)
2442#define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos)
2444#define FMC_MPSTS_D1_Pos (5)
2445#define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos)
2447#define FMC_MPSTS_D2_Pos (6)
2448#define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos)
2450#define FMC_MPSTS_D3_Pos (7)
2451#define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos)
2453#define FMC_MPADDR_MPADDR_Pos (0)
2454#define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /* FMC_CONST */ /* end of FMC register group */
2458
2459
2460/*---------------------- General Purpose Input/Output Controller -------------------------*/
2467typedef struct
2468{
2469
2470
2471
2652 __IO uint32_t MODE; /* Offset: 0x00/0x40/0x80/0xC0/0x100/0x140 Port A-F I/O Mode Control */
2653 __IO uint32_t DINOFF; /* Offset: 0x04/0x44/0x84/0xC4/0x104/0x144 Port A-F Digital Input Path Disable Control */
2654 __IO uint32_t DOUT; /* Offset: 0x08/0x48/0x88/0xC8/0x108/0x148 Port A-F Data Output Value */
2655 __IO uint32_t DATMSK; /* Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C Port A-F Data Output Write Mask */
2656 __I uint32_t PIN; /* Offset: 0x10/0x50/0x90/0xD0/0x110/0x150 Port A-F Pin Value */
2657 __IO uint32_t DBEN; /* Offset: 0x14/0x54/0x94/0xD4/0x114/0x154 Port A-F De-Bounce Enable Control Register */
2658 __IO uint32_t INTTYPE; /* Offset: 0x18/0x58/0x98/0xD8/0x118/0x158 Port A-F Interrupt Trigger Type Control */
2659 __IO uint32_t INTEN; /* Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C Port A-F Interrupt Enable Control Register */
2660 __IO uint32_t INTSRC; /* Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160 Port A-F Interrupt Source Flag */
2661 __IO uint32_t SMTEN; /* Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164 Port A-F Input Schmitt Trigger Enable Register */
2662 __IO uint32_t SLEWCTL; /* Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168 Port A-F High Slew Rate Control Register */
2663 __IO uint32_t DRVCTL; /* Offset: 0x12C Port E High Drive Strength Control Register */
2664
2665} GPIO_T;
2666
2667
2668
2669
2670typedef struct
2671{
2672
2673
2674
2707 __IO uint32_t DBCTL; /* Offset: 0x440 Interrupt De-bounce Control Register */
2708
2709} GPIO_DBCTL_T;
2710
2711
2712
2713
2719#define GPIO_MODE_MODE0_Pos (0)
2720#define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos)
2722#define GPIO_MODE_MODE1_Pos (2)
2723#define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos)
2725#define GPIO_MODE_MODE2_Pos (4)
2726#define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos)
2728#define GPIO_MODE_MODE3_Pos (6)
2729#define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos)
2731#define GPIO_MODE_MODE4_Pos (8)
2732#define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos)
2734#define GPIO_MODE_MODE5_Pos (10)
2735#define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos)
2737#define GPIO_MODE_MODE6_Pos (12)
2738#define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos)
2740#define GPIO_MODE_MODE7_Pos (14)
2741#define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos)
2743#define GPIO_MODE_MODE8_Pos (16)
2744#define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos)
2746#define GPIO_MODE_MODE9_Pos (18)
2747#define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos)
2749#define GPIO_MODE_MODE10_Pos (20)
2750#define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos)
2752#define GPIO_MODE_MODE11_Pos (22)
2753#define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos)
2755#define GPIO_MODE_MODE12_Pos (24)
2756#define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos)
2758#define GPIO_MODE_MODE13_Pos (26)
2759#define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos)
2761#define GPIO_MODE_MODE14_Pos (28)
2762#define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos)
2764#define GPIO_MODE_MODE15_Pos (30)
2765#define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos)
2767#define GPIO_DINOFF_DINOFF0_Pos (16)
2768#define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos)
2770#define GPIO_DINOFF_DINOFF1_Pos (17)
2771#define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos)
2773#define GPIO_DINOFF_DINOFF2_Pos (18)
2774#define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos)
2776#define GPIO_DINOFF_DINOFF3_Pos (19)
2777#define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos)
2779#define GPIO_DINOFF_DINOFF4_Pos (20)
2780#define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos)
2782#define GPIO_DINOFF_DINOFF5_Pos (21)
2783#define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos)
2785#define GPIO_DINOFF_DINOFF6_Pos (22)
2786#define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos)
2788#define GPIO_DINOFF_DINOFF7_Pos (23)
2789#define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos)
2791#define GPIO_DINOFF_DINOFF8_Pos (24)
2792#define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos)
2794#define GPIO_DINOFF_DINOFF9_Pos (25)
2795#define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos)
2797#define GPIO_DINOFF_DINOFF10_Pos (26)
2798#define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos)
2800#define GPIO_DINOFF_DINOFF11_Pos (27)
2801#define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos)
2803#define GPIO_DINOFF_DINOFF12_Pos (28)
2804#define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos)
2806#define GPIO_DINOFF_DINOFF13_Pos (29)
2807#define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos)
2809#define GPIO_DINOFF_DINOFF14_Pos (30)
2810#define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos)
2812#define GPIO_DINOFF_DINOFF15_Pos (31)
2813#define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos)
2815#define GPIO_DOUT_DOUT0_Pos (0)
2816#define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos)
2818#define GPIO_DOUT_DOUT1_Pos (1)
2819#define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos)
2821#define GPIO_DOUT_DOUT2_Pos (2)
2822#define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos)
2824#define GPIO_DOUT_DOUT3_Pos (3)
2825#define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos)
2827#define GPIO_DOUT_DOUT4_Pos (4)
2828#define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos)
2830#define GPIO_DOUT_DOUT5_Pos (5)
2831#define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos)
2833#define GPIO_DOUT_DOUT6_Pos (6)
2834#define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos)
2836#define GPIO_DOUT_DOUT7_Pos (7)
2837#define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos)
2839#define GPIO_DOUT_DOUT8_Pos (8)
2840#define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos)
2842#define GPIO_DOUT_DOUT9_Pos (9)
2843#define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos)
2845#define GPIO_DOUT_DOUT10_Pos (10)
2846#define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos)
2848#define GPIO_DOUT_DOUT11_Pos (11)
2849#define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos)
2851#define GPIO_DOUT_DOUT12_Pos (12)
2852#define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos)
2854#define GPIO_DOUT_DOUT13_Pos (13)
2855#define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos)
2857#define GPIO_DOUT_DOUT14_Pos (14)
2858#define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos)
2860#define GPIO_DOUT_DOUT15_Pos (15)
2861#define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos)
2863#define GPIO_DATMSK_DMASK0_Pos (0)
2864#define GPIO_DATMSK_DMASK0_Msk (0x1ul << GPIO_DATMSK_DMASK0_Pos)
2866#define GPIO_DATMSK_DMASK1_Pos (1)
2867#define GPIO_DATMSK_DMASK1_Msk (0x1ul << GPIO_DATMSK_DMASK1_Pos)
2869#define GPIO_DATMSK_DMASK2_Pos (2)
2870#define GPIO_DATMSK_DMASK2_Msk (0x1ul << GPIO_DATMSK_DMASK2_Pos)
2872#define GPIO_DATMSK_DMASK3_Pos (3)
2873#define GPIO_DATMSK_DMASK3_Msk (0x1ul << GPIO_DATMSK_DMASK3_Pos)
2875#define GPIO_DATMSK_DMASK4_Pos (4)
2876#define GPIO_DATMSK_DMASK4_Msk (0x1ul << GPIO_DATMSK_DMASK4_Pos)
2878#define GPIO_DATMSK_DMASK5_Pos (5)
2879#define GPIO_DATMSK_DMASK5_Msk (0x1ul << GPIO_DATMSK_DMASK5_Pos)
2881#define GPIO_DATMSK_DMASK6_Pos (6)
2882#define GPIO_DATMSK_DMASK6_Msk (0x1ul << GPIO_DATMSK_DMASK6_Pos)
2884#define GPIO_DATMSK_DMASK7_Pos (7)
2885#define GPIO_DATMSK_DMASK7_Msk (0x1ul << GPIO_DATMSK_DMASK7_Pos)
2887#define GPIO_DATMSK_DMASK8_Pos (8)
2888#define GPIO_DATMSK_DMASK8_Msk (0x1ul << GPIO_DATMSK_DMASK8_Pos)
2890#define GPIO_DATMSK_DMASK9_Pos (9)
2891#define GPIO_DATMSK_DMASK9_Msk (0x1ul << GPIO_DATMSK_DMASK9_Pos)
2893#define GPIO_DATMSK_DMASK10_Pos (10)
2894#define GPIO_DATMSK_DMASK10_Msk (0x1ul << GPIO_DATMSK_DMASK10_Pos)
2896#define GPIO_DATMSK_DMASK11_Pos (11)
2897#define GPIO_DATMSK_DMASK11_Msk (0x1ul << GPIO_DATMSK_DMASK11_Pos)
2899#define GPIO_DATMSK_DMASK12_Pos (12)
2900#define GPIO_DATMSK_DMASK12_Msk (0x1ul << GPIO_DATMSK_DMASK12_Pos)
2902#define GPIO_DATMSK_DMASK13_Pos (13)
2903#define GPIO_DATMSK_DMASK13_Msk (0x1ul << GPIO_DATMSK_DMASK13_Pos)
2905#define GPIO_DATMSK_DMASK14_Pos (14)
2906#define GPIO_DATMSK_DMASK14_Msk (0x1ul << GPIO_DATMSK_DMASK14_Pos)
2908#define GPIO_DATMSK_DMASK15_Pos (15)
2909#define GPIO_DATMSK_DMASK15_Msk (0x1ul << GPIO_DATMSK_DMASK15_Pos)
2911#define GPIO_PIN_PIN0_Pos (0)
2912#define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos)
2914#define GPIO_PIN_PIN1_Pos (1)
2915#define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos)
2917#define GPIO_PIN_PIN2_Pos (2)
2918#define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos)
2920#define GPIO_PIN_PIN3_Pos (3)
2921#define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos)
2923#define GPIO_PIN_PIN4_Pos (4)
2924#define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos)
2926#define GPIO_PIN_PIN5_Pos (5)
2927#define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos)
2929#define GPIO_PIN_PIN6_Pos (6)
2930#define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos)
2932#define GPIO_PIN_PIN7_Pos (7)
2933#define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos)
2935#define GPIO_PIN_PIN8_Pos (8)
2936#define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos)
2938#define GPIO_PIN_PIN9_Pos (9)
2939#define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos)
2941#define GPIO_PIN_PIN10_Pos (10)
2942#define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos)
2944#define GPIO_PIN_PIN11_Pos (11)
2945#define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos)
2947#define GPIO_PIN_PIN12_Pos (12)
2948#define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos)
2950#define GPIO_PIN_PIN13_Pos (13)
2951#define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos)
2953#define GPIO_PIN_PIN14_Pos (14)
2954#define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos)
2956#define GPIO_PIN_PIN15_Pos (15)
2957#define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos)
2959#define GPIO_DBEN_DBEN0_Pos (0)
2960#define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos)
2962#define GPIO_DBEN_DBEN1_Pos (1)
2963#define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos)
2965#define GPIO_DBEN_DBEN2_Pos (2)
2966#define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos)
2968#define GPIO_DBEN_DBEN3_Pos (3)
2969#define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos)
2971#define GPIO_DBEN_DBEN4_Pos (4)
2972#define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos)
2974#define GPIO_DBEN_DBEN5_Pos (5)
2975#define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos)
2977#define GPIO_DBEN_DBEN6_Pos (6)
2978#define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos)
2980#define GPIO_DBEN_DBEN7_Pos (7)
2981#define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos)
2983#define GPIO_DBEN_DBEN8_Pos (8)
2984#define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos)
2986#define GPIO_DBEN_DBEN9_Pos (9)
2987#define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos)
2989#define GPIO_DBEN_DBEN10_Pos (10)
2990#define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos)
2992#define GPIO_DBEN_DBEN11_Pos (11)
2993#define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos)
2995#define GPIO_DBEN_DBEN12_Pos (12)
2996#define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos)
2998#define GPIO_DBEN_DBEN13_Pos (13)
2999#define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos)
3001#define GPIO_DBEN_DBEN14_Pos (14)
3002#define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos)
3004#define GPIO_DBEN_DBEN15_Pos (15)
3005#define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos)
3007#define GPIO_INTTYPE_TYPE0_Pos (0)
3008#define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos)
3010#define GPIO_INTTYPE_TYPE1_Pos (1)
3011#define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos)
3013#define GPIO_INTTYPE_TYPE2_Pos (2)
3014#define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos)
3016#define GPIO_INTTYPE_TYPE3_Pos (3)
3017#define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos)
3019#define GPIO_INTTYPE_TYPE4_Pos (4)
3020#define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos)
3022#define GPIO_INTTYPE_TYPE5_Pos (5)
3023#define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos)
3025#define GPIO_INTTYPE_TYPE6_Pos (6)
3026#define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos)
3028#define GPIO_INTTYPE_TYPE7_Pos (7)
3029#define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos)
3031#define GPIO_INTTYPE_TYPE8_Pos (8)
3032#define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos)
3034#define GPIO_INTTYPE_TYPE9_Pos (9)
3035#define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos)
3037#define GPIO_INTTYPE_TYPE10_Pos (10)
3038#define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos)
3040#define GPIO_INTTYPE_TYPE11_Pos (11)
3041#define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos)
3043#define GPIO_INTTYPE_TYPE12_Pos (12)
3044#define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos)
3046#define GPIO_INTTYPE_TYPE13_Pos (13)
3047#define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos)
3049#define GPIO_INTTYPE_TYPE14_Pos (14)
3050#define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos)
3052#define GPIO_INTTYPE_TYPE15_Pos (15)
3053#define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos)
3055#define GPIO_INTEN_FLIEN0_Pos (0)
3056#define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos)
3058#define GPIO_INTEN_FLIEN1_Pos (1)
3059#define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos)
3061#define GPIO_INTEN_FLIEN2_Pos (2)
3062#define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos)
3064#define GPIO_INTEN_FLIEN3_Pos (3)
3065#define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos)
3067#define GPIO_INTEN_FLIEN4_Pos (4)
3068#define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos)
3070#define GPIO_INTEN_FLIEN5_Pos (5)
3071#define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos)
3073#define GPIO_INTEN_FLIEN6_Pos (6)
3074#define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos)
3076#define GPIO_INTEN_FLIEN7_Pos (7)
3077#define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos)
3079#define GPIO_INTEN_FLIEN8_Pos (8)
3080#define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos)
3082#define GPIO_INTEN_FLIEN9_Pos (9)
3083#define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos)
3085#define GPIO_INTEN_FLIEN10_Pos (10)
3086#define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos)
3088#define GPIO_INTEN_FLIEN11_Pos (11)
3089#define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos)
3091#define GPIO_INTEN_FLIEN12_Pos (12)
3092#define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos)
3094#define GPIO_INTEN_FLIEN13_Pos (13)
3095#define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos)
3097#define GPIO_INTEN_FLIEN14_Pos (14)
3098#define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos)
3100#define GPIO_INTEN_FLIEN15_Pos (15)
3101#define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos)
3103#define GPIO_INTEN_RHIEN0_Pos (16)
3104#define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos)
3106#define GPIO_INTEN_RHIEN1_Pos (17)
3107#define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos)
3109#define GPIO_INTEN_RHIEN2_Pos (18)
3110#define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos)
3112#define GPIO_INTEN_RHIEN3_Pos (19)
3113#define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos)
3115#define GPIO_INTEN_RHIEN4_Pos (20)
3116#define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos)
3118#define GPIO_INTEN_RHIEN5_Pos (21)
3119#define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos)
3121#define GPIO_INTEN_RHIEN6_Pos (22)
3122#define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos)
3124#define GPIO_INTEN_RHIEN7_Pos (23)
3125#define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos)
3127#define GPIO_INTEN_RHIEN8_Pos (24)
3128#define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos)
3130#define GPIO_INTEN_RHIEN9_Pos (25)
3131#define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos)
3133#define GPIO_INTEN_RHIEN10_Pos (26)
3134#define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos)
3136#define GPIO_INTEN_RHIEN11_Pos (27)
3137#define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos)
3139#define GPIO_INTEN_RHIEN12_Pos (28)
3140#define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos)
3142#define GPIO_INTEN_RHIEN13_Pos (29)
3143#define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos)
3145#define GPIO_INTEN_RHIEN14_Pos (30)
3146#define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos)
3148#define GPIO_INTEN_RHIEN15_Pos (31)
3149#define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos)
3151#define GPIO_INTSRC_INTSRC0_Pos (0)
3152#define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos)
3154#define GPIO_INTSRC_INTSRC1_Pos (1)
3155#define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos)
3157#define GPIO_INTSRC_INTSRC2_Pos (2)
3158#define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos)
3160#define GPIO_INTSRC_INTSRC3_Pos (3)
3161#define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos)
3163#define GPIO_INTSRC_INTSRC4_Pos (4)
3164#define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos)
3166#define GPIO_INTSRC_INTSRC5_Pos (5)
3167#define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos)
3169#define GPIO_INTSRC_INTSRC6_Pos (6)
3170#define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos)
3172#define GPIO_INTSRC_INTSRC7_Pos (7)
3173#define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos)
3175#define GPIO_INTSRC_INTSRC8_Pos (8)
3176#define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos)
3178#define GPIO_INTSRC_INTSRC9_Pos (9)
3179#define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos)
3181#define GPIO_INTSRC_INTSRC10_Pos (10)
3182#define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos)
3184#define GPIO_INTSRC_INTSRC11_Pos (11)
3185#define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos)
3187#define GPIO_INTSRC_INTSRC12_Pos (12)
3188#define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos)
3190#define GPIO_INTSRC_INTSRC13_Pos (13)
3191#define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos)
3193#define GPIO_INTSRC_INTSRC14_Pos (14)
3194#define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos)
3196#define GPIO_INTSRC_INTSRC15_Pos (15)
3197#define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos)
3199#define GPIO_SMTEN_SMTEN0_Pos (0)
3200#define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos)
3202#define GPIO_SMTEN_SMTEN1_Pos (1)
3203#define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos)
3205#define GPIO_SMTEN_SMTEN2_Pos (2)
3206#define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos)
3208#define GPIO_SMTEN_SMTEN3_Pos (3)
3209#define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos)
3211#define GPIO_SMTEN_SMTEN4_Pos (4)
3212#define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos)
3214#define GPIO_SMTEN_SMTEN5_Pos (5)
3215#define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos)
3217#define GPIO_SMTEN_SMTEN6_Pos (6)
3218#define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos)
3220#define GPIO_SMTEN_SMTEN7_Pos (7)
3221#define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos)
3223#define GPIO_SMTEN_SMTEN8_Pos (8)
3224#define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos)
3226#define GPIO_SMTEN_SMTEN9_Pos (9)
3227#define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos)
3229#define GPIO_SMTEN_SMTEN10_Pos (10)
3230#define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos)
3232#define GPIO_SMTEN_SMTEN11_Pos (11)
3233#define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos)
3235#define GPIO_SMTEN_SMTEN12_Pos (12)
3236#define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos)
3238#define GPIO_SMTEN_SMTEN13_Pos (13)
3239#define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos)
3241#define GPIO_SMTEN_SMTEN14_Pos (14)
3242#define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos)
3244#define GPIO_SMTEN_SMTEN15_Pos (15)
3245#define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos)
3247#define GPIO_SLEWCTL_HSREN0_Pos (0)
3248#define GPIO_SLEWCTL_HSREN0_Msk (0x1ul << GPIO_SLEWCTL_HSREN0_Pos)
3250#define GPIO_SLEWCTL_HSREN1_Pos (1)
3251#define GPIO_SLEWCTL_HSREN1_Msk (0x1ul << GPIO_SLEWCTL_HSREN1_Pos)
3253#define GPIO_SLEWCTL_HSREN2_Pos (2)
3254#define GPIO_SLEWCTL_HSREN2_Msk (0x1ul << GPIO_SLEWCTL_HSREN2_Pos)
3256#define GPIO_SLEWCTL_HSREN3_Pos (3)
3257#define GPIO_SLEWCTL_HSREN3_Msk (0x1ul << GPIO_SLEWCTL_HSREN3_Pos)
3259#define GPIO_SLEWCTL_HSREN4_Pos (4)
3260#define GPIO_SLEWCTL_HSREN4_Msk (0x1ul << GPIO_SLEWCTL_HSREN4_Pos)
3262#define GPIO_SLEWCTL_HSREN5_Pos (5)
3263#define GPIO_SLEWCTL_HSREN5_Msk (0x1ul << GPIO_SLEWCTL_HSREN5_Pos)
3265#define GPIO_SLEWCTL_HSREN6_Pos (6)
3266#define GPIO_SLEWCTL_HSREN6_Msk (0x1ul << GPIO_SLEWCTL_HSREN6_Pos)
3268#define GPIO_SLEWCTL_HSREN7_Pos (7)
3269#define GPIO_SLEWCTL_HSREN7_Msk (0x1ul << GPIO_SLEWCTL_HSREN7_Pos)
3271#define GPIO_SLEWCTL_HSREN8_Pos (8)
3272#define GPIO_SLEWCTL_HSREN8_Msk (0x1ul << GPIO_SLEWCTL_HSREN8_Pos)
3274#define GPIO_SLEWCTL_HSREN9_Pos (9)
3275#define GPIO_SLEWCTL_HSREN9_Msk (0x1ul << GPIO_SLEWCTL_HSREN9_Pos)
3277#define GPIO_SLEWCTL_HSREN10_Pos (10)
3278#define GPIO_SLEWCTL_HSREN10_Msk (0x1ul << GPIO_SLEWCTL_HSREN10_Pos)
3280#define GPIO_SLEWCTL_HSREN11_Pos (11)
3281#define GPIO_SLEWCTL_HSREN11_Msk (0x1ul << GPIO_SLEWCTL_HSREN11_Pos)
3283#define GPIO_SLEWCTL_HSREN12_Pos (12)
3284#define GPIO_SLEWCTL_HSREN12_Msk (0x1ul << GPIO_SLEWCTL_HSREN12_Pos)
3286#define GPIO_SLEWCTL_HSREN13_Pos (13)
3287#define GPIO_SLEWCTL_HSREN13_Msk (0x1ul << GPIO_SLEWCTL_HSREN13_Pos)
3289#define GPIO_SLEWCTL_HSREN14_Pos (14)
3290#define GPIO_SLEWCTL_HSREN14_Msk (0x1ul << GPIO_SLEWCTL_HSREN14_Pos)
3292#define GPIO_SLEWCTL_HSREN15_Pos (15)
3293#define GPIO_SLEWCTL_HSREN15_Msk (0x1ul << GPIO_SLEWCTL_HSREN15_Pos)
3295#define GPIO_DRVCTL_HDRVEN8_Pos (8)
3296#define GPIO_DRVCTL_HDRVEN8_Msk (0x1ul << GPIO_DRVCTL_HDRVEN8_Pos)
3298#define GPIO_DRVCTL_HDRVEN9_Pos (9)
3299#define GPIO_DRVCTL_HDRVEN9_Msk (0x1ul << GPIO_DRVCTL_HDRVEN9_Pos)
3301#define GPIO_DRVCTL_HDRVEN10_Pos (10)
3302#define GPIO_DRVCTL_HDRVEN10_Msk (0x1ul << GPIO_DRVCTL_HDRVEN10_Pos)
3304#define GPIO_DRVCTL_HDRVEN11_Pos (11)
3305#define GPIO_DRVCTL_HDRVEN11_Msk (0x1ul << GPIO_DRVCTL_HDRVEN11_Pos)
3307#define GPIO_DRVCTL_HDRVEN12_Pos (12)
3308#define GPIO_DRVCTL_HDRVEN12_Msk (0x1ul << GPIO_DRVCTL_HDRVEN12_Pos)
3310#define GPIO_DRVCTL_HDRVEN13_Pos (13)
3311#define GPIO_DRVCTL_HDRVEN13_Msk (0x1ul << GPIO_DRVCTL_HDRVEN13_Pos)
3313#define GPIO_DBCTL_DBCLKSEL_Pos (0)
3314#define GPIO_DBCTL_DBCLKSEL_Msk (0xFul << GPIO_DBCTL_DBCLKSEL_Pos)
3316#define GPIO_DBCTL_DBCLKSRC_Pos (4)
3317#define GPIO_DBCTL_DBCLKSRC_Msk (1ul << GPIO_DBCTL_DBCLKSRC_Pos)
3319#define GPIO_DBCTL_ICLKON_Pos (5)
3320#define GPIO_DBCTL_ICLKON_Msk (1ul << GPIO_DBCTL_ICLKON_Pos) /* GPIO_CONST */ /* end of GPIO register group */
3325
3326
3327/*---------------------- Inter-IC Bus Controller -------------------------*/
3334typedef struct
3335{
3336
3337
3338
3339
3701 __IO uint32_t CTL; /* Offset: 0x00 I2C Control Register */
3702 __IO uint32_t ADDR0; /* Offset: 0x04 I2C Slave Address Register0 */
3703 __IO uint32_t DAT; /* Offset: 0x08 I2C Data Register */
3704 __I uint32_t STATUS; /* Offset: 0x0C I2C Status Register */
3705 __IO uint32_t CLKDIV; /* Offset: 0x10 I2C Clock Divided Register */
3706 __IO uint32_t TOCTL; /* Offset: 0x14 I2C Time-out Control Register */
3707 __IO uint32_t ADDR1; /* Offset: 0x18 I2C Slave Address Register1 */
3708 __IO uint32_t ADDR2; /* Offset: 0x1C I2C Slave Address Register2 */
3709 __IO uint32_t ADDR3; /* Offset: 0x20 I2C Slave Address Register3 */
3710 __IO uint32_t ADDRMSK0; /* Offset: 0x24 I2C Slave Address Mask Register0 */
3711 __IO uint32_t ADDRMSK1; /* Offset: 0x28 I2C Slave Address Mask Register1 */
3712 __IO uint32_t ADDRMSK2; /* Offset: 0x2C I2C Slave Address Mask Register2 */
3713 __IO uint32_t ADDRMSK3; /* Offset: 0x30 I2C Slave Address Mask Register3 */
3714 __I uint32_t RESERVE0[2];
3715 __IO uint32_t WKCTL; /* Offset: 0x3C I2C Wake-up Control Register */
3716 __IO uint32_t WKSTS; /* Offset: 0x40 I2C Wake-up Status Register */
3717 __IO uint32_t BUSCTL; /* Offset: 0x44 I2C Bus Management Control Register */
3718 __IO uint32_t BUSTCTL; /* Offset: 0x48 I2C Bus Management Timer Control Register */
3719 __IO uint32_t BUSSTS; /* Offset: 0x4C I2C Bus Management Status Register */
3720 __IO uint32_t PKTSIZE; /* Offset: 0x50 I2C Packet Error Checking Byte Number Register */
3721 __I uint32_t PKTCRC; /* Offset: 0x54 I2C Packet Error Checking Byte Value Register */
3722 __IO uint32_t BUSTOUT; /* Offset: 0x58 I2C Bus Management Timer Register */
3723 __IO uint32_t CLKTOUT; /* Offset: 0x5C I2C Bus Management Clock Low Timer Register */
3724
3725} I2C_T;
3726
3727
3728
3734#define I2C_CTL_AA_Pos (2)
3735#define I2C_CTL_AA_Msk (0x1ul << I2C_CTL_AA_Pos)
3737#define I2C_CTL_SI_Pos (3)
3738#define I2C_CTL_SI_Msk (0x1ul << I2C_CTL_SI_Pos)
3740#define I2C_CTL_STO_Pos (4)
3741#define I2C_CTL_STO_Msk (0x1ul << I2C_CTL_STO_Pos)
3743#define I2C_CTL_STA_Pos (5)
3744#define I2C_CTL_STA_Msk (0x1ul << I2C_CTL_STA_Pos)
3746#define I2C_CTL_I2CEN_Pos (6)
3747#define I2C_CTL_I2CEN_Msk (0x1ul << I2C_CTL_I2CEN_Pos)
3749#define I2C_CTL_INTEN_Pos (7)
3750#define I2C_CTL_INTEN_Msk (0x1ul << I2C_CTL_INTEN_Pos)
3752#define I2C_ADDR0_GC_Pos (0)
3753#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos)
3755#define I2C_ADDR0_ADDR_Pos (1)
3756#define I2C_ADDR0_ADDR_Msk (0x7ful << I2C_ADDR0_ADDR_Pos)
3758#define I2C_DAT_DAT_Pos (0)
3759#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos)
3761#define I2C_STATUS_STATUS_Pos (0)
3762#define I2C_STATUS_STATUS_Msk (0xfful << I2C_STATUS_STATUS_Pos)
3764#define I2C_CLKDIV_DIVIDER_Pos (0)
3765#define I2C_CLKDIV_DIVIDER_Msk (0xfful << I2C_CLKDIV_DIVIDER_Pos)
3767#define I2C_TOCTL_TOIF_Pos (0)
3768#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos)
3770#define I2C_TOCTL_TOCDIV4_Pos (1)
3771#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos)
3773#define I2C_TOCTL_TOCEN_Pos (2)
3774#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos)
3776#define I2C_ADDR1_GC_Pos (0)
3777#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos)
3779#define I2C_ADDR1_ADDR_Pos (1)
3780#define I2C_ADDR1_ADDR_Msk (0x7ful << I2C_ADDR1_ADDR_Pos)
3782#define I2C_ADDR2_GC_Pos (0)
3783#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos)
3785#define I2C_ADDR2_ADDR_Pos (1)
3786#define I2C_ADDR2_ADDR_Msk (0x7ful << I2C_ADDR2_ADDR_Pos)
3788#define I2C_ADDR3_GC_Pos (0)
3789#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos)
3791#define I2C_ADDR3_ADDR_Pos (1)
3792#define I2C_ADDR3_ADDR_Msk (0x7ful << I2C_ADDR3_ADDR_Pos)
3794#define I2C_ADDRMSK0_ADDRMSK_Pos (1)
3795#define I2C_ADDRMSK0_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK0_ADDRMSK_Pos)
3797#define I2C_ADDRMSK1_ADDRMSK_Pos (1)
3798#define I2C_ADDRMSK1_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK1_ADDRMSK_Pos)
3800#define I2C_ADDRMSK2_ADDRMSK_Pos (1)
3801#define I2C_ADDRMSK2_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK2_ADDRMSK_Pos)
3803#define I2C_ADDRMSK3_ADDRMSK_Pos (1)
3804#define I2C_ADDRMSK3_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK3_ADDRMSK_Pos)
3806#define I2C_WKCTL_WKEN_Pos (0)
3807#define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos)
3809#define I2C_WKSTS_WKIF_Pos (0)
3810#define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos)
3812#define I2C_BUSCTL_ACKMEN_Pos (0)
3813#define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos)
3815#define I2C_BUSCTL_PECEN_Pos (1)
3816#define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos)
3818#define I2C_BUSCTL_BMDEN_Pos (2)
3819#define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos)
3821#define I2C_BUSCTL_BMHEN_Pos (3)
3822#define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos)
3824#define I2C_BUSCTL_ALERTEN_Pos (4)
3825#define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos)
3827#define I2C_BUSCTL_SCTLOSTS_Pos (5)
3828#define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos)
3830#define I2C_BUSCTL_SCTLOEN_Pos (6)
3831#define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos)
3833#define I2C_BUSCTL_BUSEN_Pos (7)
3834#define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos)
3836#define I2C_BUSCTL_PECTXEN_Pos (8)
3837#define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos)
3839#define I2C_BUSCTL_TIDLE_Pos (9)
3840#define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos)
3842#define I2C_BUSCTL_PECCLR_Pos (10)
3843#define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos)
3845#define I2C_BUSCTL_ACKM9SI_Pos (11)
3846#define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos)
3848#define I2C_BUSTCTL_BUSTOEN_Pos (0)
3849#define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos)
3851#define I2C_BUSTCTL_CLKTOEN_Pos (1)
3852#define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos)
3854#define I2C_BUSTCTL_BUSTOIEN_Pos (2)
3855#define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos)
3857#define I2C_BUSTCTL_CLKTOIEN_Pos (3)
3858#define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos)
3860#define I2C_BUSTCTL_TORSTEN_Pos (4)
3861#define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos)
3863#define I2C_BUSTCTL_PECIEN_Pos (5)
3864#define I2C_BUSTCTL_PECIEN_Msk (0x1ul << I2C_BUSTCTL_PECIEN_Pos)
3866#define I2C_BUSSTS_BUSY_Pos (0)
3867#define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos)
3869#define I2C_BUSSTS_BCDONE_Pos (1)
3870#define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos)
3872#define I2C_BUSSTS_PECERR_Pos (2)
3873#define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos)
3875#define I2C_BUSSTS_ALERT_Pos (3)
3876#define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos)
3878#define I2C_BUSSTS_SCTLDIN_Pos (4)
3879#define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos)
3881#define I2C_BUSSTS_BUSTO_Pos (5)
3882#define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos)
3884#define I2C_BUSSTS_CLKTO_Pos (6)
3885#define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos)
3887#define I2C_PKTSIZE_PLDSIZE_Pos (0)
3888#define I2C_PKTSIZE_PLDSIZE_Msk (0xfful << I2C_PKTSIZE_PLDSIZE_Pos)
3890#define I2C_PKTCRC_PECCRC_Pos (0)
3891#define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos)
3893#define I2C_BUSTOUT_BUSTO_Pos (0)
3894#define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos)
3896#define I2C_CLKTOUT_CLKTO_Pos (0)
3897#define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) /* I2C_CONST */ /* end of I2C register group */
3902
3903
3904/*---------------------- Peripheral Direct Memory Access Controller -------------------------*/
3911typedef struct
3912{
3913
3914
3992 __IO uint32_t CTL; /* Offset: 0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70/0x80/0x90/0xA0/0xB0 Descriptor Table Control Register of PDMA Channel 0~11 */
3993 __IO uint32_t SA; /* Offset: 0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74/0x84/0x94/0xA4/0xB4 Source Address Register of PDMA Channel 0~11 */
3994 __IO uint32_t DA; /* Offset: 0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78/0x88/0x98/0xA8/0xB8 Destination Address Register of PDMA Channel 0~11 */
3995 __IO uint32_t NEXT; /* Offset: 0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C/0x8C/0x9C/0xAC/0xBC First Scatter-Gather Descriptor Table Offset Address of PDMA Channel 0~11 */
3996
3997} DSCT_T;
3998
3999
4000
4001
4002typedef struct
4003{
4004
4005
4322 DSCT_T DSCT[12]; /* Offset: 0x0000 ~ 0x00BC DMA Embedded Description Table 0~11 */
4323 __I uint32_t CURSCAT[12];
4324 __I uint32_t RESERVE0[196]; /* Offset: 0xC0 ~ 0xEC Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~11 */
4325 __IO uint32_t CHCTL; /* Offset: 0x400 PDMA Channel Control Register */
4326 __O uint32_t STOP; /* Offset: 0x404 PDMA Transfer Stop Control Register */
4327 __O uint32_t SWREQ; /* Offset: 0x408 PDMA Software Request Register */
4328 __I uint32_t TRGSTS; /* Offset: 0x40C PDMA Channel Request Status Register */
4329 __IO uint32_t PRISET; /* Offset: 0x410 PDMA Fixed Priority Setting Register */
4330 __O uint32_t PRICLR; /* Offset: 0x414 PDMA Fixed Priority Clear Register */
4331 __IO uint32_t INTEN; /* Offset: 0x418 PDMA Interrupt Enable Register */
4332 __IO uint32_t INTSTS; /* Offset: 0x41C PDMA Interrupt Status Register */
4333 __IO uint32_t ABTSTS; /* Offset: 0x420 PDMA Channel Read/Write Target Abort Flag Register */
4334 __IO uint32_t TDSTS; /* Offset: 0x424 PDMA Channel Transfer Done Flag Register */
4335 __IO uint32_t SCATSTS; /* Offset: 0x428 PDMA Scatter-Gather Table Empty Status Register */
4336 __I uint32_t TACTSTS;
4337 __I uint32_t RESERVE1[1]; /* Offset: 0x42C PDMA Transfer Active Flag Register */
4338 __IO uint32_t TOUTEN; /* Offset: 0x434 PDMA Time-out Enable register */
4339 __IO uint32_t TOUTIEN; /* Offset: 0x438 PDMA Time-out Interrupt Enable register */
4340 __IO uint32_t SCATBA; /* Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register */
4341 __IO uint32_t TOC0_1; /* Offset: 0x440 PDMA Time-out Counter Ch1 and Ch0 Register */
4342 __IO uint32_t TOC2_3; /* Offset: 0x444 PDMA Time-out Counter Ch3 and Ch2 Register */
4343 __IO uint32_t TOC4_5; /* Offset: 0x448 PDMA Time-out Counter Ch5 and Ch4 Register */
4344 __IO uint32_t TOC6_7;
4345 __I uint32_t RESERVE2[12]; /* Offset: 0x44C PDMA Time-out Counter Ch7 and Ch6 Register */
4346 __IO uint32_t REQSEL0_3; /* Offset: 0x480 PDMA Request Source Select Register 0 */
4347 __IO uint32_t REQSEL4_7; /* Offset: 0x484 PDMA Request Source Select Register 1 */
4348 __IO uint32_t REQSEL8_11; /* Offset: 0x484 PDMA Request Source Select Register 2 */
4349
4350} PDMA_T;
4351
4352
4353
4359#define PDMA_DSCT_CTL_OPMODE_Pos (0)
4360#define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos)
4362#define PDMA_DSCT_CTL_TXTYPE_Pos (2)
4363#define PDMA_DSCT_CTL_TXTYPE_Msk (1ul << PDMA_DSCT_CTL_TXTYPE_Pos)
4365#define PDMA_DSCT_CTL_BURSIZE_Pos (4)
4366#define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos)
4368#define PDMA_DSCT_CTL_TBINTDIS_Pos (7)
4369#define PDMA_DSCT_CTL_TBINTDIS_Msk (1ul << PDMA_DSCT_CTL_TBINTDIS_Pos)
4371#define PDMA_DSCT_CTL_SAINC_Pos (8)
4372#define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos)
4374#define PDMA_DSCT_CTL_DAINC_Pos (10)
4375#define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos)
4377#define PDMA_DSCT_CTL_TXWIDTH_Pos (12)
4378#define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos)
4380#define PDMA_DSCT_CTL_TXCNT_Pos (16)
4381#define PDMA_DSCT_CTL_TXCNT_Msk (0x3FFFul << PDMA_DSCT_CTL_TXCNT_Pos)
4383#define PDMA_DSCT_SA_SA_Pos (0)
4384#define PDMA_DSCT_SA_SA_Msk (0xFFFFFFFFul << PDMA_DSCT_SA_SA_Pos)
4386#define PDMA_DSCT_DA_DA_Pos (0)
4387#define PDMA_DSCT_DA_DA_Msk (0xFFFFFFFFul << PDMA_DSCT_DA_DA_Pos)
4389#define PDMA_DSCT_NEXT_NEXT_Pos (0)
4390#define PDMA_DSCT_NEXT_NEXT_Msk (0xFFFFul << PDMA_DSCT_NEXT_NEXT_Pos)
4392#define PDMA_CURSCAT_CURADDR_Pos (0)
4393#define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos)
4395#define PDMA_CHCTL_CHENn_Pos (0)
4396#define PDMA_CHCTL_CHENn_Msk (0xffful << PDMA_CHCTL_CHENn_Pos)
4398#define PDMA_STOP_STOPn_Pos (0)
4399#define PDMA_STOP_STOPn_Msk (0xffful << PDMA_STOP_STOPn_Pos)
4401#define PDMA_SWREQ_SWREQn_Pos (0)
4402#define PDMA_SWREQ_SWREQn_Msk (0xffful << PDMA_SWREQ_SWREQn_Pos)
4404#define PDMA_TRGSTS_REQSTSn_Pos (0)
4405#define PDMA_TRGSTS_REQSTSn_Msk (0xffful << PDMA_TRGSTS_REQSTSn_Pos)
4407#define PDMA_PRISET_FPRISETn_Pos (0)
4408#define PDMA_PRISET_FPRISETn_Msk (0xffful << PDMA_PRISET_FPRISETn_Pos)
4410#define PDMA_PRICLR_FPRICLRn_Pos (0)
4411#define PDMA_PRICLR_FPRICLRn_Msk (0xffful << PDMA_PRICLR_FPRICLRn_Pos)
4413#define PDMA_INTEN_INTENn_Pos (0)
4414#define PDMA_INTEN_INTENn_Msk (0xffful << PDMA_INTEN_INTENn_Pos)
4416#define PDMA_INTSTS_ABTIF_Pos (0)
4417#define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos)
4419#define PDMA_INTSTS_TDIF_Pos (1)
4420#define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos)
4422#define PDMA_INTSTS_TEIF_Pos (2)
4423#define PDMA_INTSTS_TEIF_Msk (0x1ul << PDMA_INTSTS_TEIF_Pos)
4425#define PDMA_INTSTS_REQTOFn_Pos (8)
4426#define PDMA_INTSTS_REQTOFn_Msk (0xfful << PDMA_INTSTS_REQTOFn_Pos)
4428#define PDMA_ABTSTS_ABTIFn_Pos (0)
4429#define PDMA_ABTSTS_ABTIFn_Msk (0xffful << PDMA_ABTSTS_ABTIFn_Pos)
4431#define PDMA_TDSTS_TDIFn_Pos (0)
4432#define PDMA_TDSTS_TDIFn_Msk (0xffful << PDMA_TDSTS_TDIFn_Pos)
4434#define PDMA_SCATSTS_TEMPTYFn_Pos (0)
4435#define PDMA_SCATSTS_TEMPTYFn_Msk (0xffful << PDMA_SCATSTS_TEMPTYFn_Pos)
4437#define PDMA_TACTSTS_TXACTFn_Pos (0)
4438#define PDMA_TACTSTS_TXACTFn_Msk (0xffful << PDMA_TACTSTS_TXACTFn_Pos)
4440#define PDMA_TOUTEN_TOUTENn_Pos (0)
4441#define PDMA_TOUTEN_TOUTENn_Msk (0xfful << PDMA_TOUTEN_TOUTENn_Pos)
4443#define PDMA_TOUTIEN_TOUTIENn_Pos (0)
4444#define PDMA_TOUTIEN_TOUTIENn_Msk (0xfful << PDMA_TOUTIEN_TOUTIENn_Pos)
4446#define PDMA_SCATBA_SCATBA_Pos (16)
4447#define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos)
4449#define PDMA_TOC0_1_TOC0_Pos (0)
4450#define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos)
4452#define PDMA_TOC0_1_TOC1_Pos (16)
4453#define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos)
4455#define PDMA_TOC2_3_TOC2_Pos (0)
4456#define PDMA_TOC2_3_TOC2_Msk (0xfffful << PDMA_TOC2_3_TOC2_Pos)
4458#define PDMA_TOC2_3_TOC3_Pos (16)
4459#define PDMA_TOC2_3_TOC3_Msk (0xfffful << PDMA_TOC2_3_TOC3_Pos)
4461#define PDMA_TOC4_5_TOC4_Pos (0)
4462#define PDMA_TOC4_5_TOC4_Msk (0xfffful << PDMA_TOC4_5_TOC4_Pos)
4464#define PDMA_TOC4_5_TOC5_Pos (16)
4465#define PDMA_TOC4_5_TOC5_Msk (0xfffful << PDMA_TOC4_5_TOC5_Pos)
4467#define PDMA_TOC6_7_TOC6_Pos (0)
4468#define PDMA_TOC6_7_TOC6_Msk (0xfffful << PDMA_TOC6_7_TOC6_Pos)
4470#define PDMA_TOC6_7_TOC7_Pos (16)
4471#define PDMA_TOC6_7_TOC7_Msk (0xfffful << PDMA_TOC6_7_TOC7_Pos)
4473#define PDMA_REQSEL0_3_REQSRC0_Pos (0)
4474#define PDMA_REQSEL0_3_REQSRC0_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC0_Pos)
4476#define PDMA_REQSEL0_3_REQSRC1_Pos (8)
4477#define PDMA_REQSEL0_3_REQSRC1_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC1_Pos)
4479#define PDMA_REQSEL0_3_REQSRC2_Pos (16)
4480#define PDMA_REQSEL0_3_REQSRC2_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC2_Pos)
4482#define PDMA_REQSEL0_3_REQSRC3_Pos (24)
4483#define PDMA_REQSEL0_3_REQSRC3_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC3_Pos)
4485#define PDMA_REQSEL4_7_REQSRC4_Pos (0)
4486#define PDMA_REQSEL4_7_REQSRC4_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC4_Pos)
4488#define PDMA_REQSEL4_7_REQSRC5_Pos (8)
4489#define PDMA_REQSEL4_7_REQSRC5_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC5_Pos)
4491#define PDMA_REQSEL4_7_REQSRC6_Pos (16)
4492#define PDMA_REQSEL4_7_REQSRC6_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC6_Pos)
4494#define PDMA_REQSEL4_7_REQSRC7_Pos (24)
4495#define PDMA_REQSEL4_7_REQSRC7_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC7_Pos)
4497#define PDMA_REQSEL8_11_REQSRC8_Pos (0)
4498#define PDMA_REQSEL8_11_REQSRC8_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC8_Pos)
4500#define PDMA_REQSEL8_11_REQSRC9_Pos (8)
4501#define PDMA_REQSEL8_11_REQSRC9_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC9_Pos)
4503#define PDMA_REQSEL8_11_REQSRC10_Pos (16)
4504#define PDMA_REQSEL8_11_REQSRC10_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC10_Pos)
4506#define PDMA_REQSEL8_11_REQSRC11_Pos (24)
4507#define PDMA_REQSEL8_11_REQSRC11_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC11_Pos) /* PDMA_CONST */ /* end of PDMA register group */
4511
4512
4513/*---------------------- Pulse Width Modulation Controller -------------------------*/
4520typedef struct
4521{
4522
4523
5815 __IO uint32_t CTL0; /* Offset: 0x00 PWM Control Register 0 */
5816 __IO uint32_t CTL1; /* Offset: 0x04 PWM Control Register 1 */
5817 __IO uint32_t SYNC; /* Offset: 0x08 PWM Synchronization Register */
5818 __IO uint32_t SWSYNC; /* Offset: 0x0C PWM Software Control Synchronization Register */
5819 __IO uint32_t CLKSRC; /* Offset: 0x10 PWM Clock Source Register */
5820 __IO uint32_t CLKPSC0_1; /* Offset: 0x14 PWM Clock Pre-scale Register 0 */
5821 __IO uint32_t CLKPSC2_3; /* Offset: 0x18 PWM Clock Pre-scale Register 2 */
5822 __IO uint32_t CLKPSC4_5; /* Offset: 0x1C PWM Clock Pre-scale Register 4 */
5823 __IO uint32_t CNTEN; /* Offset: 0x20 PWM Counter Enable Register */
5824 __IO uint32_t CNTCLR; /* Offset: 0x24 PWM Clear Counter Register */
5825 __IO uint32_t LOAD; /* Offset: 0x28 PWM Load Register */
5826 __I uint32_t RESERVE0[1];
5827 __IO uint32_t PERIOD[6]; /* Offset: 0x30~0x44 PWM Period Register 0~5 */
5828 __I uint32_t RESERVE1[2];
5829 __IO uint32_t CMPDAT[6]; /* Offset: 0x50~0x64 PWM Comparator Register 0~5 */
5830 __I uint32_t RESERVE2[2];
5831 __IO uint32_t DTCTL0_1; /* Offset: 0x70 PWM Dead-Time Control Register 0 */
5832 __IO uint32_t DTCTL2_3; /* Offset: 0x74 PWM Dead-Time Control Register 2 */
5833 __IO uint32_t DTCTL4_5; /* Offset: 0x78 PWM Dead-Time Control Register 4 */
5834 __I uint32_t RESERVE3[1];
5835 __IO uint32_t PHS0_1; /* Offset: 0x80 PWM Counter Phase Register 0 */
5836 __IO uint32_t PHS2_3; /* Offset: 0x84 PWM Counter Phase Register 2 */
5837 __IO uint32_t PHS4_5; /* Offset: 0x88 PWM Counter Phase Register 4 */
5838 __I uint32_t RESERVE4[1];
5839 __I uint32_t CNT[6]; /* Offset: 0x90~0xA4 PWM Counter Register 0~5 */
5840 __I uint32_t RESERVE5[2];
5841 __IO uint32_t WGCTL0; /* Offset: 0xB0 PWM Generation Register 0 */
5842 __IO uint32_t WGCTL1; /* Offset: 0xB4 PWM Generation Register 1 */
5843 __IO uint32_t MSKEN; /* Offset: 0xB8 PWM Mask Enable Register */
5844 __IO uint32_t MSK; /* Offset: 0xBC PWM Mask Data Register */
5845 __IO uint32_t BNF; /* Offset: 0xC0 PWM Brake Noise Filter Register */
5846 __IO uint32_t FAILBRK; /* Offset: 0xC4 PWM System Fail Brake Control Register */
5847 __IO uint32_t BRKCTL0_1; /* Offset: 0xC8 PWM Brake Edge Detect Control Register 0 */
5848 __IO uint32_t BRKCTL2_3; /* Offset: 0xCC PWM Brake Edge Detect Control Register 2 */
5849 __IO uint32_t BRKCTL4_5; /* Offset: 0xD0 PWM Brake Edge Detect Control Register 4 */
5850 __IO uint32_t POLCTL; /* Offset: 0xD4 PWM Pin Polar Inverse Register */
5851 __IO uint32_t POEN; /* Offset: 0xD8 PWM Output Enable Register */
5852 __O uint32_t SWBRK; /* Offset: 0xDC PWM Software Brake Control Register */
5853 __IO uint32_t INTEN0; /* Offset: 0xE0 PWM Interrupt Enable Register 0 */
5854 __IO uint32_t INTEN1; /* Offset: 0xE4 PWM Interrupt Enable Register 1 */
5855 __IO uint32_t INTSTS0; /* Offset: 0xE8 PWM Interrupt Flag Register 0 */
5856 __IO uint32_t INTSTS1; /* Offset: 0xEC PWM Interrupt Flag Register 1 */
5857 __IO uint32_t IFA; /* Offset: 0xF0 PWM Interrupt Flag Accumulator Register */
5858 __IO uint32_t RESERVE6[1];
5859 __IO uint32_t EADCTS0; /* Offset: 0xF8 PWM Trigger EADC Source Select Register 0 */
5860 __IO uint32_t EADCTS1; /* Offset: 0xFC PWM Trigger EADC Source Select Register 1 */
5861 __IO uint32_t FTCMPDAT0_1; /* Offset: 0x100 PWM Free Trigger Compare Register 0 */
5862 __IO uint32_t FTCMPDAT2_3; /* Offset: 0x104 PWM Free Trigger Compare Register 2 */
5863 __IO uint32_t FTCMPDAT4_5; /* Offset: 0x108 PWM Free Trigger Compare Register 4 */
5864 __I uint32_t RESERVE7[1];
5865 __IO uint32_t SSCTL; /* Offset: 0x110 PWM Synchronous Start Control Register */
5866 __O uint32_t SSTRG; /* Offset: 0x114 PWM Synchronous Start Trigger Register */
5867 __I uint32_t RESERVE8[2];
5868 __IO uint32_t STATUS; /* Offset: 0x120 PWM Status Register */
5869 __I uint32_t RESERVE9[55];
5870 __IO uint32_t CAPINEN; /* Offset: 0x200 PWM Capture Input Enable Register */
5871 __IO uint32_t CAPCTL; /* Offset: 0x204 PWM Capture Control Register */
5872 __I uint32_t CAPSTS; /* Offset: 0x208 PWM Capture Status Register */
5873 __I uint32_t RCAPDAT0; /* Offset: 0x20C PWM Rising Capture Data Register 0 */
5874 __I uint32_t FCAPDAT0; /* Offset: 0x210 PWM Falling Capture Data Register 0 */
5875 __I uint32_t RCAPDAT1; /* Offset: 0x214 PWM Rising Capture Data Register 1 */
5876 __I uint32_t FCAPDAT1; /* Offset: 0x218 PWM Falling Capture Data Register 1 */
5877 __I uint32_t RCAPDAT2; /* Offset: 0x21C PWM Rising Capture Data Register 2 */
5878 __I uint32_t FCAPDAT2; /* Offset: 0x220 PWM Falling Capture Data Register 2 */
5879 __I uint32_t RCAPDAT3; /* Offset: 0x224 PWM Rising Capture Data Register 3 */
5880 __I uint32_t FCAPDAT3; /* Offset: 0x228 PWM Falling Capture Data Register 3 */
5881 __I uint32_t RCAPDAT4; /* Offset: 0x22C PWM Rising Capture Data Register 4 */
5882 __I uint32_t FCAPDAT4; /* Offset: 0x230 PWM Falling Capture Data Register 4 */
5883 __I uint32_t RCAPDAT5; /* Offset: 0x234 PWM Rising Capture Data Register 5 */
5884 __I uint32_t FCAPDAT5; /* Offset: 0x238 PWM Falling Capture Data Register 5 */
5885 __IO uint32_t PDMACTL; /* Offset: 0x23C PWM PDMA Control Register */
5886 __I uint32_t PDMACAP0_1; /* Offset: 0x240 PWM Capture Channel 01 PDMA Register */
5887 __I uint32_t PDMACAP2_3; /* Offset: 0x244 PWM Capture Channel 23 PDMA Register */
5888 __I uint32_t PDMACAP4_5; /* Offset: 0x248 PWM Capture Channel 45 PDMA Register */
5889 __I uint32_t RESERVE10[1];
5890 __IO uint32_t CAPIEN; /* Offset: 0x250 PWM Capture Interrupt Enable Register */
5891 __IO uint32_t CAPIF; /* Offset: 0x254 PWM Capture Interrupt Flag Register */
5892 __I uint32_t RESERVE11[43];
5893 __I uint32_t PBUF[6]; /* Offset: 0x304~0x318 PWM PERIOD0~5 Buffer */
5894 __I uint32_t CMPBUF[6]; /* Offset: 0x31C~0x330 PWM CMPDAT0~5 Buffer */
5895 __I uint32_t RESERVE12[3];
5896 __I uint32_t FTCBUF0_1; /* Offset: 0x340 PWM FTCMPDAT0_1 Buffer */
5897 __I uint32_t FTCBUF2_3; /* Offset: 0x344 PWM FTCMPDAT2_3 Buffer */
5898 __I uint32_t FTCBUF4_5; /* Offset: 0x348 PWM FTCMPDAT4_5 Buffer */
5899 __IO uint32_t FTCI; /* Offset: 0x34C PWM FTCMPDAT Indicator Register */
5900
5901} PWM_T;
5902
5903
5904
5910#define PWM_CTL0_CTRLDn_Pos (0)
5911#define PWM_CTL0_CTRLDn_Msk (0x3ful << PWM_CTL0_CTRLDn_Pos)
5913#define PWM_CTL0_CTRLD0_Pos (0)
5914#define PWM_CTL0_CTRLD0_Msk (0x1ul << PWM_CTL0_CTRLD0_Pos)
5916#define PWM_CTL0_CTRLD1_Pos (1)
5917#define PWM_CTL0_CTRLD1_Msk (0x1ul << PWM_CTL0_CTRLD1_Pos)
5919#define PWM_CTL0_CTRLD2_Pos (2)
5920#define PWM_CTL0_CTRLD2_Msk (0x1ul << PWM_CTL0_CTRLD2_Pos)
5922#define PWM_CTL0_CTRLD3_Pos (3)
5923#define PWM_CTL0_CTRLD3_Msk (0x1ul << PWM_CTL0_CTRLD3_Pos)
5925#define PWM_CTL0_CTRLD4_Pos (4)
5926#define PWM_CTL0_CTRLD4_Msk (0x1ul << PWM_CTL0_CTRLD4_Pos)
5928#define PWM_CTL0_CTRLD5_Pos (5)
5929#define PWM_CTL0_CTRLD5_Msk (0x1ul << PWM_CTL0_CTRLD5_Pos)
5931#define PWM_CTL0_WINLDENn_Pos (8)
5932#define PWM_CTL0_WINLDENn_Msk (0x3ful << PWM_CTL0_WINLDENn_Pos)
5934#define PWM_CTL0_WINLDEN0_Pos (8)
5935#define PWM_CTL0_WINLDEN0_Msk (0x1ul << PWM_CTL0_WINLDEN0_Pos)
5937#define PWM_CTL0_WINLDEN1_Pos (9)
5938#define PWM_CTL0_WINLDEN1_Msk (0x1ul << PWM_CTL0_WINLDEN1_Pos)
5940#define PWM_CTL0_WINLDEN2_Pos (10)
5941#define PWM_CTL0_WINLDEN2_Msk (0x1ul << PWM_CTL0_WINLDEN2_Pos)
5943#define PWM_CTL0_WINLDEN3_Pos (11)
5944#define PWM_CTL0_WINLDEN3_Msk (0x1ul << PWM_CTL0_WINLDEN3_Pos)
5946#define PWM_CTL0_WINLDEN4_Pos (12)
5947#define PWM_CTL0_WINLDEN4_Msk (0x1ul << PWM_CTL0_WINLDEN4_Pos)
5949#define PWM_CTL0_WINLDEN5_Pos (13)
5950#define PWM_CTL0_WINLDEN5_Msk (0x1ul << PWM_CTL0_WINLDEN5_Pos)
5952#define PWM_CTL0_IMMLDENn_Pos (16)
5953#define PWM_CTL0_IMMLDENn_Msk (0x3ful << PWM_CTL0_IMMLDENn_Pos)
5955#define PWM_CTL0_IMMLDEN0_Pos (16)
5956#define PWM_CTL0_IMMLDEN0_Msk (0x1ul << PWM_CTL0_IMMLDEN0_Pos)
5958#define PWM_CTL0_IMMLDEN1_Pos (17)
5959#define PWM_CTL0_IMMLDEN1_Msk (0x1ul << PWM_CTL0_IMMLDEN1_Pos)
5961#define PWM_CTL0_IMMLDEN2_Pos (18)
5962#define PWM_CTL0_IMMLDEN2_Msk (0x1ul << PWM_CTL0_IMMLDEN2_Pos)
5964#define PWM_CTL0_IMMLDEN3_Pos (19)
5965#define PWM_CTL0_IMMLDEN3_Msk (0x1ul << PWM_CTL0_IMMLDEN3_Pos)
5967#define PWM_CTL0_IMMLDEN4_Pos (20)
5968#define PWM_CTL0_IMMLDEN4_Msk (0x1ul << PWM_CTL0_IMMLDEN4_Pos)
5970#define PWM_CTL0_IMMLDEN5_Pos (21)
5971#define PWM_CTL0_IMMLDEN5_Msk (0x1ul << PWM_CTL0_IMMLDEN5_Pos)
5973#define PWM_CTL0_GROUPEN_Pos (24)
5974#define PWM_CTL0_GROUPEN_Msk (0x1ul << PWM_CTL0_GROUPEN_Pos)
5976#define PWM_CTL0_DBGHALT_Pos (30)
5977#define PWM_CTL0_DBGHALT_Msk (0x1ul << PWM_CTL0_DBGHALT_Pos)
5979#define PWM_CTL0_DBGTRIOFF_Pos (31)
5980#define PWM_CTL0_DBGTRIOFF_Msk (0x1ul << PWM_CTL0_DBGTRIOFF_Pos)
5982#define PWM_CTL1_CNTTYPEn_Pos (0)
5983#define PWM_CTL1_CNTTYPEn_Msk (0xffful << PWM_CTL1_CNTTYPEn_Pos)
5985#define PWM_CTL1_CNTTYPE0_Pos (0)
5986#define PWM_CTL1_CNTTYPE0_Msk (0x3ul << PWM_CTL1_CNTTYPE0_Pos)
5988#define PWM_CTL1_CNTTYPE1_Pos (2)
5989#define PWM_CTL1_CNTTYPE1_Msk (0x3ul << PWM_CTL1_CNTTYPE1_Pos)
5991#define PWM_CTL1_CNTTYPE2_Pos (4)
5992#define PWM_CTL1_CNTTYPE2_Msk (0x3ul << PWM_CTL1_CNTTYPE2_Pos)
5994#define PWM_CTL1_CNTTYPE3_Pos (6)
5995#define PWM_CTL1_CNTTYPE3_Msk (0x3ul << PWM_CTL1_CNTTYPE3_Pos)
5997#define PWM_CTL1_CNTTYPE4_Pos (8)
5998#define PWM_CTL1_CNTTYPE4_Msk (0x3ul << PWM_CTL1_CNTTYPE4_Pos)
6000#define PWM_CTL1_CNTTYPE5_Pos (10)
6001#define PWM_CTL1_CNTTYPE5_Msk (0x3ul << PWM_CTL1_CNTTYPE5_Pos)
6003#define PWM_CTL1_CNTMODEn_Pos (16)
6004#define PWM_CTL1_CNTMODEn_Msk (0x3ful << PWM_CTL1_CNTMODEn_Pos)
6006#define PWM_CTL1_CNTMODE0_Pos (16)
6007#define PWM_CTL1_CNTMODE0_Msk (0x1ul << PWM_CTL1_CNTMODE0_Pos)
6009#define PWM_CTL1_CNTMODE1_Pos (17)
6010#define PWM_CTL1_CNTMODE1_Msk (0x1ul << PWM_CTL1_CNTMODE1_Pos)
6012#define PWM_CTL1_CNTMODE2_Pos (18)
6013#define PWM_CTL1_CNTMODE2_Msk (0x1ul << PWM_CTL1_CNTMODE2_Pos)
6015#define PWM_CTL1_CNTMODE3_Pos (19)
6016#define PWM_CTL1_CNTMODE3_Msk (0x1ul << PWM_CTL1_CNTMODE3_Pos)
6018#define PWM_CTL1_CNTMODE4_Pos (20)
6019#define PWM_CTL1_CNTMODE4_Msk (0x1ul << PWM_CTL1_CNTMODE4_Pos)
6021#define PWM_CTL1_CNTMODE5_Pos (21)
6022#define PWM_CTL1_CNTMODE5_Msk (0x1ul << PWM_CTL1_CNTMODE5_Pos)
6024#define PWM_CTL1_OUTMODEn_Pos (24)
6025#define PWM_CTL1_OUTMODEn_Msk (0x7ul << PWM_CTL1_OUTMODEn_Pos)
6027#define PWM_CTL1_OUTMODE0_Pos (24)
6028#define PWM_CTL1_OUTMODE0_Msk (0x1ul << PWM_CTL1_OUTMODE0_Pos)
6030#define PWM_CTL1_OUTMODE2_Pos (25)
6031#define PWM_CTL1_OUTMODE2_Msk (0x1ul << PWM_CTL1_OUTMODE2_Pos)
6033#define PWM_CTL1_OUTMODE4_Pos (26)
6034#define PWM_CTL1_OUTMODE4_Msk (0x1ul << PWM_CTL1_OUTMODE4_Pos)
6036#define PWM_SYNC_PHSENn_Pos (0)
6037#define PWM_SYNC_PHSENn_Msk (0x7ul << PWM_SYNC_PHSENn_Pos)
6039#define PWM_SYNC_PHSEN0_Pos (0)
6040#define PWM_SYNC_PHSEN0_Msk (0x1ul << PWM_SYNC_PHSEN0_Pos)
6042#define PWM_SYNC_PHSEN2_Pos (1)
6043#define PWM_SYNC_PHSEN2_Msk (0x1ul << PWM_SYNC_PHSEN2_Pos)
6045#define PWM_SYNC_PHSEN4_Pos (2)
6046#define PWM_SYNC_PHSEN4_Msk (0x1ul << PWM_SYNC_PHSEN4_Pos)
6048#define PWM_SYNC_SINSRCn_Pos (8)
6049#define PWM_SYNC_SINSRCn_Msk (0x3ful << PWM_SYNC_SINSRCn_Pos)
6051#define PWM_SYNC_SINSRC0_Pos (8)
6052#define PWM_SYNC_SINSRC0_Msk (0x3ul << PWM_SYNC_SINSRC0_Pos)
6054#define PWM_SYNC_SINSRC2_Pos (10)
6055#define PWM_SYNC_SINSRC2_Msk (0x3ul << PWM_SYNC_SINSRC2_Pos)
6057#define PWM_SYNC_SINSRC4_Pos (12)
6058#define PWM_SYNC_SINSRC4_Msk (0x3ul << PWM_SYNC_SINSRC4_Pos)
6060#define PWM_SYNC_SNFLTEN_Pos (16)
6061#define PWM_SYNC_SNFLTEN_Msk (0x1ul << PWM_SYNC_SNFLTEN_Pos)
6063#define PWM_SYNC_SFLTCSEL_Pos (17)
6064#define PWM_SYNC_SFLTCSEL_Msk (0x7ul << PWM_SYNC_SFLTCSEL_Pos)
6066#define PWM_SYNC_SFLTCNT_Pos (20)
6067#define PWM_SYNC_SFLTCNT_Msk (0x7ul << PWM_SYNC_SFLTCNT_Pos)
6069#define PWM_SYNC_SINPINV_Pos (23)
6070#define PWM_SYNC_SINPINV_Msk (0x1ul << PWM_SYNC_SINPINV_Pos)
6072#define PWM_SYNC_PHSDIRn_Pos (24)
6073#define PWM_SYNC_PHSDIRn_Msk (0x7ul << PWM_SYNC_PHSDIRn_Pos)
6075#define PWM_SYNC_PHSDIR0_Pos (24)
6076#define PWM_SYNC_PHSDIR0_Msk (0x1ul << PWM_SYNC_PHSDIR0_Pos)
6078#define PWM_SYNC_PHSDIR2_Pos (25)
6079#define PWM_SYNC_PHSDIR2_Msk (0x1ul << PWM_SYNC_PHSDIR2_Pos)
6081#define PWM_SYNC_PHSDIR4_Pos (26)
6082#define PWM_SYNC_PHSDIR4_Msk (0x1ul << PWM_SYNC_PHSDIR4_Pos)
6084#define PWM_SWSYNC_SWSYNCn_Pos (0)
6085#define PWM_SWSYNC_SWSYNCn_Msk (0x7ul << PWM_SWSYNC_SWSYNCn_Pos)
6087#define PWM_SWSYNC_SWSYNC0_Pos (0)
6088#define PWM_SWSYNC_SWSYNC0_Msk (0x1ul << PWM_SWSYNC_SWSYNC0_Pos)
6090#define PWM_SWSYNC_SWSYNC2_Pos (1)
6091#define PWM_SWSYNC_SWSYNC2_Msk (0x1ul << PWM_SWSYNC_SWSYNC2_Pos)
6093#define PWM_SWSYNC_SWSYNC4_Pos (2)
6094#define PWM_SWSYNC_SWSYNC4_Msk (0x1ul << PWM_SWSYNC_SWSYNC4_Pos)
6096#define PWM_CLKSRC_ECLKSRC0_Pos (0)
6097#define PWM_CLKSRC_ECLKSRC0_Msk (0x7ul << PWM_CLKSRC_ECLKSRC0_Pos)
6099#define PWM_CLKSRC_ECLKSRC2_Pos (8)
6100#define PWM_CLKSRC_ECLKSRC2_Msk (0x7ul << PWM_CLKSRC_ECLKSRC2_Pos)
6102#define PWM_CLKSRC_ECLKSRC4_Pos (16)
6103#define PWM_CLKSRC_ECLKSRC4_Msk (0x7ul << PWM_CLKSRC_ECLKSRC4_Pos)
6105#define PWM_CLKPSC0_1_CLKPSC_Pos (0)
6106#define PWM_CLKPSC0_1_CLKPSC_Msk (0xffful << PWM_CLKPSC0_1_CLKPSC_Pos)
6108#define PWM_CLKPSC2_3_CLKPSC_Pos (0)
6109#define PWM_CLKPSC2_3_CLKPSC_Msk (0xffful << PWM_CLKPSC2_3_CLKPSC_Pos)
6111#define PWM_CLKPSC4_5_CLKPSC_Pos (0)
6112#define PWM_CLKPSC4_5_CLKPSC_Msk (0xffful << PWM_CLKPSC4_5_CLKPSC_Pos)
6114#define PWM_CNTEN_CNTENn_Pos (0)
6115#define PWM_CNTEN_CNTENn_Msk (0x3ful << PWM_CNTEN_CNTENn_Pos)
6117#define PWM_CNTEN_CNTEN0_Pos (0)
6118#define PWM_CNTEN_CNTEN0_Msk (0x1ul << PWM_CNTEN_CNTEN0_Pos)
6120#define PWM_CNTEN_CNTEN1_Pos (1)
6121#define PWM_CNTEN_CNTEN1_Msk (0x1ul << PWM_CNTEN_CNTEN1_Pos)
6123#define PWM_CNTEN_CNTEN2_Pos (2)
6124#define PWM_CNTEN_CNTEN2_Msk (0x1ul << PWM_CNTEN_CNTEN2_Pos)
6126#define PWM_CNTEN_CNTEN3_Pos (3)
6127#define PWM_CNTEN_CNTEN3_Msk (0x1ul << PWM_CNTEN_CNTEN3_Pos)
6129#define PWM_CNTEN_CNTEN4_Pos (4)
6130#define PWM_CNTEN_CNTEN4_Msk (0x1ul << PWM_CNTEN_CNTEN4_Pos)
6132#define PWM_CNTEN_CNTEN5_Pos (5)
6133#define PWM_CNTEN_CNTEN5_Msk (0x1ul << PWM_CNTEN_CNTEN5_Pos)
6135#define PWM_CNTCLR_CNTCLRn_Pos (0)
6136#define PWM_CNTCLR_CNTCLRn_Msk (0x3ful << PWM_CNTCLR_CNTCLRn_Pos)
6138#define PWM_CNTCLR_CNTCLR0_Pos (0)
6139#define PWM_CNTCLR_CNTCLR0_Msk (0x1ul << PWM_CNTCLR_CNTCLR0_Pos)
6141#define PWM_CNTCLR_CNTCLR1_Pos (1)
6142#define PWM_CNTCLR_CNTCLR1_Msk (0x1ul << PWM_CNTCLR_CNTCLR1_Pos)
6144#define PWM_CNTCLR_CNTCLR2_Pos (2)
6145#define PWM_CNTCLR_CNTCLR2_Msk (0x1ul << PWM_CNTCLR_CNTCLR2_Pos)
6147#define PWM_CNTCLR_CNTCLR3_Pos (3)
6148#define PWM_CNTCLR_CNTCLR3_Msk (0x1ul << PWM_CNTCLR_CNTCLR3_Pos)
6150#define PWM_CNTCLR_CNTCLR4_Pos (4)
6151#define PWM_CNTCLR_CNTCLR4_Msk (0x1ul << PWM_CNTCLR_CNTCLR4_Pos)
6153#define PWM_CNTCLR_CNTCLR5_Pos (5)
6154#define PWM_CNTCLR_CNTCLR5_Msk (0x1ul << PWM_CNTCLR_CNTCLR5_Pos)
6156#define PWM_LOAD_LOADn_Pos (0)
6157#define PWM_LOAD_LOADn_Msk (0x3ful << PWM_LOAD_LOADn_Pos)
6159#define PWM_LOAD_LOAD0_Pos (0)
6160#define PWM_LOAD_LOAD0_Msk (0x1ul << PWM_LOAD_LOAD0_Pos)
6162#define PWM_LOAD_LOAD1_Pos (1)
6163#define PWM_LOAD_LOAD1_Msk (0x1ul << PWM_LOAD_LOAD1_Pos)
6165#define PWM_LOAD_LOAD2_Pos (2)
6166#define PWM_LOAD_LOAD2_Msk (0x1ul << PWM_LOAD_LOAD2_Pos)
6168#define PWM_LOAD_LOAD3_Pos (3)
6169#define PWM_LOAD_LOAD3_Msk (0x1ul << PWM_LOAD_LOAD3_Pos)
6171#define PWM_LOAD_LOAD4_Pos (4)
6172#define PWM_LOAD_LOAD4_Msk (0x1ul << PWM_LOAD_LOAD4_Pos)
6174#define PWM_LOAD_LOAD5_Pos (5)
6175#define PWM_LOAD_LOAD5_Msk (0x1ul << PWM_LOAD_LOAD5_Pos)
6177#define PWM_PERIOD_PERIOD_Pos (0)
6178#define PWM_PERIOD_PERIOD_Msk (0xfffful << PWM_PERIOD_PERIOD_Pos)
6180#define PWM_CMPDAT_CMP_Pos (0)
6181#define PWM_CMPDAT_CMP_Msk (0xfffful << PWM_CMPDAT_CMP_Pos)
6183#define PWM_DTCTL0_1_DTCNT_Pos (0)
6184#define PWM_DTCTL0_1_DTCNT_Msk (0xffful << PWM_DTCTL0_1_DTCNT_Pos)
6186#define PWM_DTCTL0_1_DTEN_Pos (16)
6187#define PWM_DTCTL0_1_DTEN_Msk (0x1ul << PWM_DTCTL0_1_DTEN_Pos)
6189#define PWM_DTCTL0_1_DTCKSEL_Pos (24)
6190#define PWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << PWM_DTCTL0_1_DTCKSEL_Pos)
6192#define PWM_DTCTL2_3_DTCNT_Pos (0)
6193#define PWM_DTCTL2_3_DTCNT_Msk (0xffful << PWM_DTCTL2_3_DTCNT_Pos)
6195#define PWM_DTCTL2_3_DTEN_Pos (16)
6196#define PWM_DTCTL2_3_DTEN_Msk (0x1ul << PWM_DTCTL2_3_DTEN_Pos)
6198#define PWM_DTCTL2_3_DTCKSEL_Pos (24)
6199#define PWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << PWM_DTCTL2_3_DTCKSEL_Pos)
6201#define PWM_DTCTL4_5_DTCNT_Pos (0)
6202#define PWM_DTCTL4_5_DTCNT_Msk (0xffful << PWM_DTCTL4_5_DTCNT_Pos)
6204#define PWM_DTCTL4_5_DTEN_Pos (16)
6205#define PWM_DTCTL4_5_DTEN_Msk (0x1ul << PWM_DTCTL4_5_DTEN_Pos)
6207#define PWM_DTCTL4_5_DTCKSEL_Pos (24)
6208#define PWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << PWM_DTCTL4_5_DTCKSEL_Pos)
6210#define PWM_PHS0_1_PHS_Pos (0)
6211#define PWM_PHS0_1_PHS_Msk (0xfffful << PWM_PHS0_1_PHS_Pos)
6213#define PWM_PHS2_3_PHS_Pos (0)
6214#define PWM_PHS2_3_PHS_Msk (0xfffful << PWM_PHS2_3_PHS_Pos)
6216#define PWM_PHS4_5_PHS_Pos (0)
6217#define PWM_PHS4_5_PHS_Msk (0xfffful << PWM_PHS4_5_PHS_Pos)
6219#define PWM_CNT_CNT_Pos (0)
6220#define PWM_CNT_CNT_Msk (0xfffful << PWM_CNT_CNT_Pos)
6222#define PWM_CNT_DIRF_Pos (16)
6223#define PWM_CNT_DIRF_Msk (0x1ul << PWM_CNT_DIRF_Pos)
6225#define PWM_WGCTL0_ZPCTLn_Pos (0)
6226#define PWM_WGCTL0_ZPCTLn_Msk (0xffful << PWM_WGCTL0_ZPCTLn_Pos)
6228#define PWM_WGCTL0_ZPCTL0_Pos (0)
6229#define PWM_WGCTL0_ZPCTL0_Msk (0x3ul << PWM_WGCTL0_ZPCTL0_Pos)
6231#define PWM_WGCTL0_ZPCTL1_Pos (2)
6232#define PWM_WGCTL0_ZPCTL1_Msk (0x3ul << PWM_WGCTL0_ZPCTL1_Pos)
6234#define PWM_WGCTL0_ZPCTL2_Pos (4)
6235#define PWM_WGCTL0_ZPCTL2_Msk (0x3ul << PWM_WGCTL0_ZPCTL2_Pos)
6237#define PWM_WGCTL0_ZPCTL3_Pos (6)
6238#define PWM_WGCTL0_ZPCTL3_Msk (0x3ul << PWM_WGCTL0_ZPCTL3_Pos)
6240#define PWM_WGCTL0_ZPCTL4_Pos (8)
6241#define PWM_WGCTL0_ZPCTL4_Msk (0x3ul << PWM_WGCTL0_ZPCTL4_Pos)
6243#define PWM_WGCTL0_ZPCTL5_Pos (10)
6244#define PWM_WGCTL0_ZPCTL5_Msk (0x3ul << PWM_WGCTL0_ZPCTL5_Pos)
6246#define PWM_WGCTL0_PRDPCTLn_Pos (16)
6247#define PWM_WGCTL0_PRDPCTLn_Msk (0xffful << PWM_WGCTL0_PRDPCTLn_Pos)
6249#define PWM_WGCTL0_PRDPCTL0_Pos (16)
6250#define PWM_WGCTL0_PRDPCTL0_Msk (0x3ul << PWM_WGCTL0_PRDPCTL0_Pos)
6252#define PWM_WGCTL0_PRDPCTL1_Pos (18)
6253#define PWM_WGCTL0_PRDPCTL1_Msk (0x3ul << PWM_WGCTL0_PRDPCTL1_Pos)
6255#define PWM_WGCTL0_PRDPCTL2_Pos (20)
6256#define PWM_WGCTL0_PRDPCTL2_Msk (0x3ul << PWM_WGCTL0_PRDPCTL2_Pos)
6258#define PWM_WGCTL0_PRDPCTL3_Pos (22)
6259#define PWM_WGCTL0_PRDPCTL3_Msk (0x3ul << PWM_WGCTL0_PRDPCTL3_Pos)
6261#define PWM_WGCTL0_PRDPCTL4_Pos (24)
6262#define PWM_WGCTL0_PRDPCTL4_Msk (0x3ul << PWM_WGCTL0_PRDPCTL4_Pos)
6264#define PWM_WGCTL0_PRDPCTL5_Pos (26)
6265#define PWM_WGCTL0_PRDPCTL5_Msk (0x3ul << PWM_WGCTL0_PRDPCTL5_Pos)
6267#define PWM_WGCTL1_CMPUCTLn_Pos (0)
6268#define PWM_WGCTL1_CMPUCTLn_Msk (0xffful << PWM_WGCTL1_CMPUCTLn_Pos)
6270#define PWM_WGCTL1_CMPUCTL0_Pos (0)
6271#define PWM_WGCTL1_CMPUCTL0_Msk (0x3ul << PWM_WGCTL1_CMPUCTL0_Pos)
6273#define PWM_WGCTL1_CMPUCTL1_Pos (2)
6274#define PWM_WGCTL1_CMPUCTL1_Msk (0x3ul << PWM_WGCTL1_CMPUCTL1_Pos)
6276#define PWM_WGCTL1_CMPUCTL2_Pos (4)
6277#define PWM_WGCTL1_CMPUCTL2_Msk (0x3ul << PWM_WGCTL1_CMPUCTL2_Pos)
6279#define PWM_WGCTL1_CMPUCTL3_Pos (6)
6280#define PWM_WGCTL1_CMPUCTL3_Msk (0x3ul << PWM_WGCTL1_CMPUCTL3_Pos)
6282#define PWM_WGCTL1_CMPUCTL4_Pos (8)
6283#define PWM_WGCTL1_CMPUCTL4_Msk (0x3ul << PWM_WGCTL1_CMPUCTL4_Pos)
6285#define PWM_WGCTL1_CMPUCTL5_Pos (10)
6286#define PWM_WGCTL1_CMPUCTL5_Msk (0x3ul << PWM_WGCTL1_CMPUCTL5_Pos)
6288#define PWM_WGCTL1_CMPDCTLn_Pos (16)
6289#define PWM_WGCTL1_CMPDCTLn_Msk (0xffful << PWM_WGCTL1_CMPDCTLn_Pos)
6291#define PWM_WGCTL1_CMPDCTL0_Pos (16)
6292#define PWM_WGCTL1_CMPDCTL0_Msk (0x3ul << PWM_WGCTL1_CMPDCTL0_Pos)
6294#define PWM_WGCTL1_CMPDCTL1_Pos (18)
6295#define PWM_WGCTL1_CMPDCTL1_Msk (0x3ul << PWM_WGCTL1_CMPDCTL1_Pos)
6297#define PWM_WGCTL1_CMPDCTL2_Pos (20)
6298#define PWM_WGCTL1_CMPDCTL2_Msk (0x3ul << PWM_WGCTL1_CMPDCTL2_Pos)
6300#define PWM_WGCTL1_CMPDCTL3_Pos (22)
6301#define PWM_WGCTL1_CMPDCTL3_Msk (0x3ul << PWM_WGCTL1_CMPDCTL3_Pos)
6303#define PWM_WGCTL1_CMPDCTL4_Pos (24)
6304#define PWM_WGCTL1_CMPDCTL4_Msk (0x3ul << PWM_WGCTL1_CMPDCTL4_Pos)
6306#define PWM_WGCTL1_CMPDCTL5_Pos (26)
6307#define PWM_WGCTL1_CMPDCTL5_Msk (0x3ul << PWM_WGCTL1_CMPDCTL5_Pos)
6309#define PWM_MSKEN_MSKENn_Pos (0)
6310#define PWM_MSKEN_MSKENn_Msk (0x3ful << PWM_MSKEN_MSKENn_Pos)
6312#define PWM_MSKEN_MSKEN0_Pos (0)
6313#define PWM_MSKEN_MSKEN0_Msk (0x1ul << PWM_MSKEN_MSKEN0_Pos)
6315#define PWM_MSKEN_MSKEN1_Pos (1)
6316#define PWM_MSKEN_MSKEN1_Msk (0x1ul << PWM_MSKEN_MSKEN1_Pos)
6318#define PWM_MSKEN_MSKEN2_Pos (2)
6319#define PWM_MSKEN_MSKEN2_Msk (0x1ul << PWM_MSKEN_MSKEN2_Pos)
6321#define PWM_MSKEN_MSKEN3_Pos (3)
6322#define PWM_MSKEN_MSKEN3_Msk (0x1ul << PWM_MSKEN_MSKEN3_Pos)
6324#define PWM_MSKEN_MSKEN4_Pos (4)
6325#define PWM_MSKEN_MSKEN4_Msk (0x1ul << PWM_MSKEN_MSKEN4_Pos)
6327#define PWM_MSKEN_MSKEN5_Pos (5)
6328#define PWM_MSKEN_MSKEN5_Msk (0x1ul << PWM_MSKEN_MSKEN5_Pos)
6330#define PWM_MSK_MSKDATn_Pos (0)
6331#define PWM_MSK_MSKDATn_Msk (0x3ful << PWM_MSK_MSKDATn_Pos)
6333#define PWM_MSK_MSKDAT0_Pos (0)
6334#define PWM_MSK_MSKDAT0_Msk (0x1ul << PWM_MSK_MSKDAT0_Pos)
6336#define PWM_MSK_MSKDAT1_Pos (1)
6337#define PWM_MSK_MSKDAT1_Msk (0x1ul << PWM_MSK_MSKDAT1_Pos)
6339#define PWM_MSK_MSKDAT2_Pos (2)
6340#define PWM_MSK_MSKDAT2_Msk (0x1ul << PWM_MSK_MSKDAT2_Pos)
6342#define PWM_MSK_MSKDAT3_Pos (3)
6343#define PWM_MSK_MSKDAT3_Msk (0x1ul << PWM_MSK_MSKDAT3_Pos)
6345#define PWM_MSK_MSKDAT4_Pos (4)
6346#define PWM_MSK_MSKDAT4_Msk (0x1ul << PWM_MSK_MSKDAT4_Pos)
6348#define PWM_MSK_MSKDAT5_Pos (5)
6349#define PWM_MSK_MSKDAT5_Msk (0x1ul << PWM_MSK_MSKDAT5_Pos)
6351#define PWM_BNF_BRK0NFEN_Pos (0)
6352#define PWM_BNF_BRK0NFEN_Msk (0x1ul << PWM_BNF_BRK0NFEN_Pos)
6354#define PWM_BNF_BRK0NFSEL_Pos (1)
6355#define PWM_BNF_BRK0NFSEL_Msk (0x7ul << PWM_BNF_BRK0NFSEL_Pos)
6357#define PWM_BNF_BRK0FCNT_Pos (4)
6358#define PWM_BNF_BRK0FCNT_Msk (0x7ul << PWM_BNF_BRK0FCNT_Pos)
6360#define PWM_BNF_BRK0PINV_Pos (7)
6361#define PWM_BNF_BRK0PINV_Msk (0x1ul << PWM_BNF_BRK0PINV_Pos)
6363#define PWM_BNF_BRK1NFEN_Pos (8)
6364#define PWM_BNF_BRK1NFEN_Msk (0x1ul << PWM_BNF_BRK1NFEN_Pos)
6366#define PWM_BNF_BRK1NFSEL_Pos (9)
6367#define PWM_BNF_BRK1NFSEL_Msk (0x7ul << PWM_BNF_BRK1NFSEL_Pos)
6369#define PWM_BNF_BRK1FCNT_Pos (12)
6370#define PWM_BNF_BRK1FCNT_Msk (0x7ul << PWM_BNF_BRK1FCNT_Pos)
6372#define PWM_BNF_BRK1PINV_Pos (15)
6373#define PWM_BNF_BRK1PINV_Msk (0x1ul << PWM_BNF_BRK1PINV_Pos)
6375#define PWM_BNF_BK0SRC_Pos (16)
6376#define PWM_BNF_BK0SRC_Msk (0x1ul << PWM_BNF_BK0SRC_Pos)
6378#define PWM_BNF_BK1SRC_Pos (24)
6379#define PWM_BNF_BK1SRC_Msk (0x1ul << PWM_BNF_BK1SRC_Pos)
6381#define PWM_FAILBRK_CSSBRKEN_Pos (0)
6382#define PWM_FAILBRK_CSSBRKEN_Msk (0x1ul << PWM_FAILBRK_CSSBRKEN_Pos)
6384#define PWM_FAILBRK_BODBRKEN_Pos (1)
6385#define PWM_FAILBRK_BODBRKEN_Msk (0x1ul << PWM_FAILBRK_BODBRKEN_Pos)
6387#define PWM_FAILBRK_CORBRKEN_Pos (3)
6388#define PWM_FAILBRK_CORBRKEN_Msk (0x1ul << PWM_FAILBRK_CORBRKEN_Pos)
6390#define PWM_BRKCTL0_1_BRKP0EEN_Pos (4)
6391#define PWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP0EEN_Pos)
6393#define PWM_BRKCTL0_1_BRKP1EEN_Pos (5)
6394#define PWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP1EEN_Pos)
6396#define PWM_BRKCTL0_1_SYSEBEN_Pos (7)
6397#define PWM_BRKCTL0_1_SYSEBEN_Msk (0x1ul << PWM_BRKCTL0_1_SYSEBEN_Pos)
6399#define PWM_BRKCTL0_1_BRKP0LEN_Pos (12)
6400#define PWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP0LEN_Pos)
6402#define PWM_BRKCTL0_1_BRKP1LEN_Pos (13)
6403#define PWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP1LEN_Pos)
6405#define PWM_BRKCTL0_1_SYSLBEN_Pos (15)
6406#define PWM_BRKCTL0_1_SYSLBEN_Msk (0x1ul << PWM_BRKCTL0_1_SYSLBEN_Pos)
6408#define PWM_BRKCTL0_1_BRKAEVEN_Pos (16)
6409#define PWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL0_1_BRKAEVEN_Pos)
6411#define PWM_BRKCTL0_1_BRKAODD_Pos (18)
6412#define PWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << PWM_BRKCTL0_1_BRKAODD_Pos)
6414#define PWM_BRKCTL2_3_BRKP0EEN_Pos (4)
6415#define PWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP0EEN_Pos)
6417#define PWM_BRKCTL2_3_BRKP1EEN_Pos (5)
6418#define PWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP1EEN_Pos)
6420#define PWM_BRKCTL2_3_SYSEBEN_Pos (7)
6421#define PWM_BRKCTL2_3_SYSEBEN_Msk (0x1ul << PWM_BRKCTL2_3_SYSEBEN_Pos)
6423#define PWM_BRKCTL2_3_BRKP0LEN_Pos (12)
6424#define PWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP0LEN_Pos)
6426#define PWM_BRKCTL2_3_BRKP1LEN_Pos (13)
6427#define PWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP1LEN_Pos)
6429#define PWM_BRKCTL2_3_SYSLBEN_Pos (15)
6430#define PWM_BRKCTL2_3_SYSLBEN_Msk (0x1ul << PWM_BRKCTL2_3_SYSLBEN_Pos)
6432#define PWM_BRKCTL2_3_BRKAEVEN_Pos (16)
6433#define PWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL2_3_BRKAEVEN_Pos)
6435#define PWM_BRKCTL2_3_BRKAODD_Pos (18)
6436#define PWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << PWM_BRKCTL2_3_BRKAODD_Pos)
6438#define PWM_BRKCTL4_5_BRKP0EEN_Pos (4)
6439#define PWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP0EEN_Pos)
6441#define PWM_BRKCTL4_5_BRKP1EEN_Pos (5)
6442#define PWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP1EEN_Pos)
6444#define PWM_BRKCTL4_5_SYSEBEN_Pos (7)
6445#define PWM_BRKCTL4_5_SYSEBEN_Msk (0x1ul << PWM_BRKCTL4_5_SYSEBEN_Pos)
6447#define PWM_BRKCTL4_5_BRKP0LEN_Pos (12)
6448#define PWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP0LEN_Pos)
6450#define PWM_BRKCTL4_5_BRKP1LEN_Pos (13)
6451#define PWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP1LEN_Pos)
6453#define PWM_BRKCTL4_5_SYSLBEN_Pos (15)
6454#define PWM_BRKCTL4_5_SYSLBEN_Msk (0x1ul << PWM_BRKCTL4_5_SYSLBEN_Pos)
6456#define PWM_BRKCTL4_5_BRKAEVEN_Pos (16)
6457#define PWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL4_5_BRKAEVEN_Pos)
6459#define PWM_BRKCTL4_5_BRKAODD_Pos (18)
6460#define PWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << PWM_BRKCTL4_5_BRKAODD_Pos)
6462#define PWM_POLCTL_PINVn_Pos (0)
6463#define PWM_POLCTL_PINVn_Msk (0x3ful << PWM_POLCTL_PINVn_Pos)
6465#define PWM_POLCTL_PINV0_Pos (0)
6466#define PWM_POLCTL_PINV0_Msk (0x1ul << PWM_POLCTL_PINV0_Pos)
6468#define PWM_POLCTL_PINV1_Pos (1)
6469#define PWM_POLCTL_PINV1_Msk (0x1ul << PWM_POLCTL_PINV1_Pos)
6471#define PWM_POLCTL_PINV2_Pos (2)
6472#define PWM_POLCTL_PINV2_Msk (0x1ul << PWM_POLCTL_PINV2_Pos)
6474#define PWM_POLCTL_PINV3_Pos (3)
6475#define PWM_POLCTL_PINV3_Msk (0x1ul << PWM_POLCTL_PINV3_Pos)
6477#define PWM_POLCTL_PINV4_Pos (4)
6478#define PWM_POLCTL_PINV4_Msk (0x1ul << PWM_POLCTL_PINV4_Pos)
6480#define PWM_POLCTL_PINV5_Pos (5)
6481#define PWM_POLCTL_PINV5_Msk (0x1ul << PWM_POLCTL_PINV5_Pos)
6483#define PWM_POEN_POENn_Pos (0)
6484#define PWM_POEN_POENn_Msk (0x3ful << PWM_POEN_POENn_Pos)
6486#define PWM_POEN_POEN0_Pos (0)
6487#define PWM_POEN_POEN0_Msk (0x1ul << PWM_POEN_POEN0_Pos)
6489#define PWM_POEN_POEN1_Pos (1)
6490#define PWM_POEN_POEN1_Msk (0x1ul << PWM_POEN_POEN1_Pos)
6492#define PWM_POEN_POEN2_Pos (2)
6493#define PWM_POEN_POEN2_Msk (0x1ul << PWM_POEN_POEN2_Pos)
6495#define PWM_POEN_POEN3_Pos (3)
6496#define PWM_POEN_POEN3_Msk (0x1ul << PWM_POEN_POEN3_Pos)
6498#define PWM_POEN_POEN4_Pos (4)
6499#define PWM_POEN_POEN4_Msk (0x1ul << PWM_POEN_POEN4_Pos)
6501#define PWM_POEN_POEN5_Pos (5)
6502#define PWM_POEN_POEN5_Msk (0x1ul << PWM_POEN_POEN5_Pos)
6504#define PWM_SWBRK_BRKETRGn_Pos (0)
6505#define PWM_SWBRK_BRKETRGn_Msk (0x7ul << PWM_SWBRK_BRKETRGn_Pos)
6507#define PWM_SWBRK_BRKETRG0_Pos (0)
6508#define PWM_SWBRK_BRKETRG0_Msk (0x1ul << PWM_SWBRK_BRKETRG0_Pos)
6510#define PWM_SWBRK_BRKETRG2_Pos (1)
6511#define PWM_SWBRK_BRKETRG2_Msk (0x1ul << PWM_SWBRK_BRKETRG2_Pos)
6513#define PWM_SWBRK_BRKETRG4_Pos (2)
6514#define PWM_SWBRK_BRKETRG4_Msk (0x1ul << PWM_SWBRK_BRKETRG4_Pos)
6516#define PWM_SWBRK_BRKLTRGn_Pos (8)
6517#define PWM_SWBRK_BRKLTRGn_Msk (0x7ul << PWM_SWBRK_BRKLTRGn_Pos)
6519#define PWM_SWBRK_BRKLTRG0_Pos (8)
6520#define PWM_SWBRK_BRKLTRG0_Msk (0x1ul << PWM_SWBRK_BRKLTRG0_Pos)
6522#define PWM_SWBRK_BRKLTRG2_Pos (9)
6523#define PWM_SWBRK_BRKLTRG2_Msk (0x1ul << PWM_SWBRK_BRKLTRG2_Pos)
6525#define PWM_SWBRK_BRKLTRG4_Pos (10)
6526#define PWM_SWBRK_BRKLTRG4_Msk (0x1ul << PWM_SWBRK_BRKLTRG4_Pos)
6528#define PWM_INTEN0_ZIENn_Pos (0)
6529#define PWM_INTEN0_ZIENn_Msk (0x3ful << PWM_INTEN0_ZIENn_Pos)
6531#define PWM_INTEN0_ZIEN0_Pos (0)
6532#define PWM_INTEN0_ZIEN0_Msk (0x1ul << PWM_INTEN0_ZIEN0_Pos)
6534#define PWM_INTEN0_ZIEN1_Pos (1)
6535#define PWM_INTEN0_ZIEN1_Msk (0x1ul << PWM_INTEN0_ZIEN1_Pos)
6537#define PWM_INTEN0_ZIEN2_Pos (2)
6538#define PWM_INTEN0_ZIEN2_Msk (0x1ul << PWM_INTEN0_ZIEN2_Pos)
6540#define PWM_INTEN0_ZIEN3_Pos (3)
6541#define PWM_INTEN0_ZIEN3_Msk (0x1ul << PWM_INTEN0_ZIEN3_Pos)
6543#define PWM_INTEN0_ZIEN4_Pos (4)
6544#define PWM_INTEN0_ZIEN4_Msk (0x1ul << PWM_INTEN0_ZIEN4_Pos)
6546#define PWM_INTEN0_ZIEN5_Pos (5)
6547#define PWM_INTEN0_ZIEN5_Msk (0x1ul << PWM_INTEN0_ZIEN5_Pos)
6549#define PWM_INTEN0_IFAIEN0_1_Pos (7)
6550#define PWM_INTEN0_IFAIEN0_1_Msk (0x1ul << PWM_INTEN0_IFAIEN0_1_Pos)
6552#define PWM_INTEN0_PIENn_Pos (8)
6553#define PWM_INTEN0_PIENn_Msk (0x3ful << PWM_INTEN0_PIENn_Pos)
6555#define PWM_INTEN0_PIEN0_Pos (8)
6556#define PWM_INTEN0_PIEN0_Msk (0x1ul << PWM_INTEN0_PIEN0_Pos)
6558#define PWM_INTEN0_PIEN1_Pos (9)
6559#define PWM_INTEN0_PIEN1_Msk (0x1ul << PWM_INTEN0_PIEN1_Pos)
6561#define PWM_INTEN0_PIEN2_Pos (10)
6562#define PWM_INTEN0_PIEN2_Msk (0x1ul << PWM_INTEN0_PIEN2_Pos)
6564#define PWM_INTEN0_PIEN3_Pos (11)
6565#define PWM_INTEN0_PIEN3_Msk (0x1ul << PWM_INTEN0_PIEN3_Pos)
6567#define PWM_INTEN0_PIEN4_Pos (12)
6568#define PWM_INTEN0_PIEN4_Msk (0x1ul << PWM_INTEN0_PIEN4_Pos)
6570#define PWM_INTEN0_PIEN5_Pos (13)
6571#define PWM_INTEN0_PIEN5_Msk (0x1ul << PWM_INTEN0_PIEN5_Pos)
6573#define PWM_INTEN0_IFAIEN2_3_Pos (15)
6574#define PWM_INTEN0_IFAIEN2_3_Msk (0x1ul << PWM_INTEN0_IFAIEN2_3_Pos)
6576#define PWM_INTEN0_CMPUIENn_Pos (16)
6577#define PWM_INTEN0_CMPUIENn_Msk (0x3ful << PWM_INTEN0_CMPUIENn_Pos)
6579#define PWM_INTEN0_CMPUIEN0_Pos (16)
6580#define PWM_INTEN0_CMPUIEN0_Msk (0x1ul << PWM_INTEN0_CMPUIEN0_Pos)
6582#define PWM_INTEN0_CMPUIEN1_Pos (17)
6583#define PWM_INTEN0_CMPUIEN1_Msk (0x1ul << PWM_INTEN0_CMPUIEN1_Pos)
6585#define PWM_INTEN0_CMPUIEN2_Pos (18)
6586#define PWM_INTEN0_CMPUIEN2_Msk (0x1ul << PWM_INTEN0_CMPUIEN2_Pos)
6588#define PWM_INTEN0_CMPUIEN3_Pos (19)
6589#define PWM_INTEN0_CMPUIEN3_Msk (0x1ul << PWM_INTEN0_CMPUIEN3_Pos)
6591#define PWM_INTEN0_CMPUIEN4_Pos (20)
6592#define PWM_INTEN0_CMPUIEN4_Msk (0x1ul << PWM_INTEN0_CMPUIEN4_Pos)
6594#define PWM_INTEN0_CMPUIEN5_Pos (21)
6595#define PWM_INTEN0_CMPUIEN5_Msk (0x1ul << PWM_INTEN0_CMPUIEN5_Pos)
6597#define PWM_INTEN0_IFAIEN4_5_Pos (23)
6598#define PWM_INTEN0_IFAIEN4_5_Msk (0x1ul << PWM_INTEN0_IFAIEN4_5_Pos)
6600#define PWM_INTEN0_CMPDIENn_Pos (24)
6601#define PWM_INTEN0_CMPDIENn_Msk (0x3ful << PWM_INTEN0_CMPDIENn_Pos)
6603#define PWM_INTEN0_CMPDIEN0_Pos (24)
6604#define PWM_INTEN0_CMPDIEN0_Msk (0x1ul << PWM_INTEN0_CMPDIEN0_Pos)
6606#define PWM_INTEN0_CMPDIEN1_Pos (25)
6607#define PWM_INTEN0_CMPDIEN1_Msk (0x1ul << PWM_INTEN0_CMPDIEN1_Pos)
6609#define PWM_INTEN0_CMPDIEN2_Pos (26)
6610#define PWM_INTEN0_CMPDIEN2_Msk (0x1ul << PWM_INTEN0_CMPDIEN2_Pos)
6612#define PWM_INTEN0_CMPDIEN3_Pos (27)
6613#define PWM_INTEN0_CMPDIEN3_Msk (0x1ul << PWM_INTEN0_CMPDIEN3_Pos)
6615#define PWM_INTEN0_CMPDIEN4_Pos (28)
6616#define PWM_INTEN0_CMPDIEN4_Msk (0x1ul << PWM_INTEN0_CMPDIEN4_Pos)
6618#define PWM_INTEN0_CMPDIEN5_Pos (29)
6619#define PWM_INTEN0_CMPDIEN5_Msk (0x1ul << PWM_INTEN0_CMPDIEN5_Pos)
6621#define PWM_INTEN1_BRKEIEN0_1_Pos (0)
6622#define PWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << PWM_INTEN1_BRKEIEN0_1_Pos)
6624#define PWM_INTEN1_BRKEIEN2_3_Pos (1)
6625#define PWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << PWM_INTEN1_BRKEIEN2_3_Pos)
6627#define PWM_INTEN1_BRKEIEN4_5_Pos (2)
6628#define PWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << PWM_INTEN1_BRKEIEN4_5_Pos)
6630#define PWM_INTEN1_BRKLIEN0_1_Pos (8)
6631#define PWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << PWM_INTEN1_BRKLIEN0_1_Pos)
6633#define PWM_INTEN1_BRKLIEN2_3_Pos (9)
6634#define PWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << PWM_INTEN1_BRKLIEN2_3_Pos)
6636#define PWM_INTEN1_BRKLIEN4_5_Pos (10)
6637#define PWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << PWM_INTEN1_BRKLIEN4_5_Pos)
6639#define PWM_INTSTS0_ZIFn_Pos (0)
6640#define PWM_INTSTS0_ZIFn_Msk (0x3ful << PWM_INTSTS0_ZIFn_Pos)
6642#define PWM_INTSTS0_ZIF0_Pos (0)
6643#define PWM_INTSTS0_ZIF0_Msk (0x1ul << PWM_INTSTS0_ZIF0_Pos)
6645#define PWM_INTSTS0_ZIF1_Pos (1)
6646#define PWM_INTSTS0_ZIF1_Msk (0x1ul << PWM_INTSTS0_ZIF1_Pos)
6648#define PWM_INTSTS0_ZIF2_Pos (2)
6649#define PWM_INTSTS0_ZIF2_Msk (0x1ul << PWM_INTSTS0_ZIF2_Pos)
6651#define PWM_INTSTS0_ZIF3_Pos (3)
6652#define PWM_INTSTS0_ZIF3_Msk (0x1ul << PWM_INTSTS0_ZIF3_Pos)
6654#define PWM_INTSTS0_ZIF4_Pos (4)
6655#define PWM_INTSTS0_ZIF4_Msk (0x1ul << PWM_INTSTS0_ZIF4_Pos)
6657#define PWM_INTSTS0_ZIF5_Pos (5)
6658#define PWM_INTSTS0_ZIF5_Msk (0x1ul << PWM_INTSTS0_ZIF5_Pos)
6660#define PWM_INTSTS0_IFAIF0_1_Pos (7)
6661#define PWM_INTSTS0_IFAIF0_1_Msk (0x1ul << PWM_INTSTS0_IFAIF0_1_Pos)
6663#define PWM_INTSTS0_PIFn_Pos (8)
6664#define PWM_INTSTS0_PIFn_Msk (0x3ful << PWM_INTSTS0_PIFn_Pos)
6666#define PWM_INTSTS0_PIF0_Pos (8)
6667#define PWM_INTSTS0_PIF0_Msk (0x1ul << PWM_INTSTS0_PIF0_Pos)
6669#define PWM_INTSTS0_PIF1_Pos (9)
6670#define PWM_INTSTS0_PIF1_Msk (0x1ul << PWM_INTSTS0_PIF1_Pos)
6672#define PWM_INTSTS0_PIF2_Pos (10)
6673#define PWM_INTSTS0_PIF2_Msk (0x1ul << PWM_INTSTS0_PIF2_Pos)
6675#define PWM_INTSTS0_PIF3_Pos (11)
6676#define PWM_INTSTS0_PIF3_Msk (0x1ul << PWM_INTSTS0_PIF3_Pos)
6678#define PWM_INTSTS0_PIF4_Pos (12)
6679#define PWM_INTSTS0_PIF4_Msk (0x1ul << PWM_INTSTS0_PIF4_Pos)
6681#define PWM_INTSTS0_PIF5_Pos (13)
6682#define PWM_INTSTS0_PIF5_Msk (0x1ul << PWM_INTSTS0_PIF5_Pos)
6684#define PWM_INTSTS0_IFAIF2_3_Pos (15)
6685#define PWM_INTSTS0_IFAIF2_3_Msk (0x1ul << PWM_INTSTS0_IFAIF2_3_Pos)
6687#define PWM_INTSTS0_CMPUIFn_Pos (16)
6688#define PWM_INTSTS0_CMPUIFn_Msk (0x3ful << PWM_INTSTS0_CMPUIFn_Pos)
6690#define PWM_INTSTS0_CMPUIF0_Pos (16)
6691#define PWM_INTSTS0_CMPUIF0_Msk (0x1ul << PWM_INTSTS0_CMPUIF0_Pos)
6693#define PWM_INTSTS0_CMPUIF1_Pos (17)
6694#define PWM_INTSTS0_CMPUIF1_Msk (0x1ul << PWM_INTSTS0_CMPUIF1_Pos)
6696#define PWM_INTSTS0_CMPUIF2_Pos (18)
6697#define PWM_INTSTS0_CMPUIF2_Msk (0x1ul << PWM_INTSTS0_CMPUIF2_Pos)
6699#define PWM_INTSTS0_CMPUIF3_Pos (19)
6700#define PWM_INTSTS0_CMPUIF3_Msk (0x1ul << PWM_INTSTS0_CMPUIF3_Pos)
6702#define PWM_INTSTS0_CMPUIF4_Pos (20)
6703#define PWM_INTSTS0_CMPUIF4_Msk (0x1ul << PWM_INTSTS0_CMPUIF4_Pos)
6705#define PWM_INTSTS0_CMPUIF5_Pos (21)
6706#define PWM_INTSTS0_CMPUIF5_Msk (0x1ul << PWM_INTSTS0_CMPUIF5_Pos)
6708#define PWM_INTSTS0_IFAIF4_5_Pos (23)
6709#define PWM_INTSTS0_IFAIF4_5_Msk (0x1ul << PWM_INTSTS0_IFAIF4_5_Pos)
6711#define PWM_INTSTS0_CMPDIFn_Pos (24)
6712#define PWM_INTSTS0_CMPDIFn_Msk (0x3ful << PWM_INTSTS0_CMPDIFn_Pos)
6714#define PWM_INTSTS0_CMPDIF0_Pos (24)
6715#define PWM_INTSTS0_CMPDIF0_Msk (0x1ul << PWM_INTSTS0_CMPDIF0_Pos)
6717#define PWM_INTSTS0_CMPDIF1_Pos (25)
6718#define PWM_INTSTS0_CMPDIF1_Msk (0x1ul << PWM_INTSTS0_CMPDIF1_Pos)
6720#define PWM_INTSTS0_CMPDIF2_Pos (26)
6721#define PWM_INTSTS0_CMPDIF2_Msk (0x1ul << PWM_INTSTS0_CMPDIF2_Pos)
6723#define PWM_INTSTS0_CMPDIF3_Pos (27)
6724#define PWM_INTSTS0_CMPDIF3_Msk (0x1ul << PWM_INTSTS0_CMPDIF3_Pos)
6726#define PWM_INTSTS0_CMPDIF4_Pos (28)
6727#define PWM_INTSTS0_CMPDIF4_Msk (0x1ul << PWM_INTSTS0_CMPDIF4_Pos)
6729#define PWM_INTSTS0_CMPDIF5_Pos (29)
6730#define PWM_INTSTS0_CMPDIF5_Msk (0x1ul << PWM_INTSTS0_CMPDIF5_Pos)
6732#define PWM_INTSTS1_BRKEIFn_Pos (0)
6733#define PWM_INTSTS1_BRKEIFn_Msk (0x3ful << PWM_INTSTS1_BRKEIFn_Pos)
6735#define PWM_INTSTS1_BRKEIF0_Pos (0)
6736#define PWM_INTSTS1_BRKEIF0_Msk (0x1ul << PWM_INTSTS1_BRKEIF0_Pos)
6738#define PWM_INTSTS1_BRKEIF1_Pos (1)
6739#define PWM_INTSTS1_BRKEIF1_Msk (0x1ul << PWM_INTSTS1_BRKEIF1_Pos)
6741#define PWM_INTSTS1_BRKEIF2_Pos (2)
6742#define PWM_INTSTS1_BRKEIF2_Msk (0x1ul << PWM_INTSTS1_BRKEIF2_Pos)
6744#define PWM_INTSTS1_BRKEIF3_Pos (3)
6745#define PWM_INTSTS1_BRKEIF3_Msk (0x1ul << PWM_INTSTS1_BRKEIF3_Pos)
6747#define PWM_INTSTS1_BRKEIF4_Pos (4)
6748#define PWM_INTSTS1_BRKEIF4_Msk (0x1ul << PWM_INTSTS1_BRKEIF4_Pos)
6750#define PWM_INTSTS1_BRKEIF5_Pos (5)
6751#define PWM_INTSTS1_BRKEIF5_Msk (0x1ul << PWM_INTSTS1_BRKEIF5_Pos)
6753#define PWM_INTSTS1_BRKLIFn_Pos (8)
6754#define PWM_INTSTS1_BRKLIFn_Msk (0x3ful << PWM_INTSTS1_BRKLIFn_Pos)
6756#define PWM_INTSTS1_BRKLIF0_Pos (8)
6757#define PWM_INTSTS1_BRKLIF0_Msk (0x1ul << PWM_INTSTS1_BRKLIF0_Pos)
6759#define PWM_INTSTS1_BRKLIF1_Pos (9)
6760#define PWM_INTSTS1_BRKLIF1_Msk (0x1ul << PWM_INTSTS1_BRKLIF1_Pos)
6762#define PWM_INTSTS1_BRKLIF2_Pos (10)
6763#define PWM_INTSTS1_BRKLIF2_Msk (0x1ul << PWM_INTSTS1_BRKLIF2_Pos)
6765#define PWM_INTSTS1_BRKLIF3_Pos (11)
6766#define PWM_INTSTS1_BRKLIF3_Msk (0x1ul << PWM_INTSTS1_BRKLIF3_Pos)
6768#define PWM_INTSTS1_BRKLIF4_Pos (12)
6769#define PWM_INTSTS1_BRKLIF4_Msk (0x1ul << PWM_INTSTS1_BRKLIF4_Pos)
6771#define PWM_INTSTS1_BRKLIF5_Pos (13)
6772#define PWM_INTSTS1_BRKLIF5_Msk (0x1ul << PWM_INTSTS1_BRKLIF5_Pos)
6774#define PWM_INTSTS1_BRKESTS0_Pos (16)
6775#define PWM_INTSTS1_BRKESTS0_Msk (0x1ul << PWM_INTSTS1_BRKESTS0_Pos)
6777#define PWM_INTSTS1_BRKESTS1_Pos (17)
6778#define PWM_INTSTS1_BRKESTS1_Msk (0x1ul << PWM_INTSTS1_BRKESTS1_Pos)
6780#define PWM_INTSTS1_BRKESTS2_Pos (18)
6781#define PWM_INTSTS1_BRKESTS2_Msk (0x1ul << PWM_INTSTS1_BRKESTS2_Pos)
6783#define PWM_INTSTS1_BRKESTS3_Pos (19)
6784#define PWM_INTSTS1_BRKESTS3_Msk (0x1ul << PWM_INTSTS1_BRKESTS3_Pos)
6786#define PWM_INTSTS1_BRKESTS4_Pos (20)
6787#define PWM_INTSTS1_BRKESTS4_Msk (0x1ul << PWM_INTSTS1_BRKESTS4_Pos)
6789#define PWM_INTSTS1_BRKESTS5_Pos (21)
6790#define PWM_INTSTS1_BRKESTS5_Msk (0x1ul << PWM_INTSTS1_BRKESTS5_Pos)
6792#define PWM_INTSTS1_BRKLSTS0_Pos (24)
6793#define PWM_INTSTS1_BRKLSTS0_Msk (0x1ul << PWM_INTSTS1_BRKLSTS0_Pos)
6795#define PWM_INTSTS1_BRKLSTS1_Pos (25)
6796#define PWM_INTSTS1_BRKLSTS1_Msk (0x1ul << PWM_INTSTS1_BRKLSTS1_Pos)
6798#define PWM_INTSTS1_BRKLSTS2_Pos (26)
6799#define PWM_INTSTS1_BRKLSTS2_Msk (0x1ul << PWM_INTSTS1_BRKLSTS2_Pos)
6801#define PWM_INTSTS1_BRKLSTS3_Pos (27)
6802#define PWM_INTSTS1_BRKLSTS3_Msk (0x1ul << PWM_INTSTS1_BRKLSTS3_Pos)
6804#define PWM_INTSTS1_BRKLSTS4_Pos (28)
6805#define PWM_INTSTS1_BRKLSTS4_Msk (0x1ul << PWM_INTSTS1_BRKLSTS4_Pos)
6807#define PWM_INTSTS1_BRKLSTS5_Pos (29)
6808#define PWM_INTSTS1_BRKLSTS5_Msk (0x1ul << PWM_INTSTS1_BRKLSTS5_Pos)
6810#define PWM_IFA_IFCNT0_1_Pos (0)
6811#define PWM_IFA_IFCNT0_1_Msk (0xful << PWM_IFA_IFCNT0_1_Pos)
6813#define PWM_IFA_IFSEL0_1_Pos (4)
6814#define PWM_IFA_IFSEL0_1_Msk (0x7ul << PWM_IFA_IFSEL0_1_Pos)
6816#define PWM_IFA_IFAEN0_1_Pos (7)
6817#define PWM_IFA_IFAEN0_1_Msk (0x1ul << PWM_IFA_IFAEN0_1_Pos)
6819#define PWM_IFA_IFCNT2_3_Pos (8)
6820#define PWM_IFA_IFCNT2_3_Msk (0xful << PWM_IFA_IFCNT2_3_Pos)
6822#define PWM_IFA_IFSEL2_3_Pos (12)
6823#define PWM_IFA_IFSEL2_3_Msk (0x7ul << PWM_IFA_IFSEL2_3_Pos)
6825#define PWM_IFA_IFAEN2_3_Pos (15)
6826#define PWM_IFA_IFAEN2_3_Msk (0x1ul << PWM_IFA_IFAEN2_3_Pos)
6828#define PWM_IFA_IFCNT4_5_Pos (16)
6829#define PWM_IFA_IFCNT4_5_Msk (0xful << PWM_IFA_IFCNT4_5_Pos)
6831#define PWM_IFA_IFSEL4_5_Pos (20)
6832#define PWM_IFA_IFSEL4_5_Msk (0x7ul << PWM_IFA_IFSEL4_5_Pos)
6834#define PWM_IFA_IFAEN4_5_Pos (23)
6835#define PWM_IFA_IFAEN4_5_Msk (0x1ul << PWM_IFA_IFAEN4_5_Pos)
6837#define PWM_EADCTS0_TRGSEL0_Pos (0)
6838#define PWM_EADCTS0_TRGSEL0_Msk (0xful << PWM_EADCTS0_TRGSEL0_Pos)
6840#define PWM_EADCTS0_TRGEN0_Pos (7)
6841#define PWM_EADCTS0_TRGEN0_Msk (0x1ul << PWM_EADCTS0_TRGEN0_Pos)
6843#define PWM_EADCTS0_TRGSEL1_Pos (8)
6844#define PWM_EADCTS0_TRGSEL1_Msk (0xful << PWM_EADCTS0_TRGSEL1_Pos)
6846#define PWM_EADCTS0_TRGEN1_Pos (15)
6847#define PWM_EADCTS0_TRGEN1_Msk (0x1ul << PWM_EADCTS0_TRGEN1_Pos)
6849#define PWM_EADCTS0_TRGSEL2_Pos (16)
6850#define PWM_EADCTS0_TRGSEL2_Msk (0xful << PWM_EADCTS0_TRGSEL2_Pos)
6852#define PWM_EADCTS0_TRGEN2_Pos (23)
6853#define PWM_EADCTS0_TRGEN2_Msk (0x1ul << PWM_EADCTS0_TRGEN2_Pos)
6855#define PWM_EADCTS0_TRGSEL3_Pos (24)
6856#define PWM_EADCTS0_TRGSEL3_Msk (0xful << PWM_EADCTS0_TRGSEL3_Pos)
6858#define PWM_EADCTS0_TRGEN3_Pos (31)
6859#define PWM_EADCTS0_TRGEN3_Msk (0x1ul << PWM_EADCTS0_TRGEN3_Pos)
6861#define PWM_EADCTS1_TRGSEL4_Pos (0)
6862#define PWM_EADCTS1_TRGSEL4_Msk (0xful << PWM_EADCTS1_TRGSEL4_Pos)
6864#define PWM_EADCTS1_TRGEN4_Pos (7)
6865#define PWM_EADCTS1_TRGEN4_Msk (0x1ul << PWM_EADCTS1_TRGEN4_Pos)
6867#define PWM_EADCTS1_TRGSEL5_Pos (8)
6868#define PWM_EADCTS1_TRGSEL5_Msk (0xful << PWM_EADCTS1_TRGSEL5_Pos)
6870#define PWM_EADCTS1_TRGEN5_Pos (15)
6871#define PWM_EADCTS1_TRGEN5_Msk (0x1ul << PWM_EADCTS1_TRGEN5_Pos)
6873#define PWM_FTCMPDAT0_1_FTCMP_Pos (0)
6874#define PWM_FTCMPDAT0_1_FTCMP_Msk (0xfffful << PWM_FTCMPDAT0_1_FTCMP_Pos)
6876#define PWM_FTCMPDAT2_3_FTCMP_Pos (0)
6877#define PWM_FTCMPDAT2_3_FTCMP_Msk (0xfffful << PWM_FTCMPDAT2_3_FTCMP_Pos)
6879#define PWM_FTCMPDAT4_5_FTCMP_Pos (0)
6880#define PWM_FTCMPDAT4_5_FTCMP_Msk (0xfffful << PWM_FTCMPDAT4_5_FTCMP_Pos)
6882#define PWM_SSCTL_SSENn_Pos (0)
6883#define PWM_SSCTL_SSENn_Msk (0x3ful << PWM_SSCTL_SSENn_Pos)
6885#define PWM_SSCTL_SSEN0_Pos (0)
6886#define PWM_SSCTL_SSEN0_Msk (0x1ul << PWM_SSCTL_SSEN0_Pos)
6888#define PWM_SSCTL_SSEN1_Pos (1)
6889#define PWM_SSCTL_SSEN1_Msk (0x1ul << PWM_SSCTL_SSEN1_Pos)
6891#define PWM_SSCTL_SSEN2_Pos (2)
6892#define PWM_SSCTL_SSEN2_Msk (0x1ul << PWM_SSCTL_SSEN2_Pos)
6894#define PWM_SSCTL_SSEN3_Pos (3)
6895#define PWM_SSCTL_SSEN3_Msk (0x1ul << PWM_SSCTL_SSEN3_Pos)
6897#define PWM_SSCTL_SSEN4_Pos (4)
6898#define PWM_SSCTL_SSEN4_Msk (0x1ul << PWM_SSCTL_SSEN4_Pos)
6900#define PWM_SSCTL_SSEN5_Pos (5)
6901#define PWM_SSCTL_SSEN5_Msk (0x1ul << PWM_SSCTL_SSEN5_Pos)
6903#define PWM_SSTRG_CNTSEN_Pos (0)
6904#define PWM_SSTRG_CNTSEN_Msk (0x1ul << PWM_SSTRG_CNTSEN_Pos)
6906#define PWM_STATUS_CNTMAXFn_Pos (0)
6907#define PWM_STATUS_CNTMAXFn_Msk (0x3ful << PWM_STATUS_CNTMAXFn_Pos)
6909#define PWM_STATUS_CNTMAXF0_Pos (0)
6910#define PWM_STATUS_CNTMAXF0_Msk (0x1ul << PWM_STATUS_CNTMAXF0_Pos)
6912#define PWM_STATUS_CNTMAXF1_Pos (1)
6913#define PWM_STATUS_CNTMAXF1_Msk (0x1ul << PWM_STATUS_CNTMAXF1_Pos)
6915#define PWM_STATUS_CNTMAXF2_Pos (2)
6916#define PWM_STATUS_CNTMAXF2_Msk (0x1ul << PWM_STATUS_CNTMAXF2_Pos)
6918#define PWM_STATUS_CNTMAXF3_Pos (3)
6919#define PWM_STATUS_CNTMAXF3_Msk (0x1ul << PWM_STATUS_CNTMAXF3_Pos)
6921#define PWM_STATUS_CNTMAXF4_Pos (4)
6922#define PWM_STATUS_CNTMAXF4_Msk (0x1ul << PWM_STATUS_CNTMAXF4_Pos)
6924#define PWM_STATUS_CNTMAXF5_Pos (5)
6925#define PWM_STATUS_CNTMAXF5_Msk (0x1ul << PWM_STATUS_CNTMAXF5_Pos)
6927#define PWM_STATUS_SYNCINFn_Pos (8)
6928#define PWM_STATUS_SYNCINFn_Msk (0x7ul << PWM_STATUS_SYNCINFn_Pos)
6930#define PWM_STATUS_SYNCINF0_Pos (8)
6931#define PWM_STATUS_SYNCINF0_Msk (0x1ul << PWM_STATUS_SYNCINF0_Pos)
6933#define PWM_STATUS_SYNCINF2_Pos (9)
6934#define PWM_STATUS_SYNCINF2_Msk (0x1ul << PWM_STATUS_SYNCINF2_Pos)
6936#define PWM_STATUS_SYNCINF4_Pos (10)
6937#define PWM_STATUS_SYNCINF4_Msk (0x1ul << PWM_STATUS_SYNCINF4_Pos)
6939#define PWM_STATUS_ADCTRGFn_Pos (16)
6940#define PWM_STATUS_ADCTRGFn_Msk (0x3ful << PWM_STATUS_ADCTRGFn_Pos)
6942#define PWM_STATUS_ADCTRGF0_Pos (16)
6943#define PWM_STATUS_ADCTRGF0_Msk (0x1ul << PWM_STATUS_ADCTRGF0_Pos)
6945#define PWM_STATUS_ADCTRGF1_Pos (17)
6946#define PWM_STATUS_ADCTRGF1_Msk (0x1ul << PWM_STATUS_ADCTRGF1_Pos)
6948#define PWM_STATUS_ADCTRGF2_Pos (18)
6949#define PWM_STATUS_ADCTRGF2_Msk (0x1ul << PWM_STATUS_ADCTRGF2_Pos)
6951#define PWM_STATUS_ADCTRGF3_Pos (19)
6952#define PWM_STATUS_ADCTRGF3_Msk (0x1ul << PWM_STATUS_ADCTRGF3_Pos)
6954#define PWM_STATUS_ADCTRGF4_Pos (20)
6955#define PWM_STATUS_ADCTRGF4_Msk (0x1ul << PWM_STATUS_ADCTRGF4_Pos)
6957#define PWM_STATUS_ADCTRGF5_Pos (21)
6958#define PWM_STATUS_ADCTRGF5_Msk (0x1ul << PWM_STATUS_ADCTRGF5_Pos)
6960#define PWM_CAPINEN_CAPINENn_Pos (0)
6961#define PWM_CAPINEN_CAPINENn_Msk (0x3ful << PWM_CAPINEN_CAPINENn_Pos)
6963#define PWM_CAPINEN_CAPINEN0_Pos (0)
6964#define PWM_CAPINEN_CAPINEN0_Msk (0x1ul << PWM_CAPINEN_CAPINEN0_Pos)
6966#define PWM_CAPINEN_CAPINEN1_Pos (1)
6967#define PWM_CAPINEN_CAPINEN1_Msk (0x1ul << PWM_CAPINEN_CAPINEN1_Pos)
6969#define PWM_CAPINEN_CAPINEN2_Pos (2)
6970#define PWM_CAPINEN_CAPINEN2_Msk (0x1ul << PWM_CAPINEN_CAPINEN2_Pos)
6972#define PWM_CAPINEN_CAPINEN3_Pos (3)
6973#define PWM_CAPINEN_CAPINEN3_Msk (0x1ul << PWM_CAPINEN_CAPINEN3_Pos)
6975#define PWM_CAPINEN_CAPINEN4_Pos (4)
6976#define PWM_CAPINEN_CAPINEN4_Msk (0x1ul << PWM_CAPINEN_CAPINEN4_Pos)
6978#define PWM_CAPINEN_CAPINEN5_Pos (5)
6979#define PWM_CAPINEN_CAPINEN5_Msk (0x1ul << PWM_CAPINEN_CAPINEN5_Pos)
6981#define PWM_CAPCTL_CAPENn_Pos (0)
6982#define PWM_CAPCTL_CAPENn_Msk (0x3ful << PWM_CAPCTL_CAPENn_Pos)
6984#define PWM_CAPCTL_CAPEN0_Pos (0)
6985#define PWM_CAPCTL_CAPEN0_Msk (0x1ul << PWM_CAPCTL_CAPEN0_Pos)
6987#define PWM_CAPCTL_CAPEN1_Pos (1)
6988#define PWM_CAPCTL_CAPEN1_Msk (0x1ul << PWM_CAPCTL_CAPEN1_Pos)
6990#define PWM_CAPCTL_CAPEN2_Pos (2)
6991#define PWM_CAPCTL_CAPEN2_Msk (0x1ul << PWM_CAPCTL_CAPEN2_Pos)
6993#define PWM_CAPCTL_CAPEN3_Pos (3)
6994#define PWM_CAPCTL_CAPEN3_Msk (0x1ul << PWM_CAPCTL_CAPEN3_Pos)
6996#define PWM_CAPCTL_CAPEN4_Pos (4)
6997#define PWM_CAPCTL_CAPEN4_Msk (0x1ul << PWM_CAPCTL_CAPEN4_Pos)
6999#define PWM_CAPCTL_CAPEN5_Pos (5)
7000#define PWM_CAPCTL_CAPEN5_Msk (0x1ul << PWM_CAPCTL_CAPEN5_Pos)
7002#define PWM_CAPCTL_CAPINVn_Pos (8)
7003#define PWM_CAPCTL_CAPINVn_Msk (0x3ful << PWM_CAPCTL_CAPINVn_Pos)
7005#define PWM_CAPCTL_CAPINV0_Pos (8)
7006#define PWM_CAPCTL_CAPINV0_Msk (0x1ul << PWM_CAPCTL_CAPINV0_Pos)
7008#define PWM_CAPCTL_CAPINV1_Pos (9)
7009#define PWM_CAPCTL_CAPINV1_Msk (0x1ul << PWM_CAPCTL_CAPINV1_Pos)
7011#define PWM_CAPCTL_CAPINV2_Pos (10)
7012#define PWM_CAPCTL_CAPINV2_Msk (0x1ul << PWM_CAPCTL_CAPINV2_Pos)
7014#define PWM_CAPCTL_CAPINV3_Pos (11)
7015#define PWM_CAPCTL_CAPINV3_Msk (0x1ul << PWM_CAPCTL_CAPINV3_Pos)
7017#define PWM_CAPCTL_CAPINV4_Pos (12)
7018#define PWM_CAPCTL_CAPINV4_Msk (0x1ul << PWM_CAPCTL_CAPINV4_Pos)
7020#define PWM_CAPCTL_CAPINV5_Pos (13)
7021#define PWM_CAPCTL_CAPINV5_Msk (0x1ul << PWM_CAPCTL_CAPINV5_Pos)
7023#define PWM_CAPCTL_RCRLDENn_Pos (16)
7024#define PWM_CAPCTL_RCRLDENn_Msk (0x3ful << PWM_CAPCTL_RCRLDENn_Pos)
7026#define PWM_CAPCTL_RCRLDEN0_Pos (16)
7027#define PWM_CAPCTL_RCRLDEN0_Msk (0x1ul << PWM_CAPCTL_RCRLDEN0_Pos)
7029#define PWM_CAPCTL_RCRLDEN1_Pos (17)
7030#define PWM_CAPCTL_RCRLDEN1_Msk (0x1ul << PWM_CAPCTL_RCRLDEN1_Pos)
7032#define PWM_CAPCTL_RCRLDEN2_Pos (18)
7033#define PWM_CAPCTL_RCRLDEN2_Msk (0x1ul << PWM_CAPCTL_RCRLDEN2_Pos)
7035#define PWM_CAPCTL_RCRLDEN3_Pos (19)
7036#define PWM_CAPCTL_RCRLDEN3_Msk (0x1ul << PWM_CAPCTL_RCRLDEN3_Pos)
7038#define PWM_CAPCTL_RCRLDEN4_Pos (20)
7039#define PWM_CAPCTL_RCRLDEN4_Msk (0x1ul << PWM_CAPCTL_RCRLDEN4_Pos)
7041#define PWM_CAPCTL_RCRLDEN5_Pos (21)
7042#define PWM_CAPCTL_RCRLDEN5_Msk (0x1ul << PWM_CAPCTL_RCRLDEN5_Pos)
7044#define PWM_CAPCTL_FCRLDENn_Pos (24)
7045#define PWM_CAPCTL_FCRLDENn_Msk (0x3ful << PWM_CAPCTL_FCRLDENn_Pos)
7047#define PWM_CAPCTL_FCRLDEN0_Pos (24)
7048#define PWM_CAPCTL_FCRLDEN0_Msk (0x1ul << PWM_CAPCTL_FCRLDEN0_Pos)
7050#define PWM_CAPCTL_FCRLDEN1_Pos (25)
7051#define PWM_CAPCTL_FCRLDEN1_Msk (0x1ul << PWM_CAPCTL_FCRLDEN1_Pos)
7053#define PWM_CAPCTL_FCRLDEN2_Pos (26)
7054#define PWM_CAPCTL_FCRLDEN2_Msk (0x1ul << PWM_CAPCTL_FCRLDEN2_Pos)
7056#define PWM_CAPCTL_FCRLDEN3_Pos (27)
7057#define PWM_CAPCTL_FCRLDEN3_Msk (0x1ul << PWM_CAPCTL_FCRLDEN3_Pos)
7059#define PWM_CAPCTL_FCRLDEN4_Pos (28)
7060#define PWM_CAPCTL_FCRLDEN4_Msk (0x1ul << PWM_CAPCTL_FCRLDEN4_Pos)
7062#define PWM_CAPCTL_FCRLDEN5_Pos (29)
7063#define PWM_CAPCTL_FCRLDEN5_Msk (0x1ul << PWM_CAPCTL_FCRLDEN5_Pos)
7065#define PWM_CAPSTS_CRLIFOVn_Pos (0)
7066#define PWM_CAPSTS_CRLIFOVn_Msk (0x3ful << PWM_CAPSTS_CRLIFOVn_Pos)
7068#define PWM_CAPSTS_CRLIFOV0_Pos (0)
7069#define PWM_CAPSTS_CRLIFOV0_Msk (0x1ul << PWM_CAPSTS_CRLIFOV0_Pos)
7071#define PWM_CAPSTS_CRLIFOV1_Pos (1)
7072#define PWM_CAPSTS_CRLIFOV1_Msk (0x1ul << PWM_CAPSTS_CRLIFOV1_Pos)
7074#define PWM_CAPSTS_CRLIFOV2_Pos (2)
7075#define PWM_CAPSTS_CRLIFOV2_Msk (0x1ul << PWM_CAPSTS_CRLIFOV2_Pos)
7077#define PWM_CAPSTS_CRLIFOV3_Pos (3)
7078#define PWM_CAPSTS_CRLIFOV3_Msk (0x1ul << PWM_CAPSTS_CRLIFOV3_Pos)
7080#define PWM_CAPSTS_CRLIFOV4_Pos (4)
7081#define PWM_CAPSTS_CRLIFOV4_Msk (0x1ul << PWM_CAPSTS_CRLIFOV4_Pos)
7083#define PWM_CAPSTS_CRLIFOV5_Pos (5)
7084#define PWM_CAPSTS_CRLIFOV5_Msk (0x1ul << PWM_CAPSTS_CRLIFOV5_Pos)
7086#define PWM_CAPSTS_CFLIFOVn_Pos (8)
7087#define PWM_CAPSTS_CFLIFOVn_Msk (0x3ful << PWM_CAPSTS_CFLIFOVn_Pos)
7089#define PWM_CAPSTS_CFLIFOV0_Pos (8)
7090#define PWM_CAPSTS_CFLIFOV0_Msk (0x1ul << PWM_CAPSTS_CFLIFOV0_Pos)
7092#define PWM_CAPSTS_CFLIFOV1_Pos (9)
7093#define PWM_CAPSTS_CFLIFOV1_Msk (0x1ul << PWM_CAPSTS_CFLIFOV1_Pos)
7095#define PWM_CAPSTS_CFLIFOV2_Pos (10)
7096#define PWM_CAPSTS_CFLIFOV2_Msk (0x1ul << PWM_CAPSTS_CFLIFOV2_Pos)
7098#define PWM_CAPSTS_CFLIFOV3_Pos (11)
7099#define PWM_CAPSTS_CFLIFOV3_Msk (0x1ul << PWM_CAPSTS_CFLIFOV3_Pos)
7101#define PWM_CAPSTS_CFLIFOV4_Pos (12)
7102#define PWM_CAPSTS_CFLIFOV4_Msk (0x1ul << PWM_CAPSTS_CFLIFOV4_Pos)
7104#define PWM_CAPSTS_CFLIFOV5_Pos (13)
7105#define PWM_CAPSTS_CFLIFOV5_Msk (0x1ul << PWM_CAPSTS_CFLIFOV5_Pos)
7107#define PWM_RCAPDAT0_RCAPDAT_Pos (0)
7108#define PWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT0_RCAPDAT_Pos)
7110#define PWM_FCAPDAT0_FCAPDAT_Pos (0)
7111#define PWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT0_FCAPDAT_Pos)
7113#define PWM_RCAPDAT1_RCAPDAT_Pos (0)
7114#define PWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT1_RCAPDAT_Pos)
7116#define PWM_FCAPDAT1_FCAPDAT_Pos (0)
7117#define PWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT1_FCAPDAT_Pos)
7119#define PWM_RCAPDAT2_RCAPDAT_Pos (0)
7120#define PWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT2_RCAPDAT_Pos)
7122#define PWM_FCAPDAT2_FCAPDAT_Pos (0)
7123#define PWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT2_FCAPDAT_Pos)
7125#define PWM_RCAPDAT3_RCAPDAT_Pos (0)
7126#define PWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT3_RCAPDAT_Pos)
7128#define PWM_FCAPDAT3_FCAPDAT_Pos (0)
7129#define PWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT3_FCAPDAT_Pos)
7131#define PWM_RCAPDAT4_RCAPDAT_Pos (0)
7132#define PWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT4_RCAPDAT_Pos)
7134#define PWM_FCAPDAT4_FCAPDAT_Pos (0)
7135#define PWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT4_FCAPDAT_Pos)
7137#define PWM_RCAPDAT5_RCAPDAT_Pos (0)
7138#define PWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT5_RCAPDAT_Pos)
7140#define PWM_FCAPDAT5_FCAPDAT_Pos (0)
7141#define PWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT5_FCAPDAT_Pos)
7143#define PWM_PDMACTL_CHEN0_1_Pos (0)
7144#define PWM_PDMACTL_CHEN0_1_Msk (0x1ul << PWM_PDMACTL_CHEN0_1_Pos)
7146#define PWM_PDMACTL_CAPMOD0_1_Pos (1)
7147#define PWM_PDMACTL_CAPMOD0_1_Msk (0x3ul << PWM_PDMACTL_CAPMOD0_1_Pos)
7149#define PWM_PDMACTL_CAPORD0_1_Pos (3)
7150#define PWM_PDMACTL_CAPORD0_1_Msk (0x1ul << PWM_PDMACTL_CAPORD0_1_Pos)
7152#define PWM_PDMACTL_CHSEL0_1_Pos (4)
7153#define PWM_PDMACTL_CHSEL0_1_Msk (0x1ul << PWM_PDMACTL_CHSEL0_1_Pos)
7155#define PWM_PDMACTL_CHEN2_3_Pos (8)
7156#define PWM_PDMACTL_CHEN2_3_Msk (0x1ul << PWM_PDMACTL_CHEN2_3_Pos)
7158#define PWM_PDMACTL_CAPMOD2_3_Pos (9)
7159#define PWM_PDMACTL_CAPMOD2_3_Msk (0x3ul << PWM_PDMACTL_CAPMOD2_3_Pos)
7161#define PWM_PDMACTL_CAPORD2_3_Pos (11)
7162#define PWM_PDMACTL_CAPORD2_3_Msk (0x1ul << PWM_PDMACTL_CAPORD2_3_Pos)
7164#define PWM_PDMACTL_CHSEL2_3_Pos (12)
7165#define PWM_PDMACTL_CHSEL2_3_Msk (0x1ul << PWM_PDMACTL_CHSEL2_3_Pos)
7167#define PWM_PDMACTL_CHEN4_5_Pos (16)
7168#define PWM_PDMACTL_CHEN4_5_Msk (0x1ul << PWM_PDMACTL_CHEN4_5_Pos)
7170#define PWM_PDMACTL_CAPMOD4_5_Pos (17)
7171#define PWM_PDMACTL_CAPMOD4_5_Msk (0x3ul << PWM_PDMACTL_CAPMOD4_5_Pos)
7173#define PWM_PDMACTL_CAPORD4_5_Pos (19)
7174#define PWM_PDMACTL_CAPORD4_5_Msk (0x1ul << PWM_PDMACTL_CAPORD4_5_Pos)
7176#define PWM_PDMACTL_CHSEL4_5_Pos (20)
7177#define PWM_PDMACTL_CHSEL4_5_Msk (0x1ul << PWM_PDMACTL_CHSEL4_5_Pos)
7179#define PWM_PDMACAP0_1_CAPBUF_Pos (0)
7180#define PWM_PDMACAP0_1_CAPBUF_Msk (0xfffful << PWM_PDMACAP0_1_CAPBUF_Pos)
7182#define PWM_PDMACAP2_3_CAPBUF_Pos (0)
7183#define PWM_PDMACAP2_3_CAPBUF_Msk (0xfffful << PWM_PDMACAP2_3_CAPBUF_Pos)
7185#define PWM_PDMACAP4_5_CAPBUF_Pos (0)
7186#define PWM_PDMACAP4_5_CAPBUF_Msk (0xfffful << PWM_PDMACAP4_5_CAPBUF_Pos)
7188#define PWM_CAPIEN_CAPRIENn_Pos (0)
7189#define PWM_CAPIEN_CAPRIENn_Msk (0x3ful << PWM_CAPIEN_CAPRIENn_Pos)
7191#define PWM_CAPIEN_CAPRIEN0_Pos (0)
7192#define PWM_CAPIEN_CAPRIEN0_Msk (0x1ul << PWM_CAPIEN_CAPRIEN0_Pos)
7194#define PWM_CAPIEN_CAPRIEN1_Pos (1)
7195#define PWM_CAPIEN_CAPRIEN1_Msk (0x1ul << PWM_CAPIEN_CAPRIEN1_Pos)
7197#define PWM_CAPIEN_CAPRIEN2_Pos (2)
7198#define PWM_CAPIEN_CAPRIEN2_Msk (0x1ul << PWM_CAPIEN_CAPRIEN2_Pos)
7200#define PWM_CAPIEN_CAPRIEN3_Pos (3)
7201#define PWM_CAPIEN_CAPRIEN3_Msk (0x1ul << PWM_CAPIEN_CAPRIEN3_Pos)
7203#define PWM_CAPIEN_CAPRIEN4_Pos (4)
7204#define PWM_CAPIEN_CAPRIEN4_Msk (0x1ul << PWM_CAPIEN_CAPRIEN4_Pos)
7206#define PWM_CAPIEN_CAPRIEN5_Pos (5)
7207#define PWM_CAPIEN_CAPRIEN5_Msk (0x1ul << PWM_CAPIEN_CAPRIEN5_Pos)
7209#define PWM_CAPIEN_CAPFIENn_Pos (8)
7210#define PWM_CAPIEN_CAPFIENn_Msk (0x3ful << PWM_CAPIEN_CAPFIENn_Pos)
7212#define PWM_CAPIEN_CAPFIEN0_Pos (8)
7213#define PWM_CAPIEN_CAPFIEN0_Msk (0x1ul << PWM_CAPIEN_CAPFIEN0_Pos)
7215#define PWM_CAPIEN_CAPFIEN1_Pos (9)
7216#define PWM_CAPIEN_CAPFIEN1_Msk (0x1ul << PWM_CAPIEN_CAPFIEN1_Pos)
7218#define PWM_CAPIEN_CAPFIEN2_Pos (10)
7219#define PWM_CAPIEN_CAPFIEN2_Msk (0x1ul << PWM_CAPIEN_CAPFIEN2_Pos)
7221#define PWM_CAPIEN_CAPFIEN3_Pos (11)
7222#define PWM_CAPIEN_CAPFIEN3_Msk (0x1ul << PWM_CAPIEN_CAPFIEN3_Pos)
7224#define PWM_CAPIEN_CAPFIEN4_Pos (12)
7225#define PWM_CAPIEN_CAPFIEN4_Msk (0x1ul << PWM_CAPIEN_CAPFIEN4_Pos)
7227#define PWM_CAPIEN_CAPFIEN5_Pos (13)
7228#define PWM_CAPIEN_CAPFIEN5_Msk (0x1ul << PWM_CAPIEN_CAPFIEN5_Pos)
7230#define PWM_CAPIF_CRLIFn_Pos (0)
7231#define PWM_CAPIF_CRLIFn_Msk (0x3ful << PWM_CAPIF_CRLIFn_Pos)
7233#define PWM_CAPIF_CRLIF0_Pos (0)
7234#define PWM_CAPIF_CRLIF0_Msk (0x1ul << PWM_CAPIF_CRLIF0_Pos)
7236#define PWM_CAPIF_CRLIF1_Pos (1)
7237#define PWM_CAPIF_CRLIF1_Msk (0x1ul << PWM_CAPIF_CRLIF1_Pos)
7239#define PWM_CAPIF_CRLIF2_Pos (2)
7240#define PWM_CAPIF_CRLIF2_Msk (0x1ul << PWM_CAPIF_CRLIF2_Pos)
7242#define PWM_CAPIF_CRLIF3_Pos (3)
7243#define PWM_CAPIF_CRLIF3_Msk (0x1ul << PWM_CAPIF_CRLIF3_Pos)
7245#define PWM_CAPIF_CRLIF4_Pos (4)
7246#define PWM_CAPIF_CRLIF4_Msk (0x1ul << PWM_CAPIF_CRLIF4_Pos)
7248#define PWM_CAPIF_CRLIF5_Pos (5)
7249#define PWM_CAPIF_CRLIF5_Msk (0x1ul << PWM_CAPIF_CRLIF5_Pos)
7251#define PWM_CAPIF_CFLIFn_Pos (8)
7252#define PWM_CAPIF_CFLIFn_Msk (0x3ful << PWM_CAPIF_CFLIFn_Pos)
7254#define PWM_CAPIF_CFLIF0_Pos (8)
7255#define PWM_CAPIF_CFLIF0_Msk (0x1ul << PWM_CAPIF_CFLIF0_Pos)
7257#define PWM_CAPIF_CFLIF1_Pos (9)
7258#define PWM_CAPIF_CFLIF1_Msk (0x1ul << PWM_CAPIF_CFLIF1_Pos)
7260#define PWM_CAPIF_CFLIF2_Pos (10)
7261#define PWM_CAPIF_CFLIF2_Msk (0x1ul << PWM_CAPIF_CFLIF2_Pos)
7263#define PWM_CAPIF_CFLIF3_Pos (11)
7264#define PWM_CAPIF_CFLIF3_Msk (0x1ul << PWM_CAPIF_CFLIF3_Pos)
7266#define PWM_CAPIF_CFLIF4_Pos (12)
7267#define PWM_CAPIF_CFLIF4_Msk (0x1ul << PWM_CAPIF_CFLIF4_Pos)
7269#define PWM_CAPIF_CFLIF5_Pos (13)
7270#define PWM_CAPIF_CFLIF5_Msk (0x1ul << PWM_CAPIF_CFLIF5_Pos)
7272#define PWM_PBUF_PBUF_Pos (0)
7273#define PWM_PBUF_PBUF_Msk (0xfffful << PWM_PBUF_PBUF_Pos)
7275#define PWM_CMPBUF_CMPBUF_Pos (0)
7276#define PWM_CMPBUF_CMPBUF_Msk (0xfffful << PWM_CMPBUF_CMPBUF_Pos)
7278#define PWM_FTCBUF0_1_FTCMPBUF_Pos (0)
7279#define PWM_FTCBUF0_1_FTCMPBUF_Msk (0xfffful << PWM_FTCBUF0_1_FTCMPBUF_Pos)
7281#define PWM_FTCBUF2_3_FTCMPBUF_Pos (0)
7282#define PWM_FTCBUF2_3_FTCMPBUF_Msk (0xfffful << PWM_FTCBUF2_3_FTCMPBUF_Pos)
7284#define PWM_FTCBUF4_5_FTCMPBUF_Pos (0)
7285#define PWM_FTCBUF4_5_FTCMPBUF_Msk (0xfffful << PWM_FTCBUF4_5_FTCMPBUF_Pos)
7287#define PWM_FTCI_FTCMUn_Pos (0)
7288#define PWM_FTCI_FTCMUn_Msk (0x7ul << PWM_FTCI_FTCMUn_Pos)
7290#define PWM_FTCI_FTCMU0_Pos (0)
7291#define PWM_FTCI_FTCMU0_Msk (0x1ul << PWM_FTCI_FTCMU0_Pos)
7293#define PWM_FTCI_FTCMU2_Pos (1)
7294#define PWM_FTCI_FTCMU2_Msk (0x1ul << PWM_FTCI_FTCMU2_Pos)
7296#define PWM_FTCI_FTCMU4_Pos (2)
7297#define PWM_FTCI_FTCMU4_Msk (0x1ul << PWM_FTCI_FTCMU4_Pos)
7299#define PWM_FTCI_FTCMDn_Pos (8)
7300#define PWM_FTCI_FTCMDn_Msk (0x7ul << PWM_FTCI_FTCMDn_Pos)
7302#define PWM_FTCI_FTCMD0_Pos (8)
7303#define PWM_FTCI_FTCMD0_Msk (0x1ul << PWM_FTCI_FTCMD0_Pos)
7305#define PWM_FTCI_FTCMD2_Pos (9)
7306#define PWM_FTCI_FTCMD2_Msk (0x1ul << PWM_FTCI_FTCMD2_Pos)
7308#define PWM_FTCI_FTCMD4_Pos (10)
7309#define PWM_FTCI_FTCMD4_Msk (0x1ul << PWM_FTCI_FTCMD4_Pos) /* PWM_CONST */ /* end of PWM register group */
7313
7314
7315/*---------------------- Real Time Clock Controller -------------------------*/
7322typedef struct
7323{
7324
7325
7326
7327
7637 __IO uint32_t INIT; /* Offset: 0x00 RTC Initiation Register */
7638 __O uint32_t RWEN; /* Offset: 0x04 RTC Access Enable Register */
7639 __IO uint32_t FREQADJ; /* Offset: 0x08 RTC Frequency Compensation Register */
7640 __IO uint32_t TIME; /* Offset: 0x0C Time Loading Register */
7641 __IO uint32_t CAL; /* Offset: 0x10 RTC Calendar Loading Register */
7642 __IO uint32_t CLKFMT; /* Offset: 0x14 Time Scale Selection Register */
7643 __IO uint32_t WEEKDAY; /* Offset: 0x18 Day of the Week Register */
7644 __IO uint32_t TALM; /* Offset: 0x1C Time Alarm Register */
7645 __IO uint32_t CALM; /* Offset: 0x20 Calendar Alarm Register */
7646 __I uint32_t LEAPYEAR; /* Offset: 0x24 RTC Leap Year Indicator Register */
7647 __IO uint32_t INTEN; /* Offset: 0x28 RTC Interrupt Enable Register */
7648 __IO uint32_t INTSTS; /* Offset: 0x2C RTC Interrupt Indicator Register */
7649 __IO uint32_t TICK; /* Offset: 0x30 RTC Time Tick Register */
7650 __IO uint32_t TAMSK; /* Offset: 0x34 Time Alarm Mask Register */
7651 __IO uint32_t CAMSK; /* Offset: 0x38 Calendar Alarm Mask Register */
7652 __IO uint32_t SPRCTL; /* Offset: 0x3C RTC Spare Functional Control Register */
7653 __IO uint32_t SPR[20]; /* Offset: 0x40 ~ 0x8C RTC Spare Register 0 ~ 19 */
7654 __I uint32_t RESERVE0[28];
7655 __IO uint32_t LXTCTL; /* Offset: 0x100 RTC 32.768 kHz Oscillator Control Register */
7656 __IO uint32_t LXTOCTL; /* Offset: 0x104 X32KO Pin Control Register */
7657 __IO uint32_t LXTICTL; /* Offset: 0x108 X32KI Pin Control Register */
7658 __IO uint32_t TAMPCTL; /* Offset: 0x10C TAMPER Pin Control Register */
7659
7660} RTC_T;
7661
7662
7663
7669#define RTC_INIT_ACTIVE_Pos (0)
7670#define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos)
7672#define RTC_INIT_INIT_Pos (0)
7673#define RTC_INIT_INIT_Msk (0xfffffffful << RTC_INIT_INIT_Pos)
7675#define RTC_RWEN_RWEN_Pos (0)
7676#define RTC_RWEN_RWEN_Msk (0xfffful << RTC_RWEN_RWEN_Pos)
7678#define RTC_RWEN_RWENF_Pos (16)
7679#define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos)
7681#define RTC_FREQADJ_FRACTION_Pos (0)
7682#define RTC_FREQADJ_FRACTION_Msk (0x3ful << RTC_FREQADJ_FRACTION_Pos)
7684#define RTC_FREQADJ_INTEGER_Pos (8)
7685#define RTC_FREQADJ_INTEGER_Msk (0xful << RTC_FREQADJ_INTEGER_Pos)
7687#define RTC_TIME_SEC_Pos (0)
7688#define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos)
7690#define RTC_TIME_TENSEC_Pos (4)
7691#define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos)
7693#define RTC_TIME_MIN_Pos (8)
7694#define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos)
7696#define RTC_TIME_TENMIN_Pos (12)
7697#define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos)
7699#define RTC_TIME_HR_Pos (16)
7700#define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos)
7702#define RTC_TIME_TENHR_Pos (20)
7703#define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos)
7705#define RTC_CAL_DAY_Pos (0)
7706#define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos)
7708#define RTC_CAL_TENDAY_Pos (4)
7709#define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos)
7711#define RTC_CAL_MON_Pos (8)
7712#define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos)
7714#define RTC_CAL_TENMON_Pos (12)
7715#define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos)
7717#define RTC_CAL_YEAR_Pos (16)
7718#define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos)
7720#define RTC_CAL_TENYEAR_Pos (20)
7721#define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos)
7723#define RTC_CLKFMT_24HEN_Pos (0)
7724#define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos)
7726#define RTC_WEEKDAY_WEEKDAY_Pos (0)
7727#define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos)
7729#define RTC_TALM_SEC_Pos (0)
7730#define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos)
7732#define RTC_TALM_TENSEC_Pos (4)
7733#define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos)
7735#define RTC_TALM_MIN_Pos (8)
7736#define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos)
7738#define RTC_TALM_TENMIN_Pos (12)
7739#define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos)
7741#define RTC_TALM_HR_Pos (16)
7742#define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos)
7744#define RTC_TALM_TENHR_Pos (20)
7745#define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos)
7747#define RTC_CALM_DAY_Pos (0)
7748#define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos)
7750#define RTC_CALM_TENDAY_Pos (4)
7751#define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos)
7753#define RTC_CALM_MON_Pos (8)
7754#define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos)
7756#define RTC_CALM_TENMON_Pos (12)
7757#define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos)
7759#define RTC_CALM_YEAR_Pos (16)
7760#define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos)
7762#define RTC_CALM_TENYEAR_Pos (20)
7763#define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos)
7765#define RTC_LEAPYEAR_LEAPYEAR_Pos (0)
7766#define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos)
7768#define RTC_INTEN_ALMIEN_Pos (0)
7769#define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos)
7771#define RTC_INTEN_TICKIEN_Pos (1)
7772#define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos)
7774#define RTC_INTEN_SNPDIEN_Pos (2)
7775#define RTC_INTEN_SNPDIEN_Msk (0x1ul << RTC_INTEN_SNPDIEN_Pos)
7777#define RTC_INTSTS_ALMIF_Pos (0)
7778#define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos)
7780#define RTC_INTSTS_TICKIF_Pos (1)
7781#define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos)
7783#define RTC_INTSTS_SNPDIF_Pos (2)
7784#define RTC_INTSTS_SNPDIF_Msk (0x1ul << RTC_INTSTS_SNPDIF_Pos)
7786#define RTC_TICK_TICK_Pos (0)
7787#define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos)
7789#define RTC_TAMSK_MSEC_Pos (0)
7790#define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos)
7792#define RTC_TAMSK_MTENSEC_Pos (1)
7793#define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos)
7795#define RTC_TAMSK_MMIN_Pos (2)
7796#define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos)
7798#define RTC_TAMSK_MTENMIN_Pos (3)
7799#define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos)
7801#define RTC_TAMSK_MHR_Pos (4)
7802#define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos)
7804#define RTC_TAMSK_MTENHR_Pos (5)
7805#define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos)
7807#define RTC_CAMSK_MDAY_Pos (0)
7808#define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos)
7810#define RTC_CAMSK_MTENDAY_Pos (1)
7811#define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos)
7813#define RTC_CAMSK_MMON_Pos (2)
7814#define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos)
7816#define RTC_CAMSK_MTENMON_Pos (3)
7817#define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos)
7819#define RTC_CAMSK_MYEAR_Pos (4)
7820#define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos)
7822#define RTC_CAMSK_MTENYEAR_Pos (5)
7823#define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos)
7825#define RTC_SPRCTL_SNPDEN_Pos (0)
7826#define RTC_SPRCTL_SNPDEN_Msk (0x1ul << RTC_SPRCTL_SNPDEN_Pos)
7828#define RTC_SPRCTL_SNPTYPE0_Pos (1)
7829#define RTC_SPRCTL_SNPTYPE0_Msk (0x1ul << RTC_SPRCTL_SNPTYPE0_Pos)
7831#define RTC_SPRCTL_SPRRWEN_Pos (2)
7832#define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos)
7834#define RTC_SPRCTL_SNPTYPE1_Pos (3)
7835#define RTC_SPRCTL_SNPTYPE1_Msk (0x1ul << RTC_SPRCTL_SNPTYPE1_Pos)
7837#define RTC_SPRCTL_SPRCSTS_Pos (5)
7838#define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos)
7840#define RTC_SPRCTL_SPRRWRDY_Pos (7)
7841#define RTC_SPRCTL_SPRRWRDY_Msk (0x1ul << RTC_SPRCTL_SPRRWRDY_Pos)
7843#define RTC_SPR_SPARE_Pos (0)
7844#define RTC_SPR_SPARE_Msk (0xfffffffful << RTC_SPR_SPARE_Pos)
7846#define RTC_LXTCTL_LXTEN_Pos (0)
7847#define RTC_LXTCTL_LXTEN_Msk (0x1ul << RTC_LXTCTL_LXTEN_Pos)
7849#define RTC_LXTCTL_GAIN_Pos (1)
7850#define RTC_LXTCTL_GAIN_Msk (0x7ul << RTC_LXTCTL_GAIN_Pos)
7852#define RTC_LXTOCTL_OPMODE_Pos (0)
7853#define RTC_LXTOCTL_OPMODE_Msk (0x3ul << RTC_LXTOCTL_OPMODE_Pos)
7855#define RTC_LXTOCTL_DOUT_Pos (2)
7856#define RTC_LXTOCTL_DOUT_Msk (0x1ul << RTC_LXTOCTL_DOUT_Pos)
7858#define RTC_LXTOCTL_CTLSEL_Pos (3)
7859#define RTC_LXTOCTL_CTLSEL_Msk (0x1ul << RTC_LXTOCTL_CTLSEL_Pos)
7861#define RTC_LXTICTL_OPMODE_Pos (0)
7862#define RTC_LXTICTL_OPMODE_Msk (0x3ul << RTC_LXTICTL_OPMODE_Pos)
7864#define RTC_LXTICTL_DOUT_Pos (2)
7865#define RTC_LXTICTL_DOUT_Msk (0x1ul << RTC_LXTICTL_DOUT_Pos)
7867#define RTC_LXTICTL_CTLSEL_Pos (3)
7868#define RTC_LXTICTL_CTLSEL_Msk (0x1ul << RTC_LXTICTL_CTLSEL_Pos)
7870#define RTC_TAMPCTL_OPMODE_Pos (0)
7871#define RTC_TAMPCTL_OPMODE_Msk (0x3ul << RTC_TAMPCTL_OPMODE_Pos)
7873#define RTC_TAMPCTL_DOUT_Pos (2)
7874#define RTC_TAMPCTL_DOUT_Msk (0x1ul << RTC_TAMPCTL_DOUT_Pos)
7876#define RTC_TAMPCTL_CTLSEL_Pos (3)
7877#define RTC_TAMPCTL_CTLSEL_Msk (0x1ul << RTC_TAMPCTL_CTLSEL_Pos) /* RTC_CONST */ /* end of RTC register group */
7881
7882
7883/*---------------------- Smart Card Host Interface Controller -------------------------*/
7890typedef struct
7891{
7892
7893
8492 __IO uint32_t DAT; /* Offset: 0x00 SC Receiving/Transmit Holding Buffer Register. */
8493 __IO uint32_t CTL; /* Offset: 0x04 SC Control Register. */
8494 __IO uint32_t ALTCTL; /* Offset: 0x08 SC Alternate Control Register. */
8495 __IO uint32_t EGT; /* Offset: 0x0C SC Extend Guard Time Register. */
8496 __IO uint32_t RXTOUT; /* Offset: 0x10 SC Receive buffer Time-out Register. */
8497 __IO uint32_t ETUCTL; /* Offset: 0x14 SC ETU Control Register. */
8498 __IO uint32_t INTEN; /* Offset: 0x18 SC Interrupt Enable Control Register. */
8499 __IO uint32_t INTSTS; /* Offset: 0x1C SC Interrupt Status Register. */
8500 __IO uint32_t STATUS; /* Offset: 0x20 SC Status Register. */
8501 __IO uint32_t PINCTL; /* Offset: 0x24 SC Pin Control State Register. */
8502 __IO uint32_t TMRCTL0; /* Offset: 0x28 SC Internal Timer Control Register 0. */
8503 __IO uint32_t TMRCTL1; /* Offset: 0x2C SC Internal Timer Control Register 1. */
8504 __IO uint32_t TMRCTL2; /* Offset: 0x30 SC Internal Timer Control Register 2. */
8505 __IO uint32_t UARTCTL; /* Offset: 0x34 SC UART Mode Control Register. */
8506 __I uint32_t TMRDAT0; /* Offset: 0x38 SC Timer Current Data Register A. */
8507 __I uint32_t TMRDAT1_2; /* Offset: 0x3C SC Timer Current Data Register B. */
8508
8509} SC_T;
8510
8511
8512
8518#define SC_DAT_DAT_Pos (0)
8519#define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos)
8521#define SC_CTL_SCEN_Pos (0)
8522#define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos)
8524#define SC_CTL_RXOFF_Pos (1)
8525#define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos)
8527#define SC_CTL_TXOFF_Pos (2)
8528#define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos)
8530#define SC_CTL_AUTOCEN_Pos (3)
8531#define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos)
8533#define SC_CTL_CONSEL_Pos (4)
8534#define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos)
8536#define SC_CTL_RXTRGLV_Pos (6)
8537#define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos)
8539#define SC_CTL_BGT_Pos (8)
8540#define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos)
8542#define SC_CTL_TMRSEL_Pos (13)
8543#define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos)
8545#define SC_CTL_NSB_Pos (15)
8546#define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos)
8548#define SC_CTL_RXRTY_Pos (16)
8549#define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos)
8551#define SC_CTL_RXRTYEN_Pos (19)
8552#define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos)
8554#define SC_CTL_TXRTY_Pos (20)
8555#define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos)
8557#define SC_CTL_TXRTYEN_Pos (23)
8558#define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos)
8560#define SC_CTL_CDDBSEL_Pos (24)
8561#define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos)
8563#define SC_CTL_CDLV_Pos (26)
8564#define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos)
8566#define SC_CTL_SYNC_Pos (30)
8567#define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos)
8569#define SC_CTL_ICEDEBUG_Pos (31)
8570#define SC_CTL_ICEDEBUG_Msk (0x1ul << SC_CTL_ICEDEBUG_Pos)
8572#define SC_ALTCTL_TXRST_Pos (0)
8573#define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos)
8575#define SC_ALTCTL_RXRST_Pos (1)
8576#define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos)
8578#define SC_ALTCTL_DACTEN_Pos (2)
8579#define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos)
8581#define SC_ALTCTL_ACTEN_Pos (3)
8582#define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos)
8584#define SC_ALTCTL_WARSTEN_Pos (4)
8585#define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos)
8587#define SC_ALTCTL_CNTEN0_Pos (5)
8588#define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos)
8590#define SC_ALTCTL_CNTEN1_Pos (6)
8591#define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos)
8593#define SC_ALTCTL_CNTEN2_Pos (7)
8594#define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos)
8596#define SC_ALTCTL_INITSEL_Pos (8)
8597#define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos)
8599#define SC_ALTCTL_ADACEN_Pos (11)
8600#define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos)
8602#define SC_ALTCTL_RXBGTEN_Pos (12)
8603#define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos)
8605#define SC_ALTCTL_ACTSTS0_Pos (13)
8606#define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos)
8608#define SC_ALTCTL_ACTSTS1_Pos (14)
8609#define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos)
8611#define SC_ALTCTL_ACTSTS2_Pos (15)
8612#define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos)
8614#define SC_ALTCTL_OUTSEL_Pos (16)
8615#define SC_ALTCTL_OUTSEL_Msk (0x1ul << SC_ALTCTL_OUTSEL_Pos)
8617#define SC_EGT_EGT_Pos (0)
8618#define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos)
8620#define SC_RXTOUT_RFTM_Pos (0)
8621#define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos)
8623#define SC_ETUCTL_ETURDIV_Pos (0)
8624#define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos)
8626#define SC_ETUCTL_CMPEN_Pos (15)
8627#define SC_ETUCTL_CMPEN_Msk (0x1ul << SC_ETUCTL_CMPEN_Pos)
8629#define SC_INTEN_RDAIEN_Pos (0)
8630#define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos)
8632#define SC_INTEN_TBEIEN_Pos (1)
8633#define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos)
8635#define SC_INTEN_TERRIEN_Pos (2)
8636#define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos)
8638#define SC_INTEN_TMR0IEN_Pos (3)
8639#define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos)
8641#define SC_INTEN_TMR1IEN_Pos (4)
8642#define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos)
8644#define SC_INTEN_TMR2IEN_Pos (5)
8645#define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos)
8647#define SC_INTEN_BGTIEN_Pos (6)
8648#define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos)
8650#define SC_INTEN_CDIEN_Pos (7)
8651#define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos)
8653#define SC_INTEN_INITIEN_Pos (8)
8654#define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos)
8656#define SC_INTEN_RXTOIF_Pos (9)
8657#define SC_INTEN_RXTOIF_Msk (0x1ul << SC_INTEN_RXTOIF_Pos)
8659#define SC_INTEN_ACERRIEN_Pos (10)
8660#define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos)
8662#define SC_INTSTS_RDAIF_Pos (0)
8663#define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos)
8665#define SC_INTSTS_TBEIF_Pos (1)
8666#define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos)
8668#define SC_INTSTS_TERRIF_Pos (2)
8669#define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos)
8671#define SC_INTSTS_TMR0IF_Pos (3)
8672#define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos)
8674#define SC_INTSTS_TMR1IF_Pos (4)
8675#define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos)
8677#define SC_INTSTS_TMR2IF_Pos (5)
8678#define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos)
8680#define SC_INTSTS_BGTIF_Pos (6)
8681#define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos)
8683#define SC_INTSTS_CDIF_Pos (7)
8684#define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos)
8686#define SC_INTSTS_INITIF_Pos (8)
8687#define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos)
8689#define SC_INTSTS_RBTOIF_Pos (9)
8690#define SC_INTSTS_RBTOIF_Msk (0x1ul << SC_INTSTS_RBTOIF_Pos)
8692#define SC_INTSTS_ACERRIF_Pos (10)
8693#define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos)
8695#define SC_STATUS_RXOV_Pos (0)
8696#define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos)
8698#define SC_STATUS_RXEMPTY_Pos (1)
8699#define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos)
8701#define SC_STATUS_RXFULL_Pos (2)
8702#define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos)
8704#define SC_STATUS_PEF_Pos (4)
8705#define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos)
8707#define SC_STATUS_FEF_Pos (5)
8708#define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos)
8710#define SC_STATUS_BEF_Pos (6)
8711#define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos)
8713#define SC_STATUS_TXOV_Pos (8)
8714#define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos)
8716#define SC_STATUS_TXEMPTY_Pos (9)
8717#define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos)
8719#define SC_STATUS_TXFULL_Pos (10)
8720#define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos)
8722#define SC_STATUS_CREMOVE_Pos (11)
8723#define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos)
8725#define SC_STATUS_CINSERT_Pos (12)
8726#define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos)
8728#define SC_STATUS_CDPINSTS_Pos (13)
8729#define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos)
8731#define SC_STATUS_RXPOINT_Pos (16)
8732#define SC_STATUS_RXPOINT_Msk (0x3ul << SC_STATUS_RXPOINT_Pos)
8734#define SC_STATUS_RXRERR_Pos (21)
8735#define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos)
8737#define SC_STATUS_RXOVERR_Pos (22)
8738#define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos)
8740#define SC_STATUS_RXACT_Pos (23)
8741#define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos)
8743#define SC_STATUS_TXPOINT_Pos (24)
8744#define SC_STATUS_TXPOINT_Msk (0x3ul << SC_STATUS_TXPOINT_Pos)
8746#define SC_STATUS_TXRERR_Pos (29)
8747#define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos)
8749#define SC_STATUS_TXOVERR_Pos (30)
8750#define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos)
8752#define SC_STATUS_TXACT_Pos (31)
8753#define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos)
8755#define SC_PINCTL_PWREN_Pos (0)
8756#define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos)
8758#define SC_PINCTL_SCRST_Pos (1)
8759#define SC_PINCTL_SCRST_Msk (0x1ul << SC_PINCTL_SCRST_Pos)
8761#define SC_PINCTL_CSTOPLV_Pos (5)
8762#define SC_PINCTL_CSTOPLV_Msk (0x1ul << SC_PINCTL_CSTOPLV_Pos)
8764#define SC_PINCTL_CLKKEEP_Pos (6)
8765#define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos)
8767#define SC_PINCTL_SCDOUT_Pos (9)
8768#define SC_PINCTL_SCDOUT_Msk (0x1ul << SC_PINCTL_SCDOUT_Pos)
8770#define SC_PINCTL_PWRINV_Pos (11)
8771#define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos)
8773#define SC_PINCTL_SCDOSTS_Pos (12)
8774#define SC_PINCTL_SCDOSTS_Msk (0x1ul << SC_PINCTL_SCDOSTS_Pos)
8776#define SC_PINCTL_DATSTS_Pos (16)
8777#define SC_PINCTL_DATSTS_Msk (0x1ul << SC_PINCTL_DATSTS_Pos)
8779#define SC_PINCTL_PWRSTS_Pos (17)
8780#define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos)
8782#define SC_PINCTL_RSTSTS_Pos (18)
8783#define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos)
8785#define SC_PINCTL_SYNC_Pos (30)
8786#define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos)
8788#define SC_PINCTL_LOOPBK_Pos (31)
8789#define SC_PINCTL_LOOPBK_Msk (0x1ul << SC_PINCTL_LOOPBK_Pos)
8791#define SC_TMRCTL0_CNT_Pos (0)
8792#define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos)
8794#define SC_TMRCTL0_OPMODE_Pos (24)
8795#define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos)
8797#define SC_TMRCTL1_CNT_Pos (0)
8798#define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos)
8800#define SC_TMRCTL1_OPMODE_Pos (24)
8801#define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos)
8803#define SC_TMRCTL2_CNT_Pos (0)
8804#define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos)
8806#define SC_TMRCTL2_OPMODE_Pos (24)
8807#define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos)
8809#define SC_UARTCTL_UARTEN_Pos (0)
8810#define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos)
8812#define SC_UARTCTL_WLS_Pos (4)
8813#define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS10_Pos)
8815#define SC_UARTCTL_PBOFF_Pos (6)
8816#define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos)
8818#define SC_UARTCTL_OPE_Pos (7)
8819#define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos)
8821#define SC_TMRDAT0_CNT0_Pos (0)
8822#define SC_TMRDAT0_CNT0_Msk (0xfffffful << SC_TMRDAT0_CNT0_Pos)
8824#define SC_TMRDAT1_2_CNT1_Pos (0)
8825#define SC_TMRDAT1_2_CNT1_Msk (0xfful << SC_TMRDAT1_2_CNT1_Pos)
8827#define SC_TMRDAT1_2_CNT2_Pos (8)
8828#define SC_TMRDAT1_2_CNT2_Msk (0xfful << SC_TMRDAT1_2_CNT2_Pos) /* SC_CONST */ /* end of SC register group */
8832
8833
8834/*---------------------- Serial Peripheral Interface Controller -------------------------*/
8841typedef struct
8842{
8843
8844
9305 __IO uint32_t CTL; /* Offset: 0x00 Control Register */
9306 __IO uint32_t CLKDIV; /* Offset: 0x04 Clock Divider Register */
9307 __IO uint32_t SSCTL; /* Offset: 0x08 Slave Select Control Register */
9308 __IO uint32_t PDMACTL; /* Offset: 0x0C SPI PDMA Control Register */
9309 __IO uint32_t FIFOCTL; /* Offset: 0x10 SPI FIFO Control Register */
9310 __IO uint32_t STATUS; /* Offset: 0x14 SPI Status Register */
9311 __I uint32_t RESERVE0[2];
9312 __O uint32_t TX; /* Offset: 0x20 Data Transmit Register */
9313 __I uint32_t RESERVE1[3];
9314 __I uint32_t RX; /* Offset: 0x30 Data Receive Register */
9315 __I uint32_t RESERVE2[11];
9316 __IO uint32_t I2SCTL; /* Offset: 0x60 I2S Control Register */
9317 __IO uint32_t I2SCLK; /* Offset: 0x64 I2S Clock Divider Control Register */
9318 __IO uint32_t I2SSTS; /* Offset: 0x68 I2S Status Register */
9319
9320} SPI_T;
9321
9322
9323
9329#define SPI_CTL_SPIEN_Pos (0)
9330#define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos)
9332#define SPI_CTL_RXNEG_Pos (1)
9333#define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos)
9335#define SPI_CTL_TXNEG_Pos (2)
9336#define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos)
9338#define SPI_CTL_CLKPOL_Pos (3)
9339#define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos)
9341#define SPI_CTL_SUSPITV_Pos (4)
9342#define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos)
9344#define SPI_CTL_DWIDTH_Pos (8)
9345#define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos)
9347#define SPI_CTL_LSB_Pos (13)
9348#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos)
9350#define SPI_CTL_TWOBIT_Pos (16)
9351#define SPI_CTL_TWOBIT_Msk (0x1ul << SPI_CTL_TWOBIT_Pos)
9353#define SPI_CTL_UNITIEN_Pos (17)
9354#define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos)
9356#define SPI_CTL_SLAVE_Pos (18)
9357#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos)
9359#define SPI_CTL_REORDER_Pos (19)
9360#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos)
9362#define SPI_CTL_QDIODIR_Pos (20)
9363#define SPI_CTL_QDIODIR_Msk (0x1ul << SPI_CTL_QDIODIR_Pos)
9365#define SPI_CTL_DUALIOEN_Pos (21)
9366#define SPI_CTL_DUALIOEN_Msk (0x1ul << SPI_CTL_DUALIOEN_Pos)
9368#define SPI_CTL_QUADIOEN_Pos (22)
9369#define SPI_CTL_QUADIOEN_Msk (0x1ul << SPI_CTL_QUADIOEN_Pos)
9371#define SPI_CLKDIV_DIVIDER_Pos (0)
9372#define SPI_CLKDIV_DIVIDER_Msk (0xfful << SPI_CLKDIV_DIVIDER_Pos)
9374#define SPI_SSCTL_SS_Pos (0)
9375#define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos)
9377#define SPI_SSCTL_SSACTPOL_Pos (2)
9378#define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos)
9380#define SPI_SSCTL_AUTOSS_Pos (3)
9381#define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos)
9383#define SPI_SSCTL_SLV3WIRE_Pos (4)
9384#define SPI_SSCTL_SLV3WIRE_Msk (0x1ul << SPI_SSCTL_SLV3WIRE_Pos)
9386#define SPI_SSCTL_SLVTOIEN_Pos (5)
9387#define SPI_SSCTL_SLVTOIEN_Msk (0x1ul << SPI_SSCTL_SLVTOIEN_Pos)
9389#define SPI_SSCTL_SLVTORST_Pos (6)
9390#define SPI_SSCTL_SLVTORST_Msk (0x1ul << SPI_SSCTL_SLVTORST_Pos)
9392#define SPI_SSCTL_SLVBEIEN_Pos (8)
9393#define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos)
9395#define SPI_SSCTL_SLVURIEN_Pos (9)
9396#define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos)
9398#define SPI_SSCTL_SSACTIEN_Pos (12)
9399#define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos)
9401#define SPI_SSCTL_SSINAIEN_Pos (13)
9402#define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos)
9404#define SPI_SSCTL_SLVTOCNT_Pos (16)
9405#define SPI_SSCTL_SLVTOCNT_Msk (0xfffful << SPI_SSCTL_SLVTOCNT_Pos)
9407#define SPI_PDMACTL_TXPDMAEN_Pos (0)
9408#define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos)
9410#define SPI_PDMACTL_RXPDMAEN_Pos (1)
9411#define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos)
9413#define SPI_PDMACTL_PDMARST_Pos (2)
9414#define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos)
9416#define SPI_FIFOCTL_RXRST_Pos (0)
9417#define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos)
9419#define SPI_FIFOCTL_TXRST_Pos (1)
9420#define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos)
9422#define SPI_FIFOCTL_RXTHIEN_Pos (2)
9423#define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos)
9425#define SPI_FIFOCTL_TXTHIEN_Pos (3)
9426#define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos)
9428#define SPI_FIFOCTL_RXTOIEN_Pos (4)
9429#define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos)
9431#define SPI_FIFOCTL_RXOVIEN_Pos (5)
9432#define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos)
9434#define SPI_FIFOCTL_TXUFPOL_Pos (6)
9435#define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos)
9437#define SPI_FIFOCTL_TXUFIEN_Pos (7)
9438#define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos)
9440#define SPI_FIFOCTL_RXFBCLR_Pos (8)
9441#define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos)
9443#define SPI_FIFOCTL_TXFBCLR_Pos (9)
9444#define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos)
9446#define SPI_FIFOCTL_RXTH_Pos (24)
9447#define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos)
9449#define SPI_FIFOCTL_TXTH_Pos (28)
9450#define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos)
9452#define SPI_STATUS_BUSY_Pos (0)
9453#define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos)
9455#define SPI_STATUS_UNITIF_Pos (1)
9456#define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos)
9458#define SPI_STATUS_SSACTIF_Pos (2)
9459#define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos)
9461#define SPI_STATUS_SSINAIF_Pos (3)
9462#define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos)
9464#define SPI_STATUS_SSLINE_Pos (4)
9465#define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos)
9467#define SPI_STATUS_SLVTOIF_Pos (5)
9468#define SPI_STATUS_SLVTOIF_Msk (0x1ul << SPI_STATUS_SLVTOIF_Pos)
9470#define SPI_STATUS_SLVBEIF_Pos (6)
9471#define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos)
9473#define SPI_STATUS_SLVURIF_Pos (7)
9474#define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos)
9476#define SPI_STATUS_RXEMPTY_Pos (8)
9477#define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos)
9479#define SPI_STATUS_RXFULL_Pos (9)
9480#define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos)
9482#define SPI_STATUS_RXTHIF_Pos (10)
9483#define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos)
9485#define SPI_STATUS_RXOVIF_Pos (11)
9486#define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos)
9488#define SPI_STATUS_RXTOIF_Pos (12)
9489#define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos)
9491#define SPI_STATUS_SPIENSTS_Pos (15)
9492#define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos)
9494#define SPI_STATUS_TXEMPTY_Pos (16)
9495#define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos)
9497#define SPI_STATUS_TXFULL_Pos (17)
9498#define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos)
9500#define SPI_STATUS_TXTHIF_Pos (18)
9501#define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos)
9503#define SPI_STATUS_TXUFIF_Pos (19)
9504#define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos)
9506#define SPI_STATUS_TXRXRST_Pos (23)
9507#define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos)
9509#define SPI_STATUS_RXCNT_Pos (24)
9510#define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos)
9512#define SPI_STATUS_TXCNT_Pos (28)
9513#define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos)
9515#define SPI_TX_TX_Pos (0)
9516#define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos)
9518#define SPI_RX_RX_Pos (0)
9519#define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos)
9521#define SPI_I2SCTL_I2SEN_Pos (0)
9522#define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos)
9524#define SPI_I2SCTL_TXEN_Pos (1)
9525#define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos)
9527#define SPI_I2SCTL_RXEN_Pos (2)
9528#define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos)
9530#define SPI_I2SCTL_MUTE_Pos (3)
9531#define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos)
9533#define SPI_I2SCTL_WDWIDTH_Pos (4)
9534#define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos)
9536#define SPI_I2SCTL_MONO_Pos (6)
9537#define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos)
9539#define SPI_I2SCTL_ORDER_Pos (7)
9540#define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos)
9542#define SPI_I2SCTL_SLAVE_Pos (8)
9543#define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos)
9545#define SPI_I2SCTL_MCLKEN_Pos (15)
9546#define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos)
9548#define SPI_I2SCTL_RZCEN_Pos (16)
9549#define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos)
9551#define SPI_I2SCTL_LZCEN_Pos (17)
9552#define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos)
9554#define SPI_I2SCTL_RXLCH_Pos (23)
9555#define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos)
9557#define SPI_I2SCTL_RZCIEN_Pos (24)
9558#define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos)
9560#define SPI_I2SCTL_LZCIEN_Pos (25)
9561#define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos)
9563#define SPI_I2SCTL_FORMAT_Pos (28)
9564#define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos)
9566#define SPI_I2SCLK_MCLKDIV_Pos (0)
9567#define SPI_I2SCLK_MCLKDIV_Msk (0x3ful << SPI_I2SCLK_MCLKDIV_Pos)
9569#define SPI_I2SCLK_BCLKDIV_Pos (8)
9570#define SPI_I2SCLK_BCLKDIV_Msk (0x1fful << SPI_I2SCLK_BCLKDIV_Pos)
9572#define SPI_I2SSTS_RIGHT_Pos (4)
9573#define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos)
9575#define SPI_I2SSTS_RXEMPTY_Pos (8)
9576#define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos)
9578#define SPI_I2SSTS_RXFULL_Pos (9)
9579#define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos)
9581#define SPI_I2SSTS_RXTHIF_Pos (10)
9582#define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos)
9584#define SPI_I2SSTS_RXOVIF_Pos (11)
9585#define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos)
9587#define SPI_I2SSTS_RXTOIF_Pos (12)
9588#define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos)
9590#define SPI_I2SSTS_I2SENSTS_Pos (15)
9591#define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos)
9593#define SPI_I2SSTS_TXEMPTY_Pos (16)
9594#define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos)
9596#define SPI_I2SSTS_TXFULL_Pos (17)
9597#define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos)
9599#define SPI_I2SSTS_TXTHIF_Pos (18)
9600#define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos)
9602#define SPI_I2SSTS_TXUFIF_Pos (19)
9603#define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos)
9605#define SPI_I2SSTS_RZCIF_Pos (20)
9606#define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos)
9608#define SPI_I2SSTS_LZCIF_Pos (21)
9609#define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos)
9611#define SPI_I2SSTS_TXRXRST_Pos (23)
9612#define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos)
9614#define SPI_I2SSTS_RXCNT_Pos (24)
9615#define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos)
9617#define SPI_I2SSTS_TXCNT_Pos (28)
9618#define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) /* SPI_CONST */ /* end of SPI register group */
9622
9623
9624/*---------------------- System Manger Controller -------------------------*/
9631typedef struct
9632{
9633
10308 __I uint32_t PDID; /* Offset: 0x00 Part Device Identification Number Register */
10309 __IO uint32_t RSTSTS; /* Offset: 0x04 System Reset Status Register */
10310 __IO uint32_t IPRST0; /* Offset: 0x08 Peripheral Reset Control Register 0 */
10311 __IO uint32_t IPRST1; /* Offset: 0x0C Peripheral Reset Control Register 1 */
10312 __IO uint32_t IPRST2; /* Offset: 0x10 Peripheral Reset Control Register 2 */
10313 __I uint32_t RESERVE0[1];
10314 __IO uint32_t BODCTL; /* Offset: 0x18 Brown-Out Detector Control Register */
10315 __IO uint32_t IVSCTL; /* Offset: 0x1C Internal Voltage Source Control Register */
10316 __I uint32_t RESERVE1[1];
10317 __IO uint32_t PORCTL; /* Offset: 0x24 Power-On-Reset Controller Register */
10318 __IO uint32_t VREFCTL; /* Offset: 0x28 VREF Control Register */
10319 __IO uint32_t USBPHY; /* Offset: 0x2C USB PHY Control Register */
10320 __IO uint32_t GPA_MFPL; /* Offset: 0x30 GPIOA Low Byte Multiple Function Control Register */
10321 __IO uint32_t GPA_MFPH; /* Offset: 0x34 GPIOA High Byte Multiple Function Control Register */
10322 __IO uint32_t GPB_MFPL; /* Offset: 0x38 GPIOB Low Byte Multiple Function Control Register */
10323 __IO uint32_t GPB_MFPH; /* Offset: 0x3C GPIOB High Byte Multiple Function Control Register */
10324 __IO uint32_t GPC_MFPL; /* Offset: 0x40 GPIOC Low Byte Multiple Function Control Register */
10325 __IO uint32_t GPC_MFPH; /* Offset: 0x44 GPIOC High Byte Multiple Function Control Register */
10326 __IO uint32_t GPD_MFPL; /* Offset: 0x48 GPIOD Low Byte Multiple Function Control Register */
10327 __IO uint32_t GPD_MFPH; /* Offset: 0x4C GPIOD High Byte Multiple Function Control Register */
10328 __IO uint32_t GPE_MFPL; /* Offset: 0x50 GPIOE Low Byte Multiple Function Control Register */
10329 __IO uint32_t GPE_MFPH; /* Offset: 0x54 GPIOE High Byte Multiple Function Control Register */
10330 __IO uint32_t GPF_MFPL; /* Offset: 0x58 GPIOF Low Byte Multiple Function Control Register */
10331 __I uint32_t RESERVE2[29];
10332 __IO uint32_t SRAM_BISTCTL; /* Offset: 0xD0 System SRAM BIST Test Control Register */
10333 __I uint32_t SRAM_BISTSTS; /* Offset: 0xD4 System SRAM BIST Test Status Register */
10334 __I uint32_t RESERVE3[6];
10335 __IO uint32_t IRCTCTL; /* Offset: 0xF0 IRC Trim Control Register */
10336 __IO uint32_t IRCTIEN; /* Offset: 0xF4 IRC Trim Interrupt Enable Register */
10337 __IO uint32_t IRCTISTS; /* Offset: 0xF8 IRC Trim Interrupt Status Register */
10338 __I uint32_t RESERVE4[1];
10339 __IO uint32_t REGLCTL; /* Offset: 0x100 Register Lock Control Register */
10340 __I uint32_t RESERVE5[11];
10341 __IO uint32_t IRC48MTCTL; /* Offset: 0x130 IRC48M Trim Control Register */
10342 __IO uint32_t IRC48MTIEN; /* Offset: 0x134 IRC48M Trim Interrupt Enable Register */
10343 __IO uint32_t IRC48MTISTS; /* Offset: 0x138 IRC48M Trim Interrupt Status Register */
10344} SYS_T;
10345
10346
10347
10353#define SYS_PDID_PDID_Pos (0)
10354#define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos)
10356#define SYS_RSTSTS_PORF_Pos (0)
10357#define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos)
10359#define SYS_RSTSTS_PINRF_Pos (1)
10360#define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos)
10362#define SYS_RSTSTS_WDTRF_Pos (2)
10363#define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos)
10365#define SYS_RSTSTS_LVRF_Pos (3)
10366#define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos)
10368#define SYS_RSTSTS_BODRF_Pos (4)
10369#define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos)
10371#define SYS_RSTSTS_SYSRF_Pos (5)
10372#define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos)
10374#define SYS_RSTSTS_CPURF_Pos (7)
10375#define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos)
10377#define SYS_RSTSTS_CPULKRF_Pos (8)
10378#define SYS_RSTSTS_CPULKRF_Msk (0x1ul << SYS_RSTSTS_CPULKRF_Pos)
10380#define SYS_IPRST0_CHIPRST_Pos (0)
10381#define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos)
10383#define SYS_IPRST0_CPURST_Pos (1)
10384#define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos)
10386#define SYS_IPRST0_PDMARST_Pos (2)
10387#define SYS_IPRST0_PDMARST_Msk (0x1ul << SYS_IPRST0_PDMARST_Pos)
10389#define SYS_IPRST0_EBIRST_Pos (3)
10390#define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos)
10392#define SYS_IPRST0_USBHRST_Pos (4)
10393#define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos)
10395#define SYS_IPRST0_CRCRST_Pos (7)
10396#define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos)
10398#define SYS_IPRST1_GPIORST_Pos (1)
10399#define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos)
10401#define SYS_IPRST1_TMR0RST_Pos (2)
10402#define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos)
10404#define SYS_IPRST1_TMR1RST_Pos (3)
10405#define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos)
10407#define SYS_IPRST1_TMR2RST_Pos (4)
10408#define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos)
10410#define SYS_IPRST1_TMR3RST_Pos (5)
10411#define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos)
10413#define SYS_IPRST1_I2C0RST_Pos (8)
10414#define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos)
10416#define SYS_IPRST1_I2C1RST_Pos (9)
10417#define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos)
10419#define SYS_IPRST1_SPI0RST_Pos (12)
10420#define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos)
10422#define SYS_IPRST1_SPI1RST_Pos (13)
10423#define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos)
10425#define SYS_IPRST1_UART0RST_Pos (16)
10426#define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos)
10428#define SYS_IPRST1_UART1RST_Pos (17)
10429#define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos)
10431#define SYS_IPRST1_UART2RST_Pos (18)
10432#define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos)
10434#define SYS_IPRST1_UART3RST_Pos (19)
10435#define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos)
10437#define SYS_IPRST1_USBDRST_Pos (27)
10438#define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos)
10440#define SYS_IPRST1_EADCRST_Pos (28)
10441#define SYS_IPRST1_EADCRST_Msk (0x1ul << SYS_IPRST1_EADCRST_Pos)
10443#define SYS_IPRST2_SC0RST_Pos (0)
10444#define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos)
10446#define SYS_IPRST2_PWM0RST_Pos (16)
10447#define SYS_IPRST2_PWM0RST_Msk (0x1ul << SYS_IPRST2_PWM0RST_Pos)
10449#define SYS_IPRST2_PWM1RST_Pos (17)
10450#define SYS_IPRST2_PWM1RST_Msk (0x1ul << SYS_IPRST2_PWM1RST_Pos)
10452#define SYS_IPRST2_TKRST_Pos (25)
10453#define SYS_IPRST2_TKRST_Msk (0x1ul << SYS_IPRST2_TKRST_Pos)
10455#define SYS_BODCTL_BODEN_Pos (0)
10456#define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos)
10458#define SYS_BODCTL_BODVL_Pos (1)
10459#define SYS_BODCTL_BODVL_Msk (0x3ul << SYS_BODCTL_BODVL_Pos)
10461#define SYS_BODCTL_BODRSTEN_Pos (3)
10462#define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos)
10464#define SYS_BODCTL_BODIF_Pos (4)
10465#define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos)
10467#define SYS_BODCTL_BODLPM_Pos (5)
10468#define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos)
10470#define SYS_BODCTL_BODOUT_Pos (6)
10471#define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos)
10473#define SYS_BODCTL_LVREN_Pos (7)
10474#define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos)
10476#define SYS_BODCTL_BODDGSEL_Pos (8)
10477#define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos)
10479#define SYS_BODCTL_LVRDGSEL_Pos (12)
10480#define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos)
10482#define SYS_IVSCTL_VTEMPEN_Pos (0)
10483#define SYS_IVSCTL_VTEMPEN_Msk (0x1ul << SYS_IVSCTL_VTEMPEN_Pos)
10485#define SYS_IVSCTL_VBATUGEN_Pos (1)
10486#define SYS_IVSCTL_VBATUGEN_Msk (0x1ul << SYS_IVSCTL_VBATUGEN_Pos)
10488#define SYS_PORCTL_POROFF_Pos (0)
10489#define SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos)
10491#define SYS_VREFCTL_VREFCTL_Pos (0)
10492#define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos)
10494#define SYS_USBPHY_USBROLE_Pos (0)
10495#define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos)
10497#define SYS_USBPHY_LDO33EN_Pos (8)
10498#define SYS_USBPHY_LDO33EN_Msk (0x1ul << SYS_USBPHY_LDO33EN_Pos)
10500#define SYS_GPA_MFPL_PA0MFP_Pos (0)
10501#define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos)
10503#define SYS_GPA_MFPL_PA1MFP_Pos (4)
10504#define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos)
10506#define SYS_GPA_MFPL_PA2MFP_Pos (8)
10507#define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos)
10509#define SYS_GPA_MFPL_PA3MFP_Pos (12)
10510#define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos)
10512#define SYS_GPA_MFPL_PA4MFP_Pos (16)
10513#define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos)
10515#define SYS_GPA_MFPL_PA5MFP_Pos (20)
10516#define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos)
10518#define SYS_GPA_MFPL_PA6MFP_Pos (24)
10519#define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos)
10521#define SYS_GPA_MFPL_PA7MFP_Pos (28)
10522#define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos)
10524#define SYS_GPA_MFPH_PA8MFP_Pos (0)
10525#define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos)
10527#define SYS_GPA_MFPH_PA9MFP_Pos (4)
10528#define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos)
10530#define SYS_GPA_MFPH_PA10MFP_Pos (8)
10531#define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos)
10533#define SYS_GPA_MFPH_PA11MFP_Pos (12)
10534#define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos)
10536#define SYS_GPA_MFPH_PA12MFP_Pos (16)
10537#define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos)
10539#define SYS_GPA_MFPH_PA13MFP_Pos (20)
10540#define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos)
10542#define SYS_GPA_MFPH_PA14MFP_Pos (24)
10543#define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos)
10545#define SYS_GPA_MFPH_PA15MFP_Pos (28)
10546#define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos)
10548#define SYS_GPB_MFPL_PB0MFP_Pos (0)
10549#define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos)
10551#define SYS_GPB_MFPL_PB1MFP_Pos (4)
10552#define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos)
10554#define SYS_GPB_MFPL_PB2MFP_Pos (8)
10555#define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos)
10557#define SYS_GPB_MFPL_PB3MFP_Pos (12)
10558#define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos)
10560#define SYS_GPB_MFPL_PB4MFP_Pos (16)
10561#define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos)
10563#define SYS_GPB_MFPL_PB5MFP_Pos (20)
10564#define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos)
10566#define SYS_GPB_MFPL_PB6MFP_Pos (24)
10567#define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos)
10569#define SYS_GPB_MFPL_PB7MFP_Pos (28)
10570#define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos)
10572#define SYS_GPB_MFPH_PB8MFP_Pos (0)
10573#define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos)
10575#define SYS_GPB_MFPH_PB9MFP_Pos (4)
10576#define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos)
10578#define SYS_GPB_MFPH_PB10MFP_Pos (8)
10579#define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos)
10581#define SYS_GPB_MFPH_PB11MFP_Pos (12)
10582#define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos)
10584#define SYS_GPB_MFPH_PB12MFP_Pos (16)
10585#define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos)
10587#define SYS_GPB_MFPH_PB13MFP_Pos (20)
10588#define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos)
10590#define SYS_GPB_MFPH_PB14MFP_Pos (24)
10591#define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos)
10593#define SYS_GPB_MFPH_PB15MFP_Pos (28)
10594#define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos)
10596#define SYS_GPC_MFPL_PC0MFP_Pos (0)
10597#define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos)
10599#define SYS_GPC_MFPL_PC1MFP_Pos (4)
10600#define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos)
10602#define SYS_GPC_MFPL_PC2MFP_Pos (8)
10603#define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos)
10605#define SYS_GPC_MFPL_PC3MFP_Pos (12)
10606#define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos)
10608#define SYS_GPC_MFPL_PC4MFP_Pos (16)
10609#define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos)
10611#define SYS_GPC_MFPL_PC5MFP_Pos (20)
10612#define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos)
10614#define SYS_GPC_MFPL_PC6MFP_Pos (24)
10615#define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos)
10617#define SYS_GPC_MFPL_PC7MFP_Pos (28)
10618#define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos)
10620#define SYS_GPC_MFPH_PC8MFP_Pos (0)
10621#define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos)
10623#define SYS_GPC_MFPH_PC9MFP_Pos (4)
10624#define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos)
10626#define SYS_GPC_MFPH_PC10MFP_Pos (8)
10627#define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos)
10629#define SYS_GPC_MFPH_PC11MFP_Pos (12)
10630#define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos)
10632#define SYS_GPC_MFPH_PC12MFP_Pos (16)
10633#define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos)
10635#define SYS_GPC_MFPH_PC13MFP_Pos (20)
10636#define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos)
10638#define SYS_GPC_MFPH_PC14MFP_Pos (24)
10639#define SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos)
10641#define SYS_GPC_MFPH_PC15MFP_Pos (28)
10642#define SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos)
10644#define SYS_GPD_MFPL_PD0MFP_Pos (0)
10645#define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos)
10647#define SYS_GPD_MFPL_PD1MFP_Pos (4)
10648#define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos)
10650#define SYS_GPD_MFPL_PD2MFP_Pos (8)
10651#define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos)
10653#define SYS_GPD_MFPL_PD3MFP_Pos (12)
10654#define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos)
10656#define SYS_GPD_MFPL_PD4MFP_Pos (16)
10657#define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos)
10659#define SYS_GPD_MFPL_PD5MFP_Pos (20)
10660#define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos)
10662#define SYS_GPD_MFPL_PD6MFP_Pos (24)
10663#define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos)
10665#define SYS_GPD_MFPL_PD7MFP_Pos (28)
10666#define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos)
10668#define SYS_GPD_MFPH_PD8MFP_Pos (0)
10669#define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos)
10671#define SYS_GPD_MFPH_PD9MFP_Pos (4)
10672#define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos)
10674#define SYS_GPD_MFPH_PD10MFP_Pos (8)
10675#define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos)
10677#define SYS_GPD_MFPH_PD11MFP_Pos (12)
10678#define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos)
10680#define SYS_GPD_MFPH_PD12MFP_Pos (16)
10681#define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos)
10683#define SYS_GPD_MFPH_PD13MFP_Pos (20)
10684#define SYS_GPD_MFPH_PD13MFP_Msk (0xful << SYS_GPD_MFPH_PD13MFP_Pos)
10686#define SYS_GPD_MFPH_PD14MFP_Pos (24)
10687#define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos)
10689#define SYS_GPD_MFPH_PD15MFP_Pos (28)
10690#define SYS_GPD_MFPH_PD15MFP_Msk (0xful << SYS_GPD_MFPH_PD15MFP_Pos)
10692#define SYS_GPE_MFPL_PE0MFP_Pos (0)
10693#define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos)
10695#define SYS_GPE_MFPL_PE1MFP_Pos (4)
10696#define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos)
10698#define SYS_GPE_MFPL_PE2MFP_Pos (8)
10699#define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos)
10701#define SYS_GPE_MFPL_PE3MFP_Pos (12)
10702#define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos)
10704#define SYS_GPE_MFPL_PE4MFP_Pos (16)
10705#define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos)
10707#define SYS_GPE_MFPL_PE5MFP_Pos (20)
10708#define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos)
10710#define SYS_GPE_MFPL_PE6MFP_Pos (24)
10711#define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos)
10713#define SYS_GPE_MFPL_PE7MFP_Pos (28)
10714#define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos)
10716#define SYS_GPE_MFPH_PE8MFP_Pos (0)
10717#define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos)
10719#define SYS_GPE_MFPH_PE9MFP_Pos (4)
10720#define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos)
10722#define SYS_GPE_MFPH_PE10MFP_Pos (8)
10723#define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos)
10725#define SYS_GPE_MFPH_PE11MFP_Pos (12)
10726#define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos)
10728#define SYS_GPE_MFPH_PE12MFP_Pos (16)
10729#define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos)
10731#define SYS_GPE_MFPH_PE13MFP_Pos (20)
10732#define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos)
10734#define SYS_GPE_MFPH_PE14MFP_Pos (24)
10735#define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos)
10737#define SYS_GPF_MFPL_PF0MFP_Pos (0)
10738#define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos)
10740#define SYS_GPF_MFPL_PF1MFP_Pos (4)
10741#define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos)
10743#define SYS_GPF_MFPL_PF2MFP_Pos (8)
10744#define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos)
10746#define SYS_GPF_MFPL_PF3MFP_Pos (12)
10747#define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos)
10749#define SYS_GPF_MFPL_PF4MFP_Pos (16)
10750#define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos)
10752#define SYS_GPF_MFPL_PF5MFP_Pos (20)
10753#define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos)
10755#define SYS_GPF_MFPL_PF6MFP_Pos (24)
10756#define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos)
10758#define SYS_GPF_MFPL_PF7MFP_Pos (28)
10759#define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos)
10761#define SYS_SRAM_BISTCTL_SRBIST0_Pos (0)
10762#define SYS_SRAM_BISTCTL_SRBIST0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST0_Pos)
10764#define SYS_SRAM_BISTCTL_SRBIST1_Pos (1)
10765#define SYS_SRAM_BISTCTL_SRBIST1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST1_Pos)
10767#define SYS_SRAM_BISTCTL_CRBIST_Pos (2)
10768#define SYS_SRAM_BISTCTL_CRBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CRBIST_Pos)
10770#define SYS_SRAM_BISTCTL_USBBIST_Pos (4)
10771#define SYS_SRAM_BISTCTL_USBBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_USBBIST_Pos)
10773#define SYS_SRAM_BISTSTS_SRBISTEF0_Pos (0)
10774#define SYS_SRAM_BISTSTS_SRBISTEF0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF0_Pos)
10776#define SYS_SRAM_BISTSTS_SRBISTEF1_Pos (1)
10777#define SYS_SRAM_BISTSTS_SRBISTEF1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF1_Pos)
10779#define SYS_SRAM_BISTSTS_CRBISTEF_Pos (2)
10780#define SYS_SRAM_BISTSTS_CRBISTEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBISTEF_Pos)
10782#define SYS_SRAM_BISTSTS_USBBEF_Pos (4)
10783#define SYS_SRAM_BISTSTS_USBBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEF_Pos)
10785#define SYS_SRAM_BISTSTS_SRBEND0_Pos (16)
10786#define SYS_SRAM_BISTSTS_SRBEND0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND0_Pos)
10788#define SYS_SRAM_BISTSTS_SRBEND1_Pos (17)
10789#define SYS_SRAM_BISTSTS_SRBEND1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND1_Pos)
10791#define SYS_SRAM_BISTSTS_CRBEND_Pos (18)
10792#define SYS_SRAM_BISTSTS_CRBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBEND_Pos)
10794#define SYS_SRAM_BISTSTS_USBBEND_Pos (20)
10795#define SYS_SRAM_BISTSTS_USBBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEND_Pos)
10797#define SYS_IRCTCTL_FREQSEL_Pos (0)
10798#define SYS_IRCTCTL_FREQSEL_Msk (0x3ul << SYS_IRCTCTL_FREQSEL_Pos)
10800#define SYS_IRCTCTL_LOOPSEL_Pos (4)
10801#define SYS_IRCTCTL_LOOPSEL_Msk (0x3ul << SYS_IRCTCTL_LOOPSEL_Pos)
10803#define SYS_IRCTCTL_RETRYCNT_Pos (6)
10804#define SYS_IRCTCTL_RETRYCNT_Msk (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos)
10806#define SYS_IRCTCTL_CESTOPEN_Pos (8)
10807#define SYS_IRCTCTL_CESTOPEN_Msk (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos)
10809#define SYS_IRCTIEN_TFAILIEN_Pos (1)
10810#define SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos)
10812#define SYS_IRCTIEN_CLKEIEN_Pos (2)
10813#define SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos)
10815#define SYS_IRCTISTS_FREQLOCK_Pos (0)
10816#define SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos)
10818#define SYS_IRCTISTS_TFAILIF_Pos (1)
10819#define SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos)
10821#define SYS_IRCTISTS_CLKERRIF_Pos (2)
10822#define SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos)
10824#define SYS_REGLCTL_REGLCTL_Pos (0)
10825#define SYS_REGLCTL_REGLCTL_Msk (0xfful << SYS_REGLCTL_REGLCTL_Pos)
10827#define SYS_IRC48MTCTL_FREQSEL_Pos (0)
10828#define SYS_IRC48MTCTL_FREQSEL_Msk (0x3ul << SYS_IRC48MTCTL_FREQSEL_Pos)
10830#define SYS_IRC48MTCTL_LOOPSEL_Pos (4)
10831#define SYS_IRC48MTCTL_LOOPSEL_Msk (0x3ul << SYS_IRC48MTCTL_LOOPSEL_Pos)
10833#define SYS_IRC48MTCTL_RETRYCNT_Pos (6)
10834#define SYS_IRC48MTCTL_RETRYCNT_Msk (0x3ul << SYS_IRC48MTCTL_RETRYCNT_Pos)
10836#define SYS_IRC48MTCTL_CESTOPEN_Pos (8)
10837#define SYS_IRC48MTCTL_CESTOPEN_Msk (0x1ul << SYS_IRC48MTCTL_CESTOPEN_Pos)
10839#define SYS_IRC48MTCTL_REFCKSEL_Pos (10)
10840#define SYS_IRC48MTCTL_REFCKSEL_Msk (0x1ul << SYS_IRC48MTCTL_REFCKSEL_Pos)
10842#define SYS_IRC48MTIEN_TFAILIEN_Pos (1)
10843#define SYS_IRC48MTIEN_TFAILIEN_Msk (0x1ul << SYS_IRC48MTIEN_TFAILIEN_Pos)
10845#define SYS_IRC48MTIEN_CLKEIEN_Pos (2)
10846#define SYS_IRC48MTIEN_CLKEIEN_Msk (0x1ul << SYS_IRC48MTIEN_CLKEIEN_Pos)
10848#define SYS_IRC48MTISTS_FREQLOCK_Pos (0)
10849#define SYS_IRC48MTISTS_FREQLOCK_Msk (0x1ul << SYS_IRC48MTISTS_FREQLOCK_Pos)
10851#define SYS_IRC48MTISTS_TFAILIF_Pos (1)
10852#define SYS_IRC48MTISTS_TFAILIF_Msk (0x1ul << SYS_IRC48MTISTS_TFAILIF_Pos)
10854#define SYS_IRC48MTISTS_CLKERRIF_Pos (2)
10855#define SYS_IRC48MTISTS_CLKERRIF_Msk (0x1ul << SYS_IRC48MTISTS_CLKERRIF_Pos) /* SYS_CONST */
10858
10859
10860typedef struct
10861{
10862
10975 __IO uint32_t NMIEN; /* Offset: 0x00 NMI Source Interrupt Enable Register */
10976 __I uint32_t NMISTS; /* Offset: 0x04 NMI source interrupt Status Register */
10977
10978} SYS_INT_T;
10979
10980
10981
10987#define SYS_NMIEN_BODOUT_Pos (0)
10988#define SYS_NMIEN_BODOUT_Msk (0x1ul << SYS_NMIEN_BODOUT_Pos )
10990#define SYS_NMIEN_IRC_INT_Pos (1)
10991#define SYS_NMIEN_IRC_INT_Msk (0x1ul << SYS_NMIEN_IRC_INT_Pos )
10993#define SYS_NMIEN_PWRWU_INT_Pos (2)
10994#define SYS_NMIEN_PWRWU_INT_Msk (0x1ul << SYS_NMIEN_PWRWU_INT_Pos )
10996#define SYS_NMIEN_CLKFAIL_Pos (4)
10997#define SYS_NMIEN_CLKFAIL_Msk (0x1ul << SYS_NMIEN_CLKFAIL_Pos )
10999#define SYS_NMIEN_RTC_INT_Pos (6)
11000#define SYS_NMIEN_RTC_INT_Msk (0x1ul << SYS_NMIEN_RTC_INT_Pos )
11002#define SYS_NMIEN_TAMPER_INT_Pos (7)
11003#define SYS_NMIEN_TAMPER_INT_Msk (0x1ul << SYS_NMIEN_TAMPER_INT_Pos )
11005#define SYS_NMIEN_EINT0_Pos (8)
11006#define SYS_NMIEN_EINT0_Msk (0x1ul << SYS_NMIEN_EINT0_Pos )
11008#define SYS_NMIEN_EINT1_Pos (9)
11009#define SYS_NMIEN_EINT1_Msk (0x1ul << SYS_NMIEN_EINT1_Pos )
11011#define SYS_NMIEN_EINT2_Pos (10)
11012#define SYS_NMIEN_EINT2_Msk (0x1ul << SYS_NMIEN_EINT2_Pos )
11014#define SYS_NMIEN_EINT3_Pos (11)
11015#define SYS_NMIEN_EINT3_Msk (0x1ul << SYS_NMIEN_EINT3_Pos )
11017#define SYS_NMIEN_EINT4_Pos (12)
11018#define SYS_NMIEN_EINT4_Msk (0x1ul << SYS_NMIEN_EINT4_Pos )
11020#define SYS_NMIEN_EINT5_Pos (13)
11021#define SYS_NMIEN_EINT5_Msk (0x1ul << SYS_NMIEN_EINT5_Pos )
11023#define SYS_NMIEN_UART0_INT_Pos (14)
11024#define SYS_NMIEN_UART0_INT_Msk (0x1ul << SYS_NMIEN_UART0_INT_Pos )
11026#define SYS_NMIEN_UART1_INT_Pos (15)
11027#define SYS_NMIEN_UART1_INT_Msk (0x1ul << SYS_NMIEN_UART1_INT_Pos )
11029#define SYS_NMISTS_BODOUT_Pos (0)
11030#define SYS_NMISTS_BODOUT_Msk (0x1ul << SYS_NMISTS_BODOUT_Pos )
11032#define SYS_NMISTS_IRC_INT_Pos (1)
11033#define SYS_NMISTS_IRC_INT_Msk (0x1ul << SYS_NMISTS_IRC_INT_Pos )
11035#define SYS_NMISTS_PWRWU_INT_Pos (2)
11036#define SYS_NMISTS_PWRWU_INT_Msk (0x1ul << SYS_NMISTS_PWRWU_INT_Pos )
11038#define SYS_NMISTS_CLKFAIL_Pos (4)
11039#define SYS_NMISTS_CLKFAIL_Msk (0x1ul << SYS_NMISTS_CLKFAIL_Pos )
11041#define SYS_NMISTS_RTC_INT_Pos (6)
11042#define SYS_NMISTS_RTC_INT_Msk (0x1ul << SYS_NMISTS_RTC_INT_Pos )
11044#define SYS_NMISTS_TAMPER_INT_Pos (7)
11045#define SYS_NMISTS_TAMPER_INT_Msk (0x1ul << SYS_NMISTS_TAMPER_INT_Pos )
11047#define SYS_NMISTS_EINT0_Pos (8)
11048#define SYS_NMISTS_EINT0_Msk (0x1ul << SYS_NMISTS_EINT0_Pos )
11050#define SYS_NMISTS_EINT1_Pos (9)
11051#define SYS_NMISTS_EINT1_Msk (0x1ul << SYS_NMISTS_EINT1_Pos )
11053#define SYS_NMISTS_EINT2_Pos (10)
11054#define SYS_NMISTS_EINT2_Msk (0x1ul << SYS_NMISTS_EINT2_Pos )
11056#define SYS_NMISTS_EINT3_Pos (11)
11057#define SYS_NMISTS_EINT3_Msk (0x1ul << SYS_NMISTS_EINT3_Pos )
11059#define SYS_NMISTS_EINT4_Pos (12)
11060#define SYS_NMISTS_EINT4_Msk (0x1ul << SYS_NMISTS_EINT4_Pos )
11062#define SYS_NMISTS_EINT5_Pos (13)
11063#define SYS_NMISTS_EINT5_Msk (0x1ul << SYS_NMISTS_EINT5_Pos )
11065#define SYS_NMISTS_UART0_INT_Pos (14)
11066#define SYS_NMISTS_UART0_INT_Msk (0x1ul << SYS_NMISTS_UART0_INT_Pos )
11068#define SYS_NMISTS_UART1_INT_Pos (15)
11069#define SYS_NMISTS_UART1_INT_Msk (0x1ul << SYS_NMISTS_UART1_INT_Pos ) /* INT_CONST */ /* end of SYS register group */
11073
11074
11075
11076
11077/*---------------------- Timer Controller -------------------------*/
11084typedef struct
11085{
11086
11087
11252 __IO uint32_t CTL; /* Offset: 0x00 Timer Control and Status Register */
11253 __IO uint32_t CMP; /* Offset: 0x04 Timer Compare Register */
11254 __IO uint32_t INTSTS; /* Offset: 0x08 Timer Interrupt Status Register */
11255 __I uint32_t CNT; /* Offset: 0x0C Timer Data Register */
11256 __I uint32_t CAP; /* Offset: 0x10 Timer Capture Data Register */
11257 __IO uint32_t EXTCTL; /* Offset: 0x14 Timer External Control Register */
11258 __IO uint32_t EINTSTS; /* Offset: 0x18 Timer External Interrupt Status Register */
11259
11260} TIMER_T;
11261
11262
11263
11269#define TIMER_CTL_PSC_Pos (0)
11270#define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos)
11272#define TIMER_CTL_WKTKEN_Pos (17)
11273#define TIMER_CTL_WKTKEN_Msk (0x1ul << TIMER_CTL_WKTKEN_Pos)
11275#define TIMER_CTL_TRGSSEL_Pos (18)
11276#define TIMER_CTL_TRGSSEL_Msk (0x1ul << TIMER_CTL_TRGSSEL_Pos)
11278#define TIMER_CTL_TRGPWM_Pos (19)
11279#define TIMER_CTL_TRGPWM_Msk (0x1ul << TIMER_CTL_TRGPWM_Pos)
11281#define TIMER_CTL_TRGEADC_Pos (21)
11282#define TIMER_CTL_TRGEADC_Msk (0x1ul << TIMER_CTL_TRGEADC_Pos)
11284#define TIMER_CTL_TGLPINSEL_Pos (22)
11285#define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos)
11287#define TIMER_CTL_WKEN_Pos (23)
11288#define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos)
11290#define TIMER_CTL_EXTCNTEN_Pos (24)
11291#define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos)
11293#define TIMER_CTL_ACTSTS_Pos (25)
11294#define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos)
11296#define TIMER_CTL_RSTCNT_Pos (26)
11297#define TIMER_CTL_RSTCNT_Msk (0x1ul << TIMER_CTL_RSTCNT_Pos)
11299#define TIMER_CTL_OPMODE_Pos (27)
11300#define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos)
11302#define TIMER_CTL_INTEN_Pos (29)
11303#define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos)
11305#define TIMER_CTL_CNTEN_Pos (30)
11306#define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos)
11308#define TIMER_CTL_ICEDEBUG_Pos (31)
11309#define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos)
11311#define TIMER_CMP_CMPDAT_Pos (0)
11312#define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos)
11314#define TIMER_INTSTS_TIF_Pos (0)
11315#define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos)
11317#define TIMER_INTSTS_TWKF_Pos (1)
11318#define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos)
11320#define TIMER_CNT_CNT_Pos (0)
11321#define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos)
11323#define TIMER_CAP_CAPDAT_Pos (0)
11324#define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos)
11326#define TIMER_EXTCTL_CNTPHASE_Pos (0)
11327#define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos)
11329#define TIMER_EXTCTL_CAPEDGE_Pos (1)
11330#define TIMER_EXTCTL_CAPEDGE_Msk (0x3ul << TIMER_EXTCTL_CAPEDGE_Pos)
11332#define TIMER_EXTCTL_CAPEN_Pos (3)
11333#define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos)
11335#define TIMER_EXTCTL_CAPFUNCS_Pos (4)
11336#define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos)
11338#define TIMER_EXTCTL_CAPIEN_Pos (5)
11339#define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos)
11341#define TIMER_EXTCTL_CAPDBEN_Pos (6)
11342#define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos)
11344#define TIMER_EXTCTL_CNTDBEN_Pos (7)
11345#define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos)
11347#define TIMER_EINTSTS_CAPIF_Pos (0)
11348#define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /* TIMER_CONST */ /* end of TIMER register group */
11352
11353
11354/*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
11361typedef struct
11362{
11363
11364
11365
11366
11883 __IO uint32_t DAT; /* Offset: 0x00 UART Receive/Transmit Buffer Register */
11884 __IO uint32_t INTEN; /* Offset: 0x04 UART Interrupt Enable Register */
11885 __IO uint32_t FIFO; /* Offset: 0x08 UART FIFO Control Register */
11886 __IO uint32_t LINE; /* Offset: 0x0C UART Line Control Register */
11887 __IO uint32_t MODEM; /* Offset: 0x10 UART Modem Control Register */
11888 __IO uint32_t MODEMSTS; /* Offset: 0x14 UART Modem Status Register */
11889 __IO uint32_t FIFOSTS; /* Offset: 0x18 UART FIFO Status Register */
11890 __IO uint32_t INTSTS; /* Offset: 0x1C UART Interrupt Status Register */
11891 __IO uint32_t TOUT; /* Offset: 0x20 UART Time-out Register */
11892 __IO uint32_t BAUD; /* Offset: 0x24 UART Baud Rate Divisor Register */
11893 __IO uint32_t IRDA; /* Offset: 0x28 UART IrDA Control Register */
11894 __IO uint32_t ALTCTL; /* Offset: 0x2C UART Alternate Control/Status Register */
11895 __IO uint32_t FUNCSEL; /* Offset: 0x30 UART Function Select Register */
11896} UART_T;
11897
11898
11899
11905#define UART_DAT_DAT_Pos (0)
11906#define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos)
11908#define UART_INTEN_RDAIEN_Pos (0)
11909#define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos)
11911#define UART_INTEN_THREIEN_Pos (1)
11912#define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos)
11914#define UART_INTEN_RLSIEN_Pos (2)
11915#define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos)
11917#define UART_INTEN_MODEMIEN_Pos (3)
11918#define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos)
11920#define UART_INTEN_RXTOIEN_Pos (4)
11921#define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos)
11923#define UART_INTEN_BUFERRIEN_Pos (5)
11924#define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos)
11926#define UART_INTEN_LINIEN_Pos (8)
11927#define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos)
11929#define UART_INTEN_WKCTSIEN_Pos (9)
11930#define UART_INTEN_WKCTSIEN_Msk (0x1ul << UART_INTEN_WKCTSIEN_Pos)
11932#define UART_INTEN_WKDATIEN_Pos (10)
11933#define UART_INTEN_WKDATIEN_Msk (0x1ul << UART_INTEN_WKDATIEN_Pos)
11935#define UART_INTEN_TOCNTEN_Pos (11)
11936#define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos)
11938#define UART_INTEN_ATORTSEN_Pos (12)
11939#define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos)
11941#define UART_INTEN_ATOCTSEN_Pos (13)
11942#define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos)
11944#define UART_INTEN_TXPDMAEN_Pos (14)
11945#define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos)
11947#define UART_INTEN_RXPDMAEN_Pos (15)
11948#define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos)
11950#define UART_INTEN_ABRIEN_Pos (18)
11951#define UART_INTEN_ABRIEN_Msk (0x1ul << UART_INTEN_ABRIEN_Pos)
11953#define UART_FIFO_RXRST_Pos (1)
11954#define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos)
11956#define UART_FIFO_TXRST_Pos (2)
11957#define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos)
11959#define UART_FIFO_RFITL_Pos (4)
11960#define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos)
11962#define UART_FIFO_RXOFF_Pos (8)
11963#define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos)
11965#define UART_FIFO_RTSTRGLV_Pos (16)
11966#define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos)
11968#define UART_LINE_WLS_Pos (0)
11969#define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos)
11971#define UART_LINE_NSB_Pos (2)
11972#define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos)
11974#define UART_LINE_PBE_Pos (3)
11975#define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos)
11977#define UART_LINE_EPE_Pos (4)
11978#define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos)
11980#define UART_LINE_SPE_Pos (5)
11981#define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos)
11983#define UART_LINE_BCB_Pos (6)
11984#define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos)
11986#define UART_MODEM_RTS_Pos (1)
11987#define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos)
11989#define UART_MODEM_RTSACTLV_Pos (9)
11990#define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos)
11992#define UART_MODEM_RTSSTS_Pos (13)
11993#define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos)
11995#define UART_MODEMSTS_CTSDETF_Pos (0)
11996#define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos)
11998#define UART_MODEMSTS_CTSSTS_Pos (4)
11999#define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos)
12001#define UART_MODEMSTS_CTSACTLV_Pos (8)
12002#define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos)
12004#define UART_FIFOSTS_RXOVIF_Pos (0)
12005#define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos)
12007#define UART_FIFOSTS_ABRDIF_Pos (1)
12008#define UART_FIFOSTS_ABRDIF_Msk (0x1ul << UART_FIFOSTS_ABRDIF_Pos)
12010#define UART_FIFOSTS_ABRDTOIF_Pos (2)
12011#define UART_FIFOSTS_ABRDTOIF_Msk (0x1ul << UART_FIFOSTS_ABRDTOIF_Pos)
12013#define UART_FIFOSTS_ADDRDETF_Pos (3)
12014#define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos)
12016#define UART_FIFOSTS_PEF_Pos (4)
12017#define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos)
12019#define UART_FIFOSTS_FEF_Pos (5)
12020#define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos)
12022#define UART_FIFOSTS_BIF_Pos (6)
12023#define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos)
12025#define UART_FIFOSTS_RXPTR_Pos (8)
12026#define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos)
12028#define UART_FIFOSTS_RXEMPTY_Pos (14)
12029#define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos)
12031#define UART_FIFOSTS_RXFULL_Pos (15)
12032#define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos)
12034#define UART_FIFOSTS_TXPTR_Pos (16)
12035#define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos)
12037#define UART_FIFOSTS_TXEMPTY_Pos (22)
12038#define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos)
12040#define UART_FIFOSTS_TXFULL_Pos (23)
12041#define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos)
12043#define UART_FIFOSTS_TXOVIF_Pos (24)
12044#define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos)
12046#define UART_FIFOSTS_TXEMPTYF_Pos (28)
12047#define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos)
12049#define UART_INTSTS_RDAIF_Pos (0)
12050#define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos)
12052#define UART_INTSTS_THREIF_Pos (1)
12053#define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos)
12055#define UART_INTSTS_RLSIF_Pos (2)
12056#define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos)
12058#define UART_INTSTS_MODEMIF_Pos (3)
12059#define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos)
12061#define UART_INTSTS_RXTOIF_Pos (4)
12062#define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos)
12064#define UART_INTSTS_BUFERRIF_Pos (5)
12065#define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos)
12067#define UART_INTSTS_WKIF_Pos (6)
12068#define UART_INTSTS_WKIF_Msk (0x1ul << UART_INTSTS_WKIF_Pos)
12070#define UART_INTSTS_LINIF_Pos (7)
12071#define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos)
12073#define UART_INTSTS_RDAINT_Pos (8)
12074#define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos)
12076#define UART_INTSTS_THREINT_Pos (9)
12077#define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos)
12079#define UART_INTSTS_RLSINT_Pos (10)
12080#define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos)
12082#define UART_INTSTS_MODEMINT_Pos (11)
12083#define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos)
12085#define UART_INTSTS_RXTOINT_Pos (12)
12086#define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos)
12088#define UART_INTSTS_BUFERRINT_Pos (13)
12089#define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos)
12091#define UART_INTSTS_LININT_Pos (15)
12092#define UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos)
12094#define UART_INTSTS_CTSWKIF_Pos (16)
12095#define UART_INTSTS_CTSWKIF_Msk (0x1ul << UART_INTSTS_CTSWKIF_Pos)
12097#define UART_INTSTS_DATWKIF_Pos (17)
12098#define UART_INTSTS_DATWKIF_Msk (0x1ul << UART_INTSTS_DATWKIF_Pos)
12100#define UART_INTSTS_HWRLSIF_Pos (18)
12101#define UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos)
12103#define UART_INTSTS_HWMODIF_Pos (19)
12104#define UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos)
12106#define UART_INTSTS_HWTOIF_Pos (20)
12107#define UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos)
12109#define UART_INTSTS_HWBUFEIF_Pos (21)
12110#define UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos)
12112#define UART_INTSTS_HWRLSINT_Pos (26)
12113#define UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos)
12115#define UART_INTSTS_HWMODINT_Pos (27)
12116#define UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos)
12118#define UART_INTSTS_HWTOINT_Pos (28)
12119#define UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos)
12121#define UART_INTSTS_HWBUFEINT_Pos (29)
12122#define UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos)
12124#define UART_TOUT_TOIC_Pos (0)
12125#define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos)
12127#define UART_TOUT_DLY_Pos (8)
12128#define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos)
12130#define UART_BAUD_BRD_Pos (0)
12131#define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos)
12133#define UART_BAUD_EDIVM1_Pos (24)
12134#define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos)
12136#define UART_BAUD_BAUDM0_Pos (28)
12137#define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos)
12139#define UART_BAUD_BAUDM1_Pos (29)
12140#define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos)
12142#define UART_IRDA_TXEN_Pos (1)
12143#define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos)
12145#define UART_IRDA_TXINV_Pos (5)
12146#define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos)
12148#define UART_IRDA_RXINV_Pos (6)
12149#define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos)
12151#define UART_ALTCTL_BRKFL_Pos (0)
12152#define UART_ALTCTL_BRKFL_Msk (0xful << UART_ALTCTL_BRKFL_Pos)
12154#define UART_ALTCTL_LINRXEN_Pos (6)
12155#define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos)
12157#define UART_ALTCTL_LINTXEN_Pos (7)
12158#define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos)
12160#define UART_ALTCTL_RS485NMM_Pos (8)
12161#define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos)
12163#define UART_ALTCTL_RS485AAD_Pos (9)
12164#define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos)
12166#define UART_ALTCTL_RS485AUD_Pos (10)
12167#define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos)
12169#define UART_ALTCTL_ADDRDEN_Pos (15)
12170#define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos)
12172#define UART_ALTCTL_ABRIF_Pos (17)
12173#define UART_ALTCTL_ABRIF_Msk (0x1ul << UART_ALTCTL_ABRIF_Pos)
12175#define UART_ALTCTL_ABRDEN_Pos (18)
12176#define UART_ALTCTL_ABRDEN_Msk (0x1ul << UART_ALTCTL_ABRDEN_Pos)
12178#define UART_ALTCTL_ABRDBITS_Pos (19)
12179#define UART_ALTCTL_ABRDBITS_Msk (0x3ul << UART_ALTCTL_ABRDBITS_Pos)
12181#define UART_ALTCTL_ADDRMV_Pos (24)
12182#define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos)
12184#define UART_FUNCSEL_FUNCSEL_Pos (0)
12185#define UART_FUNCSEL_FUNCSEL_Msk (0x3ul << UART_FUNCSEL_FUNCSEL_Pos) /* UART_CONST */ /* end of UART register group */
12189
12190
12191/*---------------------- Universal Serial Bus Controller -------------------------*/
12201typedef struct
12202{
12203
12204
12271 __IO uint32_t BUFSEG; /* Offset: 0x500/0x510/0x520/0x530/0x540/0x550/0x560/0x570 Endpoint 0~7 Buffer Segmentation Register */
12272 __IO uint32_t MXPLD; /* Offset: 0x504/0x514/0x524/0x534/0x544/0x554/0x564/0x574 Endpoint 0~7 Maximal Payload Register */
12273 __IO uint32_t CFG; /* Offset: 0x508/0x518/0x528/0x538/0x548/0x558/0x568/0x578 Endpoint 0~7 Configuration Register */
12274 __IO uint32_t CFGP; /* Offset: 0x50C/0x51C/0x52C/0x53C/0x54C/0x55C/0x56C/0x57C Endpoint 0~7 Set Stall and Clear In/Out Ready Control Register */
12275
12276} USBD_EP_T;
12277
12278
12279
12280
12281
12282typedef struct
12283{
12284
12285
12509 __IO uint32_t INTEN; /* Offset: 0x00 USB Interrupt Enable Register */
12510 __IO uint32_t INTSTS; /* Offset: 0x04 USB Interrupt Event Status Register */
12511 __IO uint32_t FADDR; /* Offset: 0x08 USB Device Function Address Register */
12512 __I uint32_t EPSTS; /* Offset: 0x0C USB Endpoint Status Register */
12513 __IO uint32_t ATTR; /* Offset: 0x10 USB Bus Status and Attribution Register */
12514 __I uint32_t VBUSDET; /* Offset: 0x14 USB Device VBUS Detection Register */
12515 __IO uint32_t STBUFSEG; /* Offset: 0x18 Setup Token Buffer Segmentation Register */
12516 __I uint32_t RESERVE0[29];
12517 __IO uint32_t SE0; /* Offset: 0x90 USB Drive SE0 Control Register */
12518 __I uint32_t RESERVE1[283];
12519 USBD_EP_T EP[8]; /* Offset: 0x500 ~ 0x57C USB End Point 0 ~ 7 Configuration Register */
12520
12521} USBD_T;
12522
12523
12524
12530#define USBD_INTEN_BUSIEN_Pos (0)
12531#define USBD_INTEN_BUSIEN_Msk (0x1ul << USBD_INTEN_BUSIEN_Pos)
12533#define USBD_INTEN_USBIEN_Pos (1)
12534#define USBD_INTEN_USBIEN_Msk (0x1ul << USBD_INTEN_USBIEN_Pos)
12536#define USBD_INTEN_VBDETIEN_Pos (2)
12537#define USBD_INTEN_VBDETIEN_Msk (0x1ul << USBD_INTEN_VBDETIEN_Pos)
12539#define USBD_INTEN_NEVWKIEN_Pos (3)
12540#define USBD_INTEN_NEVWKIEN_Msk (0x1ul << USBD_INTEN_NEVWKIEN_Pos)
12542#define USBD_INTEN_WKEN_Pos (8)
12543#define USBD_INTEN_WKEN_Msk (0x1ul << USBD_INTEN_WKEN_Pos)
12545#define USBD_INTEN_INNAKEN_Pos (15)
12546#define USBD_INTEN_INNAKEN_Msk (0x1ul << USBD_INTEN_INNAKEN_Pos)
12548#define USBD_INTSTS_BUSIF_Pos (0)
12549#define USBD_INTSTS_BUSIF_Msk (0x1ul << USBD_INTSTS_BUSIF_Pos)
12551#define USBD_INTSTS_USBIF_Pos (1)
12552#define USBD_INTSTS_USBIF_Msk (0x1ul << USBD_INTSTS_USBIF_Pos)
12554#define USBD_INTSTS_VBDETIF_Pos (2)
12555#define USBD_INTSTS_VBDETIF_Msk (0x1ul << USBD_INTSTS_VBDETIF_Pos)
12557#define USBD_INTSTS_NEVWKIF_Pos (3)
12558#define USBD_INTSTS_NEVWKIF_Msk (0x1ul << USBD_INTSTS_NEVWKIF_Pos)
12560#define USBD_INTSTS_SOFIF_Pos (4)
12561#define USBD_INTSTS_SOFIF_Msk (0x1ul << USBD_INTSTS_SOFIF_Pos)
12563#define USBD_INTSTS_EPEVT0_Pos (16)
12564#define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos)
12566#define USBD_INTSTS_EPEVT1_Pos (17)
12567#define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos)
12569#define USBD_INTSTS_EPEVT2_Pos (18)
12570#define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos)
12572#define USBD_INTSTS_EPEVT3_Pos (19)
12573#define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos)
12575#define USBD_INTSTS_EPEVT4_Pos (20)
12576#define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos)
12578#define USBD_INTSTS_EPEVT5_Pos (21)
12579#define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos)
12581#define USBD_INTSTS_EPEVT6_Pos (22)
12582#define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos)
12584#define USBD_INTSTS_EPEVT7_Pos (23)
12585#define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos)
12587#define USBD_INTSTS_SETUP_Pos (31)
12588#define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos)
12590#define USBD_FADDR_FADDR_Pos (0)
12591#define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos)
12593#define USBD_EPSTS_OV_Pos (7)
12594#define USBD_EPSTS_OV_Msk (0x1ul << USBD_EPSTS_OV_Pos)
12596#define USBD_EPSTS_EPSTS0_Pos (8)
12597#define USBD_EPSTS_EPSTS0_Msk (0x7ul << USBD_EPSTS_EPSTS0_Pos)
12599#define USBD_EPSTS_EPSTS1_Pos (11)
12600#define USBD_EPSTS_EPSTS1_Msk (0x7ul << USBD_EPSTS_EPSTS1_Pos)
12602#define USBD_EPSTS_EPSTS2_Pos (14)
12603#define USBD_EPSTS_EPSTS2_Msk (0x7ul << USBD_EPSTS_EPSTS2_Pos)
12605#define USBD_EPSTS_EPSTS3_Pos (17)
12606#define USBD_EPSTS_EPSTS3_Msk (0x7ul << USBD_EPSTS_EPSTS3_Pos)
12608#define USBD_EPSTS_EPSTS4_Pos (20)
12609#define USBD_EPSTS_EPSTS4_Msk (0x7ul << USBD_EPSTS_EPSTS4_Pos)
12611#define USBD_EPSTS_EPSTS5_Pos (23)
12612#define USBD_EPSTS_EPSTS5_Msk (0x7ul << USBD_EPSTS_EPSTS5_Pos)
12614#define USBD_EPSTS_EPSTS6_Pos (26)
12615#define USBD_EPSTS_EPSTS6_Msk (0x7ul << USBD_EPSTS_EPSTS6_Pos)
12617#define USBD_EPSTS_EPSTS7_Pos (29)
12618#define USBD_EPSTS_EPSTS7_Msk (0x7ul << USBD_EPSTS_EPSTS7_Pos)
12620#define USBD_ATTR_USBRST_Pos (0)
12621#define USBD_ATTR_USBRST_Msk (0x1ul << USBD_ATTR_USBRST_Pos)
12623#define USBD_ATTR_SUSPEND_Pos (1)
12624#define USBD_ATTR_SUSPEND_Msk (0x1ul << USBD_ATTR_SUSPEND_Pos)
12626#define USBD_ATTR_RESUME_Pos (2)
12627#define USBD_ATTR_RESUME_Msk (0x1ul << USBD_ATTR_RESUME_Pos)
12629#define USBD_ATTR_TOUT_Pos (3)
12630#define USBD_ATTR_TOUT_Msk (0x1ul << USBD_ATTR_TOUT_Pos)
12632#define USBD_ATTR_PHYEN_Pos (4)
12633#define USBD_ATTR_PHYEN_Msk (0x1ul << USBD_ATTR_PHYEN_Pos)
12635#define USBD_ATTR_RWAKEUP_Pos (5)
12636#define USBD_ATTR_RWAKEUP_Msk (0x1ul << USBD_ATTR_RWAKEUP_Pos)
12638#define USBD_ATTR_USBEN_Pos (7)
12639#define USBD_ATTR_USBEN_Msk (0x1ul << USBD_ATTR_USBEN_Pos)
12641#define USBD_ATTR_DPPUEN_Pos (8)
12642#define USBD_ATTR_DPPUEN_Msk (0x1ul << USBD_ATTR_DPPUEN_Pos)
12644#define USBD_ATTR_PWRDN_Pos (9)
12645#define USBD_ATTR_PWRDN_Msk (0x1ul << USBD_ATTR_PWRDN_Pos)
12647#define USBD_ATTR_BYTEM_Pos (10)
12648#define USBD_ATTR_BYTEM_Msk (0x1ul << USBD_ATTR_BYTEM_Pos)
12650#define USBD_VBUSDET_VBUSDET_Pos (0)
12651#define USBD_VBUSDET_VBUSDET_Msk (0x1ul << USBD_VBUSDET_VBUSDET_Pos)
12653#define USBD_STBUFSEG_STBUFSEG_Pos (3)
12654#define USBD_STBUFSEG_STBUFSEG_Msk (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos)
12656#define USBD_SE0_SE0_Pos (0)
12657#define USBD_SE0_SE0_Msk (0x1ul << USBD_SE0_SE0_Pos)
12659#define USBD_BUFSEG_BUFSEG_Pos (3)
12660#define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos)
12662#define USBD_MXPLD_MXPLD_Pos (0)
12663#define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos)
12665#define USBD_CFG_EPNUM_Pos (0)
12666#define USBD_CFG_EPNUM_Msk (0xful << USBD_CFG_EPNUM_Pos)
12668#define USBD_CFG_ISOCH_Pos (4)
12669#define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos)
12671#define USBD_CFG_STATE_Pos (5)
12672#define USBD_CFG_STATE_Msk (0x3ul << USBD_CFG_STATE_Pos)
12674#define USBD_CFG_DSQSYNC_Pos (7)
12675#define USBD_CFG_DSQSYNC_Msk (0x1ul << USBD_CFG_DSQSYNC_Pos)
12677#define USBD_CFG_CSTALL_Pos (9)
12678#define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos)
12680#define USBD_CFGP_CLRRDY_Pos (0)
12681#define USBD_CFGP_CLRRDY_Msk (0x1ul << USBD_CFGP_CLRRDY_Pos)
12683#define USBD_CFGP_SSTALL_Pos (1)
12684#define USBD_CFGP_SSTALL_Msk (0x1ul << USBD_CFGP_SSTALL_Pos) /* USB_CONST */ /* end of USB register group */
12688
12689
12690/*---------------------- USB Host Controller -------------------------*/
12697typedef struct
12698{
12699
12700
12701
12702
13212 __I uint32_t HcRevision; /* Offset: 0x00 Host Controller Revision Register */
13213 __IO uint32_t HcControl; /* Offset: 0x04 Host Controller Control Register */
13214 __IO uint32_t HcCommandStatus; /* Offset: 0x08 Host Controller CMD Status Register */
13215 __IO uint32_t HcInterruptStatus; /* Offset: 0x0C Host Controller Interrupt Status Register */
13216 __IO uint32_t HcInterruptEnable; /* Offset: 0x10 Host Controller Interrupt Enable Register */
13217 __IO uint32_t HcInterruptDisable; /* Offset: 0x14 Host Controller Interrupt Disable Register */
13218 __IO uint32_t HcHCCA; /* Offset: 0x18 Host Controller Communication Area Register */
13219 __IO uint32_t HcPeriodCurrentED; /* Offset: 0x1C Host Controller Period Current ED Register */
13220 __IO uint32_t HcControlHeadED; /* Offset: 0x20 Host Controller Control Head ED Register */
13221 __IO uint32_t HcControlCurrentED; /* Offset: 0x24 Host Controller Control Current ED Register */
13222 __IO uint32_t HcBulkHeadED; /* Offset: 0x28 Host Controller Bulk Head ED Register */
13223 __IO uint32_t HcBulkCurrentED; /* Offset: 0x2C Host Controller Bulk Current ED Register */
13224 __IO uint32_t HcDoneHead; /* Offset: 0x30 Host Controller Done Head Register */
13225 __IO uint32_t HcFmInterval; /* Offset: 0x34 Host Controller Frame Interval Register */
13226 __I uint32_t HcFmRemaining; /* Offset: 0x38 Host Controller Frame Remaining Register */
13227 __I uint32_t HcFmNumber; /* Offset: 0x3C Host Controller Frame Number Register */
13228 __IO uint32_t HcPeriodicStart; /* Offset: 0x40 Host Controller Periodic Start Register */
13229 __IO uint32_t HcLSThreshold; /* Offset: 0x44 Host Controller Low-speed Threshold Register */
13230 __IO uint32_t HcRhDescriptorA; /* Offset: 0x48 Host Controller Root Hub Descriptor A Register */
13231 __IO uint32_t HcRhDescriptorB; /* Offset: 0x4C Host Controller Root Hub Descriptor B Register */
13232 __IO uint32_t HcRhStatus; /* Offset: 0x50 Host Controller Root Hub Status Register */
13233 __IO uint32_t HcRhPortStatus[2]; /* Offset: 0x54 Host Controller Root Hub Port Status [1] */
13234 __I uint32_t RESERVE0[105];
13235 __IO uint32_t HcPhyControl; /* Offset: 0x200 USB Host Controller PHY Control Register */
13236 __IO uint32_t HcMiscControl; /* Offset: 0x204 USB Host Controller Miscellaneous Control Register */
13237
13238} USBH_T;
13239
13240
13241
13242
13248#define USBH_HcRevision_REV_Pos (0)
13249#define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos)
13251#define USBH_HcControl_CBSR_Pos (0)
13252#define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos)
13254#define USBH_HcControl_PLE_Pos (2)
13255#define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos)
13257#define USBH_HcControl_IE_Pos (3)
13258#define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos)
13260#define USBH_HcControl_CLE_Pos (4)
13261#define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos)
13263#define USBH_HcControl_BLE_Pos (5)
13264#define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos)
13266#define USBH_HcControl_HCFS_Pos (6)
13267#define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos)
13269#define USBH_HcCommandStatus_HCR_Pos (0)
13270#define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos)
13272#define USBH_HcCommandStatus_CLF_Pos (1)
13273#define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos)
13275#define USBH_HcCommandStatus_BLF_Pos (2)
13276#define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos)
13278#define USBH_HcCommandStatus_SOC_Pos (16)
13279#define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos)
13281#define USBH_HcInterruptStatus_SO_Pos (0)
13282#define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos)
13284#define USBH_HcInterruptStatus_WDH_Pos (1)
13285#define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos)
13287#define USBH_HcInterruptStatus_SF_Pos (2)
13288#define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos)
13290#define USBH_HcInterruptStatus_RD_Pos (3)
13291#define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos)
13293#define USBH_HcInterruptStatus_FNO_Pos (5)
13294#define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos)
13296#define USBH_HcInterruptStatus_RHSC_Pos (6)
13297#define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos)
13299#define USBH_HcInterruptEnable_SO_Pos (0)
13300#define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos)
13302#define USBH_HcInterruptEnable_WDH_Pos (1)
13303#define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos)
13305#define USBH_HcInterruptEnable_SF_Pos (2)
13306#define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos)
13308#define USBH_HcInterruptEnable_RD_Pos (3)
13309#define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos)
13311#define USBH_HcInterruptEnable_FNO_Pos (5)
13312#define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos)
13314#define USBH_HcInterruptEnable_RHSC_Pos (6)
13315#define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos)
13317#define USBH_HcInterruptEnable_MIE_Pos (31)
13318#define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos)
13320#define USBH_HcInterruptDisable_SO_Pos (0)
13321#define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos)
13323#define USBH_HcInterruptDisable_WDH_Pos (1)
13324#define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos)
13326#define USBH_HcInterruptDisable_SF_Pos (2)
13327#define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos)
13329#define USBH_HcInterruptDisable_RD_Pos (3)
13330#define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos)
13332#define USBH_HcInterruptDisable_FNO_Pos (5)
13333#define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos)
13335#define USBH_HcInterruptDisable_RHSC_Pos (6)
13336#define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos)
13338#define USBH_HcInterruptDisable_MIE_Pos (31)
13339#define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos)
13341#define USBH_HcHCCA_HCCA_Pos (8)
13342#define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos)
13344#define USBH_HcPeriodCurrentED_PCED_Pos (4)
13345#define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos)
13347#define USBH_HcControlHeadED_CHED_Pos (4)
13348#define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos)
13350#define USBH_HcControlCurrentED_CCED_Pos (4)
13351#define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos)
13353#define USBH_HcBulkHeadED_BHED_Pos (4)
13354#define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos)
13356#define USBH_HcBulkCurrentED_BCED_Pos (4)
13357#define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos)
13359#define USBH_HcDoneHead_DH_Pos (4)
13360#define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos)
13362#define USBH_HcFmInterval_FI_Pos (0)
13363#define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos)
13365#define USBH_HcFmInterval_FSMPS_Pos (16)
13366#define USBH_HcFmInterval_FSMPS_Msk (0x7ffful << USBH_HcFmInterval_FSMPS_Pos)
13368#define USBH_HcFmInterval_FIT_Pos (31)
13369#define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos)
13371#define USBH_HcFmRemaining_FR_Pos (0)
13372#define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos)
13374#define USBH_HcFmRemaining_FRT_Pos (31)
13375#define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos)
13377#define USBH_HcFmNumber_FN_Pos (0)
13378#define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos)
13380#define USBH_HcPeriodicStart_PS_Pos (0)
13381#define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos)
13383#define USBH_HcLSThreshold_LST_Pos (0)
13384#define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos)
13386#define USBH_HcRhDescriptorA_NDP_Pos (0)
13387#define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos)
13389#define USBH_HcRhDescriptorA_PSM_Pos (8)
13390#define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos)
13392#define USBH_HcRhDescriptorA_OCPM_Pos (11)
13393#define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos)
13395#define USBH_HcRhDescriptorA_NOCP_Pos (12)
13396#define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos)
13398#define USBH_HcRhDescriptorB_PPCM_Pos (16)
13399#define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos)
13401#define USBH_HcRhStatus_LPS_Pos (0)
13402#define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos)
13404#define USBH_HcRhStatus_OCI_Pos (1)
13405#define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos)
13407#define USBH_HcRhStatus_DRWE_Pos (15)
13408#define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos)
13410#define USBH_HcRhStatus_LPSC_Pos (16)
13411#define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos)
13413#define USBH_HcRhStatus_OCIC_Pos (17)
13414#define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos)
13416#define USBH_HcRhStatus_CRWE_Pos (31)
13417#define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos)
13419#define USBH_HcRhPortStatus_CCS_Pos (0)
13420#define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos)
13422#define USBH_HcRhPortStatus_PES_Pos (1)
13423#define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos)
13425#define USBH_HcRhPortStatus_PSS_Pos (2)
13426#define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos)
13428#define USBH_HcRhPortStatus_POCI_Pos (3)
13429#define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos)
13431#define USBH_HcRhPortStatus_PRS_Pos (4)
13432#define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos)
13434#define USBH_HcRhPortStatus_PPS_Pos (8)
13435#define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos)
13437#define USBH_HcRhPortStatus_LSDA_Pos (9)
13438#define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos)
13440#define USBH_HcRhPortStatus_CSC_Pos (16)
13441#define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos)
13443#define USBH_HcRhPortStatus_PESC_Pos (17)
13444#define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos)
13446#define USBH_HcRhPortStatus_PSSC_Pos (18)
13447#define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos)
13449#define USBH_HcRhPortStatus_OCIC_Pos (19)
13450#define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos)
13452#define USBH_HcRhPortStatus_PRSC_Pos (20)
13453#define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos)
13455#define USBH_HcPhyControl_STBYEN_Pos (27)
13456#define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos)
13458#define USBH_HcMiscControl_ABORT_Pos (1)
13459#define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos)
13461#define USBH_HcMiscControl_OCAL_Pos (3)
13462#define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos)
13464#define USBH_HcMiscControl_DPRT1_Pos (16)
13465#define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) /* USBH_CONST */ /* end of USBH register group */
13469
13470
13471
13472/*---------------------- Watch Dog Timer Controller -------------------------*/
13479typedef struct
13480{
13481
13482
13483
13484
13566 __IO uint32_t CTL; /* Offset: 0x00 WDT Control Register */
13567 __IO uint32_t ALTCTL; /* Offset: 0x04 WDT Alternative Control Register */
13568
13569} WDT_T;
13570
13571
13572
13578#define WDT_CTL_RSTCNT_Pos (0)
13579#define WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos)
13581#define WDT_CTL_RSTEN_Pos (1)
13582#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos)
13584#define WDT_CTL_RSTF_Pos (2)
13585#define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos)
13587#define WDT_CTL_IF_Pos (3)
13588#define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos)
13590#define WDT_CTL_WKEN_Pos (4)
13591#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos)
13593#define WDT_CTL_WKF_Pos (5)
13594#define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos)
13596#define WDT_CTL_INTEN_Pos (6)
13597#define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos)
13599#define WDT_CTL_WDTEN_Pos (7)
13600#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos)
13602#define WDT_CTL_TOUTSEL_Pos (8)
13603#define WDT_CTL_TOUTSEL_Msk (0x7ul << WDT_CTL_TOUTSEL_Pos)
13605#define WDT_CTL_ICEDEBUG_Pos (31)
13606#define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos)
13608#define WDT_ALTCTL_RSTDSEL_Pos (0)
13609#define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /* WDT_CONST */ /* end of WDT register group */
13613
13614
13615/*---------------------- Window Watchdog Timer -------------------------*/
13622typedef struct
13623{
13624
13625
13626
13627
13701 __O uint32_t RLDCNT; /* Offset: 0x00 WWDT Reload Counter Register */
13702 __IO uint32_t CTL; /* Offset: 0x04 WWDT Control Register */
13703 __IO uint32_t STATUS; /* Offset: 0x08 WWDT Status Register */
13704 __I uint32_t CNT; /* Offset: 0x0C WWDT Counter Value Register */
13705
13706} WWDT_T;
13707
13708
13709
13715#define WWDT_RLDCNT_WWDT_RLDCNT_Pos (0)
13716#define WWDT_RLDCNT_WWDT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_WWDT_RLDCNT_Pos)
13718#define WWDT_CTL_WWDTEN_Pos (0)
13719#define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos)
13721#define WWDT_CTL_INTEN_Pos (1)
13722#define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos)
13724#define WWDT_CTL_PSCSEL_Pos (8)
13725#define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos)
13727#define WWDT_CTL_CMPDAT_Pos (16)
13728#define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos)
13730#define WWDT_CTL_ICEDEBUG_Pos (31)
13731#define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos)
13733#define WWDT_STATUS_WWDTIF_Pos (0)
13734#define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos)
13736#define WWDT_STATUS_WWDTRF_Pos (1)
13737#define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos)
13739#define WWDT_CNT_CNTDAT_Pos (0)
13740#define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /* WWDT_CONST */ /* end of WWDT register group */
13744
13745 /* end of REGISTER group */
13747
13748
13749/******************************************************************************/
13750/* Peripheral memory map */
13751/******************************************************************************/
13756/* Peripheral and SRAM base address */
13757#define SRAM_BASE (0x20000000UL)
13758#define PERIPH_BASE (0x40000000UL)
13761/* Peripheral memory map */
13762#define AHBPERIPH_BASE PERIPH_BASE
13763#define APBPERIPH_BASE (PERIPH_BASE + 0x00040000)
13764
13766#define GCR_BASE (AHBPERIPH_BASE + 0x00000)
13767#define CLK_BASE (AHBPERIPH_BASE + 0x00200)
13768#define INT_BASE (AHBPERIPH_BASE + 0x00300)
13769#define GPIO_BASE (AHBPERIPH_BASE + 0x04000)
13770#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000)
13771#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040)
13772#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080)
13773#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0)
13774#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100)
13775#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140)
13776#define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440)
13777#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800)
13778#define PDMA_BASE (AHBPERIPH_BASE + 0x08000)
13779#define USBH_BASE (AHBPERIPH_BASE + 0x09000)
13780#define FMC_BASE (AHBPERIPH_BASE + 0x0C000)
13781#define EBI_BASE (AHBPERIPH_BASE + 0x10000)
13782#define CRC_BASE (AHBPERIPH_BASE + 0x31000)
13783
13785#define WDT_BASE (APBPERIPH_BASE + 0x00000)
13786#define WWDT_BASE (APBPERIPH_BASE + 0x00100)
13787#define TMR01_BASE (APBPERIPH_BASE + 0x10000)
13788#define PWM0_BASE (APBPERIPH_BASE + 0x18000)
13789#define SPI0_BASE (APBPERIPH_BASE + 0x20000)
13790#define UART0_BASE (APBPERIPH_BASE + 0x30000)
13791#define UART2_BASE (APBPERIPH_BASE + 0x32000)
13792#define I2C0_BASE (APBPERIPH_BASE + 0x40000)
13793#define SC0_BASE (APBPERIPH_BASE + 0x50000)
13794#define USBD_BASE (APBPERIPH_BASE + 0x80000)
13795
13797#define RTC_BASE (APBPERIPH_BASE + 0x01000)
13798#define EADC0_BASE (APBPERIPH_BASE + 0x03000)
13799#define TMR23_BASE (APBPERIPH_BASE + 0x11000)
13800#define PWM1_BASE (APBPERIPH_BASE + 0x19000)
13801#define SPI1_BASE (APBPERIPH_BASE + 0x21000)
13802#define UART1_BASE (APBPERIPH_BASE + 0x31000)
13803#define UART3_BASE (APBPERIPH_BASE + 0x33000)
13804#define I2C1_BASE (APBPERIPH_BASE + 0x41000) /* end of group MemoryMap */
13806
13807
13808/******************************************************************************/
13809/* Peripheral declaration */
13810/******************************************************************************/
13816#define SYS ((SYS_T *) GCR_BASE)
13817#define SYSINT ((SYS_INT_T *) INT_BASE)
13818#define CLK ((CLK_T *) CLK_BASE)
13819#define PA ((GPIO_T *) GPIOA_BASE)
13820#define PB ((GPIO_T *) GPIOB_BASE)
13821#define PC ((GPIO_T *) GPIOC_BASE)
13822#define PD ((GPIO_T *) GPIOD_BASE)
13823#define PE ((GPIO_T *) GPIOE_BASE)
13824#define PF ((GPIO_T *) GPIOF_BASE)
13825#define GPIO ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE)
13826#define PDMA ((PDMA_T *) PDMA_BASE)
13827#define USBH ((USBH_T *) USBH_BASE)
13828#define FMC ((FMC_T *) FMC_BASE)
13829#define EBI ((EBI_T *) EBI_BASE)
13830#define CRC ((CRC_T *) CRC_BASE)
13831
13832#define WDT ((WDT_T *) WDT_BASE)
13833#define WWDT ((WWDT_T *) WWDT_BASE)
13834#define RTC ((RTC_T *) RTC_BASE)
13835#define EADC ((EADC_T *) EADC0_BASE)
13836
13837#define USBD ((USBD_T *) USBD_BASE)
13838#define TIMER0 ((TIMER_T *) TMR01_BASE)
13839#define TIMER1 ((TIMER_T *) (TMR01_BASE + 0x20))
13840#define TIMER2 ((TIMER_T *) TMR23_BASE)
13841#define TIMER3 ((TIMER_T *) (TMR23_BASE + 0x20))
13842#define PWM0 ((PWM_T *) PWM0_BASE)
13843#define PWM1 ((PWM_T *) PWM1_BASE)
13844#define SPI0 ((SPI_T *) SPI0_BASE)
13845#define SPI1 ((SPI_T *) SPI1_BASE)
13846#define UART0 ((UART_T *) UART0_BASE)
13847#define UART1 ((UART_T *) UART1_BASE)
13848#define UART2 ((UART_T *) UART2_BASE)
13849#define UART3 ((UART_T *) UART3_BASE)
13850#define I2C0 ((I2C_T *) I2C0_BASE)
13851#define I2C1 ((I2C_T *) I2C1_BASE)
13852#define SC0 ((SC_T *) SC0_BASE)
13853
13854
13855/* One Bit Mask Definitions */
13856#define BIT0 0x00000001
13857#define BIT1 0x00000002
13858#define BIT2 0x00000004
13859#define BIT3 0x00000008
13860#define BIT4 0x00000010
13861#define BIT5 0x00000020
13862#define BIT6 0x00000040
13863#define BIT7 0x00000080
13864#define BIT8 0x00000100
13865#define BIT9 0x00000200
13866#define BIT10 0x00000400
13867#define BIT11 0x00000800
13868#define BIT12 0x00001000
13869#define BIT13 0x00002000
13870#define BIT14 0x00004000
13871#define BIT15 0x00008000
13872#define BIT16 0x00010000
13873#define BIT17 0x00020000
13874#define BIT18 0x00040000
13875#define BIT19 0x00080000
13876#define BIT20 0x00100000
13877#define BIT21 0x00200000
13878#define BIT22 0x00400000
13879#define BIT23 0x00800000
13880#define BIT24 0x01000000
13881#define BIT25 0x02000000
13882#define BIT26 0x04000000
13883#define BIT27 0x08000000
13884#define BIT28 0x10000000
13885#define BIT29 0x20000000
13886#define BIT30 0x40000000
13887#define BIT31 0x80000000
13888
13889/* Byte Mask Definitions */
13890#define BYTE0_Msk (0x000000FF)
13891#define BYTE1_Msk (0x0000FF00)
13892#define BYTE2_Msk (0x00FF0000)
13893#define BYTE3_Msk (0xFF000000)
13894
13895#define _GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) )
13896#define _GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8)
13897#define _GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16)
13898#define _GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24)
13900#ifndef TRUE
13901# define TRUE 1
13902#endif
13903#ifndef FALSE
13904# define FALSE 0
13905#endif
13906
13907#ifndef NULL
13908#define NULL 0
13909#endif
13910
13911#include "sys.h"
13912#include "clk.h"
13913#include "gpio.h"
13914#include "i2c.h"
13915#include "crc.h"
13916#include "ebi.h"
13917#include "rtc.h"
13918#include "timer.h"
13919#include "wdt.h"
13920#include "wwdt.h"
13921#include "spi.h"
13922#include "sc.h"
13923#include "scuart.h"
13924#include "eadc.h"
13925#include "usbd.h"
13926#include "fmc.h"
13927#include "uart.h"
13928#include "pwm.h"
13929#include "pdma.h"
13930
13931
13932typedef volatile unsigned char vu8;
13933typedef volatile unsigned long vu32;
13934typedef volatile unsigned short vu16;
13935#define M8(adr) (*((vu8 *) (adr)))
13936#define M16(adr) (*((vu16 *) (adr)))
13937#define M32(adr) (*((vu32 *) (adr)))
13938
13939#define outpw(port,value) (*((volatile unsigned int *)(port))=(value))
13940#define inpw(port) (*((volatile unsigned int *)(port)))
13941#define outpb(port,value) (*((volatile unsigned char *)(port))=(value))
13942#define inpb(port) (*((volatile unsigned char *)(port)))
13943#define outps(port,value) (*((volatile unsigned short *)(port))=(value))
13944#define inps(port) (*((volatile unsigned short *)(port)))
13945
13946#define outp32(port,value) (*((volatile unsigned int *)(port))=(value))
13947#define inp32(port) (*((volatile unsigned int *)(port)))
13948#define outp8(port,value) (*((volatile unsigned char *)(port))=(value))
13949#define inp8(port) (*((volatile unsigned char *)(port)))
13950#define outp16(port,value) (*((volatile unsigned short *)(port))=(value))
13951#define inp16(port) (*((volatile unsigned short *)(port)))
13952 /* end of group PeripheralDecl */
13954
13955#ifdef __cplusplus
13956}
13957#endif
13958
13959#endif /* __M471M_R1_S_H__ */
13960
13961
13962
13963
13964
M471M/R1/S CLK Header File.
M471M/R1/S CRC driver header file.
M471M/R1/S EADC driver header file.
M471M/R1/S EBI driver header file.
M471M/R1/S Flash Memory Controller Driver Header File.
M471M/R1/S GPIO driver header file.
enum IRQn IRQn_Type
IRQn
Definition: M471M_R1_S.h:69
@ PendSV_IRQn
Definition: M471M_R1_S.h:77
@ EINT0_IRQn
Definition: M471M_R1_S.h:90
@ GPF_IRQn
Definition: M471M_R1_S.h:101
@ USBH_IRQn
Definition: M471M_R1_S.h:128
@ I2C0_IRQn
Definition: M471M_R1_S.h:118
@ UART3_IRQn
Definition: M471M_R1_S.h:126
@ EINT3_IRQn
Definition: M471M_R1_S.h:93
@ EINT4_IRQn
Definition: M471M_R1_S.h:94
@ PWM1P2_IRQn
Definition: M471M_R1_S.h:111
@ GPA_IRQn
Definition: M471M_R1_S.h:96
@ ADC02_IRQn
Definition: M471M_R1_S.h:123
@ TAMPER_IRQn
Definition: M471M_R1_S.h:87
@ SC0_IRQn
Definition: M471M_R1_S.h:129
@ MemoryManagement_IRQn
Definition: M471M_R1_S.h:72
@ USBD_IRQn
Definition: M471M_R1_S.h:127
@ EINT2_IRQn
Definition: M471M_R1_S.h:92
@ PWRWU_IRQn
Definition: M471M_R1_S.h:84
@ SVCall_IRQn
Definition: M471M_R1_S.h:75
@ BRAKE0_IRQn
Definition: M471M_R1_S.h:104
@ EINT5_IRQn
Definition: M471M_R1_S.h:95
@ PWM0P2_IRQn
Definition: M471M_R1_S.h:107
@ PWM1P0_IRQn
Definition: M471M_R1_S.h:109
@ UsageFault_IRQn
Definition: M471M_R1_S.h:74
@ GPC_IRQn
Definition: M471M_R1_S.h:98
@ SysTick_IRQn
Definition: M471M_R1_S.h:78
@ ADC01_IRQn
Definition: M471M_R1_S.h:122
@ GPD_IRQn
Definition: M471M_R1_S.h:99
@ ADC03_IRQn
Definition: M471M_R1_S.h:124
@ WDT_IRQn
Definition: M471M_R1_S.h:88
@ PWM0P0_IRQn
Definition: M471M_R1_S.h:105
@ PDMA_IRQn
Definition: M471M_R1_S.h:120
@ TMR1_IRQn
Definition: M471M_R1_S.h:113
@ BusFault_IRQn
Definition: M471M_R1_S.h:73
@ WWDT_IRQn
Definition: M471M_R1_S.h:89
@ DebugMonitor_IRQn
Definition: M471M_R1_S.h:76
@ TMR2_IRQn
Definition: M471M_R1_S.h:114
@ PWM1P1_IRQn
Definition: M471M_R1_S.h:110
@ UART1_IRQn
Definition: M471M_R1_S.h:117
@ IRC_IRQn
Definition: M471M_R1_S.h:83
@ PWM0P1_IRQn
Definition: M471M_R1_S.h:106
@ SPI1_IRQn
Definition: M471M_R1_S.h:103
@ UART2_IRQn
Definition: M471M_R1_S.h:125
@ TMR0_IRQn
Definition: M471M_R1_S.h:112
@ BOD_IRQn
Definition: M471M_R1_S.h:82
@ CKFAIL_IRQn
Definition: M471M_R1_S.h:85
@ BRAKE1_IRQn
Definition: M471M_R1_S.h:108
@ EINT1_IRQn
Definition: M471M_R1_S.h:91
@ RTC_IRQn
Definition: M471M_R1_S.h:86
@ NonMaskableInt_IRQn
Definition: M471M_R1_S.h:71
@ TMR3_IRQn
Definition: M471M_R1_S.h:115
@ UART0_IRQn
Definition: M471M_R1_S.h:116
@ GPE_IRQn
Definition: M471M_R1_S.h:100
@ I2C1_IRQn
Definition: M471M_R1_S.h:119
@ GPB_IRQn
Definition: M471M_R1_S.h:97
@ SPI0_IRQn
Definition: M471M_R1_S.h:102
@ ADC00_IRQn
Definition: M471M_R1_S.h:121
__IO uint32_t HcBulkCurrentED
Definition: M471M_R1_S.h:13223
__IO uint32_t DAT
Definition: M471M_R1_S.h:11883
__I uint32_t CNT
Definition: M471M_R1_S.h:11255
__O uint32_t SSTRG
Definition: M471M_R1_S.h:5866
__I uint32_t FCAPDAT2
Definition: M471M_R1_S.h:5878
__IO uint32_t SRAM_BISTCTL
Definition: M471M_R1_S.h:10332
__IO uint32_t PWRCTL
Definition: M471M_R1_S.h:1413
__IO uint32_t CLKTOUT
Definition: M471M_R1_S.h:3723
__IO uint32_t DTCTL2_3
Definition: M471M_R1_S.h:5832
__IO uint32_t FTCTL
Definition: M471M_R1_S.h:2341
__IO uint32_t I2SCLK
Definition: M471M_R1_S.h:9317
__IO uint32_t DAT
Definition: M471M_R1_S.h:8492
__IO uint32_t SE0
Definition: M471M_R1_S.h:12517
__IO uint32_t TOUTEN
Definition: M471M_R1_S.h:4338
__IO uint32_t ISPCMD
Definition: M471M_R1_S.h:2338
__I uint32_t MPADDR
Definition: M471M_R1_S.h:2351
__IO uint32_t CLKFMT
Definition: M471M_R1_S.h:7642
__IO uint32_t ADDR2
Definition: M471M_R1_S.h:3708
__IO uint32_t APBCLK0
Definition: M471M_R1_S.h:1415
__IO uint32_t INTEN
Definition: M471M_R1_S.h:11884
__IO uint32_t CFG
Definition: M471M_R1_S.h:12273
__IO uint32_t SCATSTS
Definition: M471M_R1_S.h:4335
__IO uint32_t SEED
Definition: M471M_R1_S.h:1810
__IO uint32_t CTL
Definition: M471M_R1_S.h:723
__IO uint32_t TOUTIEN
Definition: M471M_R1_S.h:4339
__IO uint32_t CNTEN
Definition: M471M_R1_S.h:5823
__IO uint32_t REQSEL8_11
Definition: M471M_R1_S.h:4348
__IO uint32_t TMRCTL2
Definition: M471M_R1_S.h:8504
__IO uint32_t IRC48MTIEN
Definition: M471M_R1_S.h:10342
__IO uint32_t FIFOSTS
Definition: M471M_R1_S.h:11889
__I uint32_t RCAPDAT5
Definition: M471M_R1_S.h:5883
__IO uint32_t HcRhDescriptorB
Definition: M471M_R1_S.h:13231
__IO uint32_t PRISET
Definition: M471M_R1_S.h:4329
__IO uint32_t IPRST2
Definition: M471M_R1_S.h:10312
__IO uint32_t FTCMPDAT4_5
Definition: M471M_R1_S.h:5863
__IO uint32_t ISPTRG
Definition: M471M_R1_S.h:2339
__IO uint32_t I2SCTL
Definition: M471M_R1_S.h:9316
__IO uint32_t HcPhyControl
Definition: M471M_R1_S.h:13235
__IO uint32_t REGLCTL
Definition: M471M_R1_S.h:10339
__IO uint32_t SA
Definition: M471M_R1_S.h:3993
__IO uint32_t IRCTISTS
Definition: M471M_R1_S.h:10337
__IO uint32_t INTEN
Definition: M471M_R1_S.h:12509
__IO uint32_t MPDAT2
Definition: M471M_R1_S.h:2347
__IO uint32_t ALTCTL
Definition: M471M_R1_S.h:8494
__I uint32_t TMRDAT0
Definition: M471M_R1_S.h:8506
__IO uint32_t SLEWCTL
Definition: M471M_R1_S.h:2662
__IO uint32_t GPA_MFPH
Definition: M471M_R1_S.h:10321
__IO uint32_t PENDSTS
Definition: M471M_R1_S.h:725
__IO uint32_t APBCLK1
Definition: M471M_R1_S.h:1416
__IO uint32_t ALTCTL
Definition: M471M_R1_S.h:11894
__IO uint32_t CLKSRC
Definition: M471M_R1_S.h:5819
__IO uint32_t CLKOCTL
Definition: M471M_R1_S.h:1428
__IO uint32_t LXTCTL
Definition: M471M_R1_S.h:7655
__I uint32_t NMISTS
Definition: M471M_R1_S.h:10976
__IO uint32_t HcFmInterval
Definition: M471M_R1_S.h:13225
__I uint32_t TACTSTS
Definition: M471M_R1_S.h:4336
__IO uint32_t INTSTS
Definition: M471M_R1_S.h:11254
__IO uint32_t ETUCTL
Definition: M471M_R1_S.h:8497
__IO uint32_t CTL0
Definition: M471M_R1_S.h:1996
__IO uint32_t CLKDIV1
Definition: M471M_R1_S.h:1422
__IO uint32_t TOC6_7
Definition: M471M_R1_S.h:4344
__I uint32_t FCAPDAT3
Definition: M471M_R1_S.h:5880
__IO uint32_t TAMPCTL
Definition: M471M_R1_S.h:7658
__IO uint32_t BUSTCTL
Definition: M471M_R1_S.h:3718
__IO uint32_t OVSTS
Definition: M471M_R1_S.h:726
__IO uint32_t I2SSTS
Definition: M471M_R1_S.h:9318
__IO uint32_t TDSTS
Definition: M471M_R1_S.h:4334
__IO uint32_t LXTICTL
Definition: M471M_R1_S.h:7657
__IO uint32_t RSTSTS
Definition: M471M_R1_S.h:10309
__IO uint32_t CLKSEL1
Definition: M471M_R1_S.h:1418
__I uint32_t RCAPDAT2
Definition: M471M_R1_S.h:5877
__I uint32_t STATUS0
Definition: M471M_R1_S.h:732
__IO uint32_t ADDR3
Definition: M471M_R1_S.h:3709
__O uint32_t RWEN
Definition: M471M_R1_S.h:7638
__IO uint32_t FREQADJ
Definition: M471M_R1_S.h:7639
__IO uint32_t IFA
Definition: M471M_R1_S.h:5857
__IO uint32_t WGCTL0
Definition: M471M_R1_S.h:5841
__I uint32_t RCAPDAT3
Definition: M471M_R1_S.h:5879
__IO uint32_t DINOFF
Definition: M471M_R1_S.h:2653
__IO uint32_t ADDRMSK1
Definition: M471M_R1_S.h:3711
__IO uint32_t CNTCLR
Definition: M471M_R1_S.h:5824
__IO uint32_t FTCMPDAT2_3
Definition: M471M_R1_S.h:5862
__IO uint32_t INTEN1
Definition: M471M_R1_S.h:5854
__IO uint32_t INTSTS0
Definition: M471M_R1_S.h:5855
__I uint32_t FTCBUF4_5
Definition: M471M_R1_S.h:5898
__IO uint32_t MPDAT0
Definition: M471M_R1_S.h:2345
__IO uint32_t CAMSK
Definition: M471M_R1_S.h:7651
__IO uint32_t FIFOCTL
Definition: M471M_R1_S.h:9309
__IO uint32_t GPB_MFPH
Definition: M471M_R1_S.h:10323
__IO uint32_t CLKPSC0_1
Definition: M471M_R1_S.h:5820
__IO uint32_t HcInterruptDisable
Definition: M471M_R1_S.h:13217
__IO uint32_t STATUS
Definition: M471M_R1_S.h:9310
__IO uint32_t IRC48MTCTL
Definition: M471M_R1_S.h:10341
__IO uint32_t VREFCTL
Definition: M471M_R1_S.h:10318
__IO uint32_t EADCTS1
Definition: M471M_R1_S.h:5860
__IO uint32_t DBEN
Definition: M471M_R1_S.h:2657
__IO uint32_t CTL
Definition: M471M_R1_S.h:9305
__I uint32_t CURDAT
Definition: M471M_R1_S.h:722
__IO uint32_t TOC0_1
Definition: M471M_R1_S.h:4341
__IO uint32_t IRCTIEN
Definition: M471M_R1_S.h:10336
__IO uint32_t MPDAT3
Definition: M471M_R1_S.h:2348
__IO uint32_t SSCTL
Definition: M471M_R1_S.h:5865
__I uint32_t RX
Definition: M471M_R1_S.h:9314
__IO uint32_t ADDR0
Definition: M471M_R1_S.h:3702
__IO uint32_t HcLSThreshold
Definition: M471M_R1_S.h:13229
__IO uint32_t TCTL0
Definition: M471M_R1_S.h:1997
__IO uint32_t INTEN
Definition: M471M_R1_S.h:8498
__IO uint32_t DTCTL0_1
Definition: M471M_R1_S.h:5831
__IO uint32_t INTSTS
Definition: M471M_R1_S.h:7648
__O uint32_t STOP
Definition: M471M_R1_S.h:4326
__IO uint32_t TOCTL
Definition: M471M_R1_S.h:3706
__O uint32_t PRICLR
Definition: M471M_R1_S.h:4330
__IO uint32_t IVSCTL
Definition: M471M_R1_S.h:10315
__IO uint32_t CLKDIV0
Definition: M471M_R1_S.h:1421
__IO uint32_t CLKSEL0
Definition: M471M_R1_S.h:1417
__IO uint32_t MODE
Definition: M471M_R1_S.h:2652
__IO uint32_t PORCTL
Definition: M471M_R1_S.h:10317
__I uint32_t FCAPDAT1
Definition: M471M_R1_S.h:5876
__IO uint32_t MPDAT1
Definition: M471M_R1_S.h:2346
__IO uint32_t CLKDIV
Definition: M471M_R1_S.h:3705
__IO uint32_t DATMSK
Definition: M471M_R1_S.h:2655
__I uint32_t TRGSTS
Definition: M471M_R1_S.h:4328
__IO uint32_t CTL
Definition: M471M_R1_S.h:8493
__IO uint32_t LXTOCTL
Definition: M471M_R1_S.h:7656
__IO uint32_t MSKEN
Definition: M471M_R1_S.h:5843
__IO uint32_t FUNCSEL
Definition: M471M_R1_S.h:11895
__IO uint32_t BAUD
Definition: M471M_R1_S.h:11892
__I uint32_t FCAPDAT5
Definition: M471M_R1_S.h:5884
__IO uint32_t CTL
Definition: M471M_R1_S.h:3701
__IO uint32_t CAPIF
Definition: M471M_R1_S.h:5891
__I uint32_t CAPSTS
Definition: M471M_R1_S.h:5872
__IO uint32_t TOC4_5
Definition: M471M_R1_S.h:4343
__I uint32_t FCAPDAT0
Definition: M471M_R1_S.h:5874
__IO uint32_t FTCI
Definition: M471M_R1_S.h:5899
__IO uint32_t MXPLD
Definition: M471M_R1_S.h:12272
__IO uint32_t SYNC
Definition: M471M_R1_S.h:5817
__IO uint32_t DAT
Definition: M471M_R1_S.h:3703
__IO uint32_t EINTSTS
Definition: M471M_R1_S.h:11258
__I uint32_t PKTCRC
Definition: M471M_R1_S.h:3721
volatile unsigned long vu32
Definition: M471M_R1_S.h:13933
__IO uint32_t CFGP
Definition: M471M_R1_S.h:12274
__I uint32_t ISPSTS
Definition: M471M_R1_S.h:2343
__IO uint32_t INTSTS1
Definition: M471M_R1_S.h:5856
__O uint32_t SWREQ
Definition: M471M_R1_S.h:4327
__IO uint32_t PDMACTL
Definition: M471M_R1_S.h:9308
__I uint32_t STATUS
Definition: M471M_R1_S.h:1426
__I uint32_t PIN
Definition: M471M_R1_S.h:2656
__I uint32_t RCAPDAT4
Definition: M471M_R1_S.h:5881
__I uint32_t CHECKSUM
Definition: M471M_R1_S.h:1811
__IO uint32_t ADDR1
Definition: M471M_R1_S.h:3707
__IO uint32_t POLCTL
Definition: M471M_R1_S.h:5850
__IO uint32_t BUSTOUT
Definition: M471M_R1_S.h:3722
__IO uint32_t TAMSK
Definition: M471M_R1_S.h:7650
__IO uint32_t ISPADDR
Definition: M471M_R1_S.h:2336
__IO uint32_t STATUS
Definition: M471M_R1_S.h:8500
__IO uint32_t GPE_MFPL
Definition: M471M_R1_S.h:10328
__IO uint32_t HcHCCA
Definition: M471M_R1_S.h:13218
__IO uint32_t PINCTL
Definition: M471M_R1_S.h:8501
__IO uint32_t INTTYPE
Definition: M471M_R1_S.h:2658
__IO uint32_t CMP
Definition: M471M_R1_S.h:11253
__IO uint32_t TMRCTL0
Definition: M471M_R1_S.h:8502
__IO uint32_t INTEN0
Definition: M471M_R1_S.h:5853
__O uint32_t SWBRK
Definition: M471M_R1_S.h:5852
__I uint32_t CAP
Definition: M471M_R1_S.h:11256
__IO uint32_t STATUS2
Definition: M471M_R1_S.h:734
__I uint32_t CNT
Definition: M471M_R1_S.h:13704
__IO uint32_t CTL0
Definition: M471M_R1_S.h:5815
__IO uint32_t CTL
Definition: M471M_R1_S.h:11252
__IO uint32_t WGCTL1
Definition: M471M_R1_S.h:5842
__IO uint32_t NEXT
Definition: M471M_R1_S.h:3995
__IO uint32_t REQSEL4_7
Definition: M471M_R1_S.h:4347
__IO uint32_t USBPHY
Definition: M471M_R1_S.h:10319
__IO uint32_t NMIEN
Definition: M471M_R1_S.h:10975
__I uint32_t EPSTS
Definition: M471M_R1_S.h:12512
__IO uint32_t SCATBA
Definition: M471M_R1_S.h:4340
__IO uint32_t SSCTL
Definition: M471M_R1_S.h:9307
__IO uint32_t GPE_MFPH
Definition: M471M_R1_S.h:10329
__IO uint32_t AHBCLK
Definition: M471M_R1_S.h:1414
__IO uint32_t CLKPSC2_3
Definition: M471M_R1_S.h:5821
__I uint32_t FTCBUF0_1
Definition: M471M_R1_S.h:5896
__IO uint32_t TMRCTL1
Definition: M471M_R1_S.h:8503
__IO uint32_t DOUT
Definition: M471M_R1_S.h:2654
__IO uint32_t GPD_MFPL
Definition: M471M_R1_S.h:10326
__IO uint32_t HcControl
Definition: M471M_R1_S.h:13213
__IO uint32_t STATUS
Definition: M471M_R1_S.h:13703
__I uint32_t PDID
Definition: M471M_R1_S.h:10308
__IO uint32_t ADDRMSK2
Definition: M471M_R1_S.h:3712
__I uint32_t PDMACAP2_3
Definition: M471M_R1_S.h:5887
__IO uint32_t GPA_MFPL
Definition: M471M_R1_S.h:10320
__IO uint32_t INTEN
Definition: M471M_R1_S.h:2659
__IO uint32_t INIT
Definition: M471M_R1_S.h:7637
__IO uint32_t PHS2_3
Definition: M471M_R1_S.h:5836
__IO uint32_t CLKPSC4_5
Definition: M471M_R1_S.h:5822
__IO uint32_t BUSSTS
Definition: M471M_R1_S.h:3719
__IO uint32_t STBUFSEG
Definition: M471M_R1_S.h:12515
__IO uint32_t ISPDAT
Definition: M471M_R1_S.h:2337
__I uint32_t SRAM_BISTSTS
Definition: M471M_R1_S.h:10333
__I uint32_t DFBA
Definition: M471M_R1_S.h:2340
__IO uint32_t FIFO
Definition: M471M_R1_S.h:11885
__IO uint32_t CDUPB
Definition: M471M_R1_S.h:1432
volatile unsigned short vu16
Definition: M471M_R1_S.h:13934
__IO uint32_t CTL1
Definition: M471M_R1_S.h:1999
__I uint32_t HcRevision
Definition: M471M_R1_S.h:13212
__IO uint32_t BODCTL
Definition: M471M_R1_S.h:10314
__IO uint32_t EXTCTL
Definition: M471M_R1_S.h:11257
__I uint32_t STATUS3
Definition: M471M_R1_S.h:735
__IO uint32_t HcDoneHead
Definition: M471M_R1_S.h:13224
__IO uint32_t FADDR
Definition: M471M_R1_S.h:12511
__IO uint32_t MODEM
Definition: M471M_R1_S.h:11887
__IO uint32_t MODEMSTS
Definition: M471M_R1_S.h:11888
__IO uint32_t BUFSEG
Definition: M471M_R1_S.h:12271
__IO uint32_t HcPeriodCurrentED
Definition: M471M_R1_S.h:13219
__I uint32_t LEAPYEAR
Definition: M471M_R1_S.h:7646
__I uint32_t FTCBUF2_3
Definition: M471M_R1_S.h:5897
__IO uint32_t IRCTCTL
Definition: M471M_R1_S.h:10335
__IO uint32_t ABTSTS
Definition: M471M_R1_S.h:4333
__IO uint32_t ADDRMSK0
Definition: M471M_R1_S.h:3710
__IO uint32_t CAPINEN
Definition: M471M_R1_S.h:5870
__IO uint32_t CLKDCTL
Definition: M471M_R1_S.h:1430
__IO uint32_t CLKDIV
Definition: M471M_R1_S.h:9306
__IO uint32_t DTCTL4_5
Definition: M471M_R1_S.h:5833
__IO uint32_t DBCTL
Definition: M471M_R1_S.h:2707
__IO uint32_t IRC48MTISTS
Definition: M471M_R1_S.h:10343
__O uint32_t TX
Definition: M471M_R1_S.h:9312
__I uint32_t VBUSDET
Definition: M471M_R1_S.h:12514
__IO uint32_t SPRCTL
Definition: M471M_R1_S.h:7652
__IO uint32_t INTSTS
Definition: M471M_R1_S.h:8499
__IO uint32_t TALM
Definition: M471M_R1_S.h:7644
__IO uint32_t HcBulkHeadED
Definition: M471M_R1_S.h:13222
__IO uint32_t UARTCTL
Definition: M471M_R1_S.h:8505
__IO uint32_t DAT
Definition: M471M_R1_S.h:1809
__IO uint32_t HcControlCurrentED
Definition: M471M_R1_S.h:13221
__IO uint32_t CALM
Definition: M471M_R1_S.h:7645
__IO uint32_t CLKDSTS
Definition: M471M_R1_S.h:1431
__IO uint32_t BNF
Definition: M471M_R1_S.h:5845
__IO uint32_t TCTL1
Definition: M471M_R1_S.h:2000
__I uint32_t RCAPDAT1
Definition: M471M_R1_S.h:5875
__I uint32_t STATUS1
Definition: M471M_R1_S.h:733
__IO uint32_t BRKCTL2_3
Definition: M471M_R1_S.h:5848
__O uint32_t RLDCNT
Definition: M471M_R1_S.h:13701
__IO uint32_t BUSCTL
Definition: M471M_R1_S.h:3717
__IO uint32_t INTEN
Definition: M471M_R1_S.h:7647
__IO uint32_t ALTCTL
Definition: M471M_R1_S.h:13567
__IO uint32_t GPC_MFPH
Definition: M471M_R1_S.h:10325
__IO uint32_t INTSTS
Definition: M471M_R1_S.h:4332
__IO uint32_t TOUT
Definition: M471M_R1_S.h:11891
__I uint32_t HcFmRemaining
Definition: M471M_R1_S.h:13226
__IO uint32_t IRDA
Definition: M471M_R1_S.h:11893
__IO uint32_t TIME
Definition: M471M_R1_S.h:7640
__IO uint32_t HcMiscControl
Definition: M471M_R1_S.h:13236
__IO uint32_t INTEN
Definition: M471M_R1_S.h:4331
__IO uint32_t CLKSEL2
Definition: M471M_R1_S.h:1419
__I uint32_t HcFmNumber
Definition: M471M_R1_S.h:13227
__I uint32_t MPSTS
Definition: M471M_R1_S.h:2350
__IO uint32_t ADDRMSK3
Definition: M471M_R1_S.h:3713
__IO uint32_t HcInterruptStatus
Definition: M471M_R1_S.h:13215
__IO uint32_t CTL
Definition: M471M_R1_S.h:13702
__IO uint32_t MSK
Definition: M471M_R1_S.h:5844
__IO uint32_t CTL1
Definition: M471M_R1_S.h:5816
__IO uint32_t PHS0_1
Definition: M471M_R1_S.h:5835
__IO uint32_t HcRhStatus
Definition: M471M_R1_S.h:13232
__IO uint32_t LOAD
Definition: M471M_R1_S.h:5825
__IO uint32_t CAL
Definition: M471M_R1_S.h:7641
__IO uint32_t GPC_MFPL
Definition: M471M_R1_S.h:10324
__IO uint32_t INTSRC
Definition: M471M_R1_S.h:2660
__IO uint32_t CTL
Definition: M471M_R1_S.h:1808
__IO uint32_t TOC2_3
Definition: M471M_R1_S.h:4342
__I uint32_t PDMACAP4_5
Definition: M471M_R1_S.h:5888
__IO uint32_t REQSEL0_3
Definition: M471M_R1_S.h:4346
__IO uint32_t DRVCTL
Definition: M471M_R1_S.h:2663
__IO uint32_t INTSTS
Definition: M471M_R1_S.h:12510
__IO uint32_t TICK
Definition: M471M_R1_S.h:7649
__IO uint32_t RXTOUT
Definition: M471M_R1_S.h:8496
__IO uint32_t CDLOWB
Definition: M471M_R1_S.h:1433
__IO uint32_t HcPeriodicStart
Definition: M471M_R1_S.h:13228
__IO uint32_t INTSTS
Definition: M471M_R1_S.h:11890
__IO uint32_t PKTSIZE
Definition: M471M_R1_S.h:3720
__IO uint32_t WEEKDAY
Definition: M471M_R1_S.h:7643
__IO uint32_t CAPIEN
Definition: M471M_R1_S.h:5890
__IO uint32_t GPD_MFPH
Definition: M471M_R1_S.h:10327
__O uint32_t SWTRG
Definition: M471M_R1_S.h:724
__IO uint32_t POEN
Definition: M471M_R1_S.h:5851
__IO uint32_t CTL
Definition: M471M_R1_S.h:13566
__IO uint32_t CTL
Definition: M471M_R1_S.h:3992
__I uint32_t TMRDAT1_2
Definition: M471M_R1_S.h:8507
__IO uint32_t CHCTL
Definition: M471M_R1_S.h:4325
__IO uint32_t PDMACTL
Definition: M471M_R1_S.h:5885
__I uint32_t STATUS
Definition: M471M_R1_S.h:3704
__IO uint32_t IPRST0
Definition: M471M_R1_S.h:10310
__IO uint32_t EGT
Definition: M471M_R1_S.h:8495
__IO uint32_t STATUS
Definition: M471M_R1_S.h:5868
__I uint32_t FCAPDAT4
Definition: M471M_R1_S.h:5882
__IO uint32_t HcInterruptEnable
Definition: M471M_R1_S.h:13216
__IO uint32_t FTCMPDAT0_1
Definition: M471M_R1_S.h:5861
__IO uint32_t CAPCTL
Definition: M471M_R1_S.h:5871
__IO uint32_t SMTEN
Definition: M471M_R1_S.h:2661
__IO uint32_t ISPCTL
Definition: M471M_R1_S.h:2335
__IO uint32_t HcRhDescriptorA
Definition: M471M_R1_S.h:13230
__IO uint32_t FAILBRK
Definition: M471M_R1_S.h:5846
volatile unsigned char vu8
Definition: M471M_R1_S.h:13932
__IO uint32_t BRKCTL0_1
Definition: M471M_R1_S.h:5847
__IO uint32_t EADCTS0
Definition: M471M_R1_S.h:5859
__IO uint32_t GPF_MFPL
Definition: M471M_R1_S.h:10330
__IO uint32_t CLKSEL3
Definition: M471M_R1_S.h:1420
__IO uint32_t PLLCTL
Definition: M471M_R1_S.h:1424
__IO uint32_t WKSTS
Definition: M471M_R1_S.h:3716
__IO uint32_t GPB_MFPL
Definition: M471M_R1_S.h:10322
__IO uint32_t BRKCTL4_5
Definition: M471M_R1_S.h:5849
__IO uint32_t ATTR
Definition: M471M_R1_S.h:12513
__I uint32_t PDMACAP0_1
Definition: M471M_R1_S.h:5886
__IO uint32_t HcCommandStatus
Definition: M471M_R1_S.h:13214
__IO uint32_t IPRST1
Definition: M471M_R1_S.h:10311
__IO uint32_t DA
Definition: M471M_R1_S.h:3994
__IO uint32_t LINE
Definition: M471M_R1_S.h:11886
__IO uint32_t WKCTL
Definition: M471M_R1_S.h:3715
__I uint32_t RCAPDAT0
Definition: M471M_R1_S.h:5873
__IO uint32_t HcControlHeadED
Definition: M471M_R1_S.h:13220
__IO uint32_t PHS4_5
Definition: M471M_R1_S.h:5837
__IO uint32_t SWSYNC
Definition: M471M_R1_S.h:5818
M471M/R1/S I2C Driver Header File.
M471M/R1/S PDMA driver header file.
M471M/R1/S PWM driver header file.
M471M/R1/S RTC driver header file.
M471M/R1/S Smartcard (SC) driver header file.
M471M/R1/S Smartcard UART mode (SCUART) driver header file.
M471M/R1/S SPI driver header file.
USBD endpoints register.
Definition: M471M_R1_S.h:12202
M471M/R1/S SYS Header File.
M471M/R1/S Timer driver header file.
M471M/R1/S UART driver header file.
M471M/R1/S Timer USBD driver header file.
M471M/R1/S WDT driver header file.
M471M/R1/S WWDT driver header file.