M471M/R1/S BSP V3.01.000
The Board Support Package for M4521
Macros | Functions
Collaboration diagram for EADC Exported Functions:

Macros

#define EADC_CONV_RESET(eadc)   ((eadc)->CTL |= EADC_CTL_ADRST_Msk)
 A/D Converter Control Circuits Reset. More...
 
#define EADC_ENABLE_PDMA(eadc)   ((eadc)->CTL |= EADC_CTL_PDMAEN_Msk)
 Enable PDMA transfer. More...
 
#define EADC_DISABLE_PDMA(eadc)   ((eadc)->CTL &= (~EADC_CTL_PDMAEN_Msk))
 Disable PDMA transfer. More...
 
#define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum)   ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk)
 Enable double buffer mode. More...
 
#define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum)   ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk)
 Disable double buffer mode. More...
 
#define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum)   ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk)
 Set ADIFn at A/D end of conversion. More...
 
#define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum)   ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk)
 Set ADIFn at A/D start of conversion. More...
 
#define EADC_ENABLE_INT(eadc, u32Mask)   ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos))
 Enable the interrupt. More...
 
#define EADC_DISABLE_INT(eadc, u32Mask)   ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos))
 Disable the interrupt. More...
 
#define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask)   ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask))
 Enable the sample module interrupt. More...
 
#define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask)   ((eadc)->INTSRC[(u32IntSel)] &= ~(u32ModuleMask))
 Disable the sample module interrupt. More...
 
#define EADC_SET_DMOF(eadc, u32Format)   ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format))
 Set the input mode output format. More...
 
#define EADC_START_CONV(eadc, u32ModuleMask)   ((eadc)->SWTRG = (u32ModuleMask))
 Start the A/D conversion. More...
 
#define EADC_STOP_CONV(eadc, u32ModuleMask)   ((eadc)->PENDSTS = (u32ModuleMask))
 Cancel the conversion for sample module. More...
 
#define EADC_GET_PENDING_CONV(eadc)   ((eadc)->PENDSTS)
 Get the conversion pending flag. More...
 
#define EADC_GET_CONV_DATA(eadc, u32ModuleNum)   ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk)
 Get the conversion data of the user-specified sample module. More...
 
#define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask)   ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask))
 Get the data overrun flag of the user-specified sample module. More...
 
#define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask)   ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask))
 Get the data valid flag of the user-specified sample module. More...
 
#define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum)   ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT_RESULT_Msk)
 Get the double data of the user-specified sample module. More...
 
#define EADC_GET_INT_FLAG(eadc, u32Mask)   ((eadc)->STATUS2 & (u32Mask))
 Get the user-specified interrupt flags. More...
 
#define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask)   ((eadc)->OVSTS & (u32ModuleMask))
 Get the user-specified sample module overrun flags. More...
 
#define EADC_CLR_INT_FLAG(eadc, u32Mask)   ((eadc)->STATUS2 = (u32Mask))
 Clear the selected interrupt status bits. More...
 
#define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask)   ((eadc)->OVSTS = (u32ModuleMask))
 Clear the selected sample module overrun status bits. More...
 
#define EADC_IS_DATA_OV(eadc)   (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos)
 Check all sample module A/D result data register overrun flags. More...
 
#define EADC_IS_DATA_VALID(eadc)   (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos)
 Check all sample module A/D result data register valid flags. More...
 
#define EADC_IS_SAMPLE_MODULE_OV(eadc)   (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos)
 Check all A/D sample module start of conversion overrun flags. More...
 
#define EADC_IS_INT_FLAG_OV(eadc)   (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos)
 Check all A/D interrupt flag overrun bits. More...
 
#define EADC_IS_BUSY(eadc)   (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos)
 Get the busy state of EADC. More...
 
#define EADC_ENABLE_CMP0(eadc, u32ModuleNum, u32Condition, u16CMPData, u32MatchCount)
 Configure the comparator 0 and enable it. More...
 
#define EADC_ENABLE_CMP1(eadc, u32ModuleNum, u32Condition, u16CMPData, u32MatchCount)
 Configure the comparator 1 and enable it. More...
 
#define EADC_ENABLE_CMP2(eadc, u32ModuleNum, u32Condition, u16CMPData, u32MatchCount)
 Configure the comparator 2 and enable it. More...
 
#define EADC_ENABLE_CMP3(eadc, u32ModuleNum, u32Condition, u16CMPData, u32MatchCount)
 Configure the comparator 3 and enable it. More...
 
#define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP)   ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk)
 Enable the compare window mode. More...
 
#define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP)   ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk)
 Disable the compare window mode. More...
 
#define EADC_ENABLE_CMP_INT(eadc, u32CMP)   ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk)
 Enable the compare interrupt. More...
 
#define EADC_DISABLE_CMP_INT(eadc, u32CMP)   ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk)
 Disable the compare interrupt. More...
 
#define EADC_DISABLE_CMP0(eadc)   ((eadc)->CMP[0] = 0)
 Disable comparator 0. More...
 
#define EADC_DISABLE_CMP1(eadc)   ((eadc)->CMP[1] = 0)
 Disable comparator 1. More...
 
#define EADC_DISABLE_CMP2(eadc)   ((eadc)->CMP[2] = 0)
 Disable comparator 2. More...
 
#define EADC_DISABLE_CMP3(eadc)   ((eadc)->CMP[3] = 0)
 Disable comparator 3. More...
 

Functions

void EADC_Open (EADC_T *eadc, uint32_t u32InputMode)
 This function make EADC_module be ready to convert. More...
 
void EADC_Close (EADC_T *eadc)
 Disable EADC_module. More...
 
void EADC_ConfigSampleModule (EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSrc, uint32_t u32Channel)
 Configure the sample control logic module. More...
 
void EADC_SetTriggerDelayTime (EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider)
 Set trigger delay time. More...
 
void EADC_SetInternalSampleTime (EADC_T *eadc, uint32_t u32SampleTime)
 Set ADC internal sample time. More...
 
void EADC_SetExtendSampleTime (EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime)
 Set ADC extend sample time. More...
 

Detailed Description

Macro Definition Documentation

◆ EADC_CLR_INT_FLAG

#define EADC_CLR_INT_FLAG (   eadc,
  u32Mask 
)    ((eadc)->STATUS2 = (u32Mask))

Clear the selected interrupt status bits.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32MaskThe combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status. Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3.
Returns
None

This macro is used to clear clear the selected interrupt status bits.

Definition at line 321 of file eadc.h.

◆ EADC_CLR_SAMPLE_MODULE_OV_FLAG

#define EADC_CLR_SAMPLE_MODULE_OV_FLAG (   eadc,
  u32ModuleMask 
)    ((eadc)->OVSTS = (u32ModuleMask))

Clear the selected sample module overrun status bits.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32ModuleMaskThe combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status. Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 18 is SPOVF18.
Returns
None

This macro is used to clear the selected sample module overrun status bits.

Definition at line 331 of file eadc.h.

◆ EADC_CONV_RESET

#define EADC_CONV_RESET (   eadc)    ((eadc)->CTL |= EADC_CTL_ADRST_Msk)

A/D Converter Control Circuits Reset.

Parameters
[in]eadcThe pointer of the specified EADC module.
Returns
None

ADCRST bit (EADC_CT[1]) remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0.

Definition at line 114 of file eadc.h.

◆ EADC_DISABLE_CMP0

#define EADC_DISABLE_CMP0 (   eadc)    ((eadc)->CMP[0] = 0)

Disable comparator 0.

Parameters
[in]eadcThe pointer of the specified EADC module.
Returns
None

This macro is used to disable comparator 0.

Definition at line 518 of file eadc.h.

◆ EADC_DISABLE_CMP1

#define EADC_DISABLE_CMP1 (   eadc)    ((eadc)->CMP[1] = 0)

Disable comparator 1.

Parameters
[in]eadcThe pointer of the specified EADC module.
Returns
None

This macro is used to disable comparator 1.

Definition at line 526 of file eadc.h.

◆ EADC_DISABLE_CMP2

#define EADC_DISABLE_CMP2 (   eadc)    ((eadc)->CMP[2] = 0)

Disable comparator 2.

Parameters
[in]eadcThe pointer of the specified EADC module.
Returns
None

This macro is used to disable comparator 2.

Definition at line 534 of file eadc.h.

◆ EADC_DISABLE_CMP3

#define EADC_DISABLE_CMP3 (   eadc)    ((eadc)->CMP[3] = 0)

Disable comparator 3.

Parameters
[in]eadcThe pointer of the specified EADC module.
Returns
None

This macro is used to disable comparator 3.

Definition at line 542 of file eadc.h.

◆ EADC_DISABLE_CMP_INT

#define EADC_DISABLE_CMP_INT (   eadc,
  u32CMP 
)    ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk)

Disable the compare interrupt.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32CMPSpecifies the compare register, valid value are from 0 to 3.
Returns
None

This macro is used to disable the compare interrupt.

Definition at line 510 of file eadc.h.

◆ EADC_DISABLE_CMP_WINDOW_MODE

#define EADC_DISABLE_CMP_WINDOW_MODE (   eadc,
  u32CMP 
)    ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk)

Disable the compare window mode.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32CMPSpecifies the compare register, valid value are 0 and 2.
Returns
None

ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.

Definition at line 490 of file eadc.h.

◆ EADC_DISABLE_DOUBLE_BUFFER

#define EADC_DISABLE_DOUBLE_BUFFER (   eadc,
  u32ModuleNum 
)    ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk)

Disable double buffer mode.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32ModuleNumDecides the sample module number, valid value are from 0 to 3.
Returns
None

Sample has one sample result register.

Definition at line 151 of file eadc.h.

◆ EADC_DISABLE_INT

#define EADC_DISABLE_INT (   eadc,
  u32Mask 
)    ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos))

Disable the interrupt.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32MaskDecides the combination of interrupt status bits. Each bit corresponds to a interrupt status. This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.
Returns
None

Specific sample module A/D ADINT0 interrupt function Disabled.

Definition at line 190 of file eadc.h.

◆ EADC_DISABLE_INT_POSITION

#define EADC_DISABLE_INT_POSITION (   eadc,
  u32ModuleNum 
)    ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk)

Set ADIFn at A/D start of conversion.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32ModuleNumDecides the sample module number, valid value are from 0 to 15.
Returns
None

The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the end of conversion.

Definition at line 169 of file eadc.h.

◆ EADC_DISABLE_PDMA

#define EADC_DISABLE_PDMA (   eadc)    ((eadc)->CTL &= (~EADC_CTL_PDMAEN_Msk))

Disable PDMA transfer.

Parameters
[in]eadcThe pointer of the specified EADC module.
Returns
None

This macro is used to disable PDMA transfer.

Definition at line 132 of file eadc.h.

◆ EADC_DISABLE_SAMPLE_MODULE_INT

#define EADC_DISABLE_SAMPLE_MODULE_INT (   eadc,
  u32IntSel,
  u32ModuleMask 
)    ((eadc)->INTSRC[(u32IntSel)] &= ~(u32ModuleMask))

Disable the sample module interrupt.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32IntSelDecides which interrupt source will be used, valid value are from 0 to 3.
[in]u32ModuleMaskthe combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF.
Returns
None

There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.

Definition at line 212 of file eadc.h.

◆ EADC_ENABLE_CMP0

#define EADC_ENABLE_CMP0 (   eadc,
  u32ModuleNum,
  u32Condition,
  u16CMPData,
  u32MatchCount 
)
Value:
((eadc)->CMP[0] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
(u32Condition) |\
((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
(((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
#define EADC_CMP_CMPDAT_Pos
Definition: M471M_R1_S.h:845
#define EADC_CMP_CMPSPL_Pos
Definition: M471M_R1_S.h:836
#define EADC_CMP_ADCMPEN_Msk
Definition: M471M_R1_S.h:828
#define EADC_CMP_CMPMCNT_Pos
Definition: M471M_R1_S.h:839

Configure the comparator 0 and enable it.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32ModuleNumspecifies the compare sample module, valid value are from 0 to 18.
[in]u32Conditionspecifies the compare condition. Valid values are:
[in]u16CMPDataspecifies the compare value, valid range are between 0~0xFFF.
[in]u32MatchCountspecifies the match count setting, valid range are between 0~0xF.
Returns
None

For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.

Definition at line 392 of file eadc.h.

◆ EADC_ENABLE_CMP1

#define EADC_ENABLE_CMP1 (   eadc,
  u32ModuleNum,
  u32Condition,
  u16CMPData,
  u32MatchCount 
)
Value:
((eadc)->CMP[1] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
(u32Condition) |\
((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
(((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\

Configure the comparator 1 and enable it.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32ModuleNumspecifies the compare sample module, valid value are from 0 to 18.
[in]u32Conditionspecifies the compare condition. Valid values are:
[in]u16CMPDataspecifies the compare value, valid range are between 0~0xFFF.
[in]u32MatchCountspecifies the match count setting, valid range are between 0~0xF.
Returns
None

For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.

Definition at line 416 of file eadc.h.

◆ EADC_ENABLE_CMP2

#define EADC_ENABLE_CMP2 (   eadc,
  u32ModuleNum,
  u32Condition,
  u16CMPData,
  u32MatchCount 
)
Value:
((eadc)->CMP[2] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
(u32Condition) |\
((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
(((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\

Configure the comparator 2 and enable it.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32ModuleNumspecifies the compare sample module, valid value are from 0 to 18.
[in]u32Conditionspecifies the compare condition. Valid values are:
[in]u16CMPDataspecifies the compare value, valid range are between 0~0xFFF.
[in]u32MatchCountspecifies the match count setting, valid range are between 0~0xF.
Returns
None

For example, ADC_ENABLE_CMP2(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.

Definition at line 440 of file eadc.h.

◆ EADC_ENABLE_CMP3

#define EADC_ENABLE_CMP3 (   eadc,
  u32ModuleNum,
  u32Condition,
  u16CMPData,
  u32MatchCount 
)
Value:
((eadc)->CMP[3] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
(u32Condition) |\
((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
(((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\

Configure the comparator 3 and enable it.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32ModuleNumspecifies the compare sample module, valid value are from 0 to 18.
[in]u32Conditionspecifies the compare condition. Valid values are:
[in]u16CMPDataspecifies the compare value, valid range are between 0~0xFFF.
[in]u32MatchCountspecifies the match count setting, valid range are between 1~0xF.
Returns
None

For example, ADC_ENABLE_CMP3(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.

Definition at line 464 of file eadc.h.

◆ EADC_ENABLE_CMP_INT

#define EADC_ENABLE_CMP_INT (   eadc,
  u32CMP 
)    ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk)

Enable the compare interrupt.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32CMPSpecifies the compare register, valid value are from 0 to 3.
Returns
None

If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, if ADCMPIE is set to 1, a compare interrupt request is generated.

Definition at line 501 of file eadc.h.

◆ EADC_ENABLE_CMP_WINDOW_MODE

#define EADC_ENABLE_CMP_WINDOW_MODE (   eadc,
  u32CMP 
)    ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk)

Enable the compare window mode.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32CMPSpecifies the compare register, valid value are 0 and 2.
Returns
None

ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched.

Definition at line 481 of file eadc.h.

◆ EADC_ENABLE_DOUBLE_BUFFER

#define EADC_ENABLE_DOUBLE_BUFFER (   eadc,
  u32ModuleNum 
)    ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk)

Enable double buffer mode.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32ModuleNumDecides the sample module number, valid value are from 0 to 3.
Returns
None

The ADC controller supports a double buffer mode in sample module 0~3. If user enable DBMEN (EADC_SCTLn[23], n=0~3), the double buffer mode will enable.

Definition at line 142 of file eadc.h.

◆ EADC_ENABLE_INT

#define EADC_ENABLE_INT (   eadc,
  u32Mask 
)    ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos))

Enable the interrupt.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32MaskDecides the combination of interrupt status bits. Each bit corresponds to a interrupt status. This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.
Returns
None

The A/D converter generates a conversion end ADIFn (EADC_STATUS2[n]) upon the end of specific sample module A/D conversion. If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3).

Definition at line 180 of file eadc.h.

◆ EADC_ENABLE_INT_POSITION

#define EADC_ENABLE_INT_POSITION (   eadc,
  u32ModuleNum 
)    ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk)

Set ADIFn at A/D end of conversion.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32ModuleNumDecides the sample module number, valid value are from 0 to 15.
Returns
None

The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the start of conversion.

Definition at line 160 of file eadc.h.

◆ EADC_ENABLE_PDMA

#define EADC_ENABLE_PDMA (   eadc)    ((eadc)->CTL |= EADC_CTL_PDMAEN_Msk)

Enable PDMA transfer.

Parameters
[in]eadcThe pointer of the specified EADC module.
Returns
None

When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, user can enable this bit to generate a PDMA data transfer request.

Note
When set PDMAEN bit (EADC_CTL[11]), user must set ADINTENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt.

Definition at line 124 of file eadc.h.

◆ EADC_ENABLE_SAMPLE_MODULE_INT

#define EADC_ENABLE_SAMPLE_MODULE_INT (   eadc,
  u32IntSel,
  u32ModuleMask 
)    ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask))

Enable the sample module interrupt.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32IntSelDecides which interrupt source will be used, valid value are from 0 to 3.
[in]u32ModuleMaskthe combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFF.
Returns
None

There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.

Definition at line 201 of file eadc.h.

◆ EADC_GET_CONV_DATA

#define EADC_GET_CONV_DATA (   eadc,
  u32ModuleNum 
)    ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk)

Get the conversion data of the user-specified sample module.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32ModuleNumDecides the sample module number, valid value are from 0 to 18.
Returns
Return the conversion data of the user-specified sample module.

This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data.

Definition at line 263 of file eadc.h.

◆ EADC_GET_DATA_OVERRUN_FLAG

#define EADC_GET_DATA_OVERRUN_FLAG (   eadc,
  u32ModuleMask 
)    ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask))

Get the data overrun flag of the user-specified sample module.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32ModuleMaskThe combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF.
Returns
Return the data overrun flag of the user-specified sample module.

This macro is used to read OV bit (EADC_STATUS0[31:16], EADC_STATUS1[18:16]) field to get data overrun status.

Definition at line 272 of file eadc.h.

◆ EADC_GET_DATA_VALID_FLAG

#define EADC_GET_DATA_VALID_FLAG (   eadc,
  u32ModuleMask 
)    ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask))

Get the data valid flag of the user-specified sample module.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32ModuleMaskThe combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF.
Returns
Return the data valid flag of the user-specified sample module.

This macro is used to read VALID bit (EADC_STATUS0[15:0], EADC_STATUS1[1:0]) field to get data overrun status.

Definition at line 281 of file eadc.h.

◆ EADC_GET_DOUBLE_DATA

#define EADC_GET_DOUBLE_DATA (   eadc,
  u32ModuleNum 
)    ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT_RESULT_Msk)

Get the double data of the user-specified sample module.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32ModuleNumDecides the sample module number, valid value are from 0 to 18.
Returns
Return the double data of the user-specified sample module.

This macro is used to read RESULT bit (EADC_DDATn[15:0], n=0~3) field to get conversion data.

Definition at line 290 of file eadc.h.

◆ EADC_GET_INT_FLAG

#define EADC_GET_INT_FLAG (   eadc,
  u32Mask 
)    ((eadc)->STATUS2 & (u32Mask))

Get the user-specified interrupt flags.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32MaskThe combination of interrupt status bits. Each bit corresponds to a interrupt status. Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3.
Returns
Return the user-specified interrupt flags.

This macro is used to get the user-specified interrupt flags.

Definition at line 301 of file eadc.h.

◆ EADC_GET_PENDING_CONV

#define EADC_GET_PENDING_CONV (   eadc)    ((eadc)->PENDSTS)

Get the conversion pending flag.

Parameters
[in]eadcThe pointer of the specified EADC module.
Returns
Return the conversion pending sample module.

This STPFn(EADC_PENDSTS[18:0]) bit remains 1 during pending state, when the respective ADC conversion is end, the STPFn (n=0~18) bit is automatically cleared to 0.

Definition at line 254 of file eadc.h.

◆ EADC_GET_SAMPLE_MODULE_OV_FLAG

#define EADC_GET_SAMPLE_MODULE_OV_FLAG (   eadc,
  u32ModuleMask 
)    ((eadc)->OVSTS & (u32ModuleMask))

Get the user-specified sample module overrun flags.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32ModuleMaskThe combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFF.
Returns
Return the user-specified sample module overrun flags.

This macro is used to get the user-specified sample module overrun flags.

Definition at line 310 of file eadc.h.

◆ EADC_IS_BUSY

#define EADC_IS_BUSY (   eadc)    (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos)

Get the busy state of EADC.

Parameters
[in]eadcThe pointer of the specified EADC module.
Return values
0Idle state.
1Busy state.

This macro is used to read BUSY bit (EADC_STATUS2[23]) to get busy state.

Definition at line 376 of file eadc.h.

◆ EADC_IS_DATA_OV

#define EADC_IS_DATA_OV (   eadc)    (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos)

Check all sample module A/D result data register overrun flags.

Parameters
[in]eadcThe pointer of the specified EADC module.
Return values
0None of sample module data register overrun flag is set to 1.
1Any one of sample module data register overrun flag is set to 1.

The AOV bit (EADC_STATUS2[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.

Definition at line 340 of file eadc.h.

◆ EADC_IS_DATA_VALID

#define EADC_IS_DATA_VALID (   eadc)    (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos)

Check all sample module A/D result data register valid flags.

Parameters
[in]eadcThe pointer of the specified EADC module.
Return values
0None of sample module data register valid flag is set to 1.
1Any one of sample module data register valid flag is set to 1.

The AVALID bit (EADC_STATUS2[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.

Definition at line 349 of file eadc.h.

◆ EADC_IS_INT_FLAG_OV

#define EADC_IS_INT_FLAG_OV (   eadc)    (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos)

Check all A/D interrupt flag overrun bits.

Parameters
[in]eadcThe pointer of the specified EADC module.
Return values
0None of ADINT interrupt flag is overwritten to 1.
1Any one of ADINT interrupt flag is overwritten to 1.

The ADOVIF bit (EADC_STATUS2[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.

Definition at line 367 of file eadc.h.

◆ EADC_IS_SAMPLE_MODULE_OV

#define EADC_IS_SAMPLE_MODULE_OV (   eadc)    (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos)

Check all A/D sample module start of conversion overrun flags.

Parameters
[in]eadcThe pointer of the specified EADC module.
Return values
0None of sample module event overrun flag is set to 1.
1Any one of sample module event overrun flag is set to 1.

The STOVF bit (EADC_STATUS2[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.

Definition at line 358 of file eadc.h.

◆ EADC_SET_DMOF

#define EADC_SET_DMOF (   eadc,
  u32Format 
)    ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format))

Set the input mode output format.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32FormatDecides the output format. Valid values are:
Returns
None

The macro is used to set A/D input mode output format.

Definition at line 223 of file eadc.h.

◆ EADC_START_CONV

#define EADC_START_CONV (   eadc,
  u32ModuleMask 
)    ((eadc)->SWTRG = (u32ModuleMask))

Start the A/D conversion.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32ModuleMaskThe combination of sample module. Each bit corresponds to a sample module. This parameter decides which sample module will be conversion, valid range are between 1~0x7FFFF. Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18.
Returns
None

After write EADC_SWTRG register to start ADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion.

Definition at line 234 of file eadc.h.

◆ EADC_STOP_CONV

#define EADC_STOP_CONV (   eadc,
  u32ModuleMask 
)    ((eadc)->PENDSTS = (u32ModuleMask))

Cancel the conversion for sample module.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32ModuleMaskThe combination of sample module. Each bit corresponds to a sample module. This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFF. Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module18.
Returns
None

If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.

Definition at line 245 of file eadc.h.

Function Documentation

◆ EADC_Close()

void EADC_Close ( EADC_T eadc)

Disable EADC_module.

Parameters
[in]eadcThe pointer of the specified EADC module..
Returns
None

Clear ADCEN bit (EADC_CTL[0]) to disable A/D converter analog circuit power consumption.

Definition at line 46 of file eadc.c.

◆ EADC_ConfigSampleModule()

void EADC_ConfigSampleModule ( EADC_T eadc,
uint32_t  u32ModuleNum,
uint32_t  u32TriggerSrc,
uint32_t  u32Channel 
)

Configure the sample control logic module.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32ModuleNumDecides the sample module number, valid value are from 0 to 15.
[in]u32TriggerSrcDecides the trigger source. Valid values are:
[in]u32ChannelSpecifies the sample module channel, valid value are from 0 to 15.
Returns
None

Each of ADC control logic modules 0~15 which is configurable for ADC converter channel EADC_CH0~15 and trigger source. sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap voltage, temperature sensor, and battery power (VBAT).

Definition at line 83 of file eadc.c.

◆ EADC_Open()

void EADC_Open ( EADC_T eadc,
uint32_t  u32InputMode 
)

This function make EADC_module be ready to convert.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32InputModeDecides the input mode.
Returns
None

This function is used to set analog input mode and enable A/D Converter. Before starting A/D conversion function, ADCEN bit (EADC_CTL[0]) should be set to 1.

Note

Definition at line 33 of file eadc.c.

◆ EADC_SetExtendSampleTime()

void EADC_SetExtendSampleTime ( EADC_T eadc,
uint32_t  u32ModuleNum,
uint32_t  u32ExtendSampleTime 
)

Set ADC extend sample time.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32ModuleNumDecides the sample module number, valid value are from 0 to 18.
[in]u32ExtendSampleTimeDecides the extend sampling time, the range is from 0~255 ADC clock. Valid value are from 0 to 0xFF.
Returns
None

When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, user can extend A/D sampling time after trigger source is coming to get enough sampling time.

Definition at line 142 of file eadc.c.

◆ EADC_SetInternalSampleTime()

void EADC_SetInternalSampleTime ( EADC_T eadc,
uint32_t  u32SampleTime 
)

Set ADC internal sample time.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32SampleTimeDecides the internal sampling time, the range is from 1~8 ADC clock. Valid value are from 1 to 8.
Returns
None

When A/D operation at high ADC clock rate, the sampling time of analog input voltage may not enough if the analog channel has heavy loading to cause fully charge time is longer. User can set SMPTSEL (EADC_CTL[18:16]) to select the sampling cycle in ADC.

Definition at line 125 of file eadc.c.

◆ EADC_SetTriggerDelayTime()

void EADC_SetTriggerDelayTime ( EADC_T eadc,
uint32_t  u32ModuleNum,
uint32_t  u32TriggerDelayTime,
uint32_t  u32DelayClockDivider 
)

Set trigger delay time.

Parameters
[in]eadcThe pointer of the specified EADC module.
[in]u32ModuleNumDecides the sample module number, valid value are from 0 to 15.
[in]u32TriggerDelayTimeDecides the trigger delay time, valid range are between 0~0xFF.
[in]u32DelayClockDividerDecides the trigger delay clock divider. Valid values are:
Returns
None

User can configure the trigger delay time by setting TRGDLYCNT (EADC_SCTLn[15:8], n=0~15) and TRGDLYDIV (EADC_SCTLn[7:6], n=0~15). Trigger delay time = (u32TriggerDelayTime) x Trigger delay clock period.

Definition at line 107 of file eadc.c.