M471M/R1/S BSP V3.01.000
The Board Support Package for M4521
pwm.c
Go to the documentation of this file.
1/**************************************************************************/
8#include "NuMicro.h"
9
34uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)
35{
36 uint32_t u32Src;
37 uint32_t u32PWMClockSrc;
38 uint32_t u32NearestUnitTimeNsec;
39 uint16_t u16Prescale = 1, u16CNR = 0xFFFF;
40
41 if(pwm == PWM0)
42 u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM0SEL_Msk;
43 else//(pwm == PWM1)
44 u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM1SEL_Msk;
45
46 if(u32Src == 0)
47 {
48 //clock source is from PLL clock
49 u32PWMClockSrc = CLK_GetPLLClockFreq();
50 }
51 else
52 {
53 //clock source is from PCLK
55 u32PWMClockSrc = SystemCoreClock;
56 }
57
58 u32PWMClockSrc /= 1000;
59 for(u16Prescale = 1; u16Prescale <= 0x1000; u16Prescale++)
60 {
61 u32NearestUnitTimeNsec = (1000000 * u16Prescale) / u32PWMClockSrc;
62 if(u32NearestUnitTimeNsec < u32UnitTimeNsec)
63 {
64 if(u16Prescale == 0x1000) //limit to the maximum unit time(nano second)
65 break;
66 if(!((1000000 * (u16Prescale + 1) > (u32NearestUnitTimeNsec * u32PWMClockSrc))))
67 break;
68 continue;
69 }
70 break;
71 }
72
73 // convert to real register value
74 // every two channels share a prescaler
75 PWM_SET_PRESCALER(pwm, u32ChannelNum, --u16Prescale);
76
77 // set PWM to down count type(edge aligned)
78 (pwm)->CTL1 = ((pwm)->CTL1 & ~(PWM_CTL1_CNTTYPE0_Msk << (2 * u32ChannelNum))) | (1UL << (2 * u32ChannelNum));
79 // set PWM to auto-reload mode
80 (pwm)->CTL1 &= ~(PWM_CTL1_CNTMODE0_Msk << u32ChannelNum);
81 PWM_SET_CNR(pwm, u32ChannelNum, u16CNR);
82
83 return (u32NearestUnitTimeNsec);
84}
85
98uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
99{
100 uint32_t u32Src;
101 uint32_t u32PWMClockSrc;
102 uint32_t i;
103 uint16_t u16Prescale = 1, u16CNR = 0xFFFF;
104
105 if(pwm == PWM0)
106 u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM0SEL_Msk;
107 else//(pwm == PWM1)
108 u32Src = CLK->CLKSEL2 & CLK_CLKSEL2_PWM1SEL_Msk;
109
110 if(u32Src == 0)
111 {
112 //clock source is from PLL clock
113 u32PWMClockSrc = CLK_GetPLLClockFreq();
114 }
115 else
116 {
117 //clock source is from PCLK
119 u32PWMClockSrc = SystemCoreClock;
120 }
121
122 for(u16Prescale = 1; u16Prescale < 0xFFF; u16Prescale++) //prescale could be 0~0xFFF
123 {
124 i = (u32PWMClockSrc / u32Frequency) / u16Prescale;
125 // If target value is larger than CNR, need to use a larger prescaler
126 if(i > (0x10000))
127 continue;
128
129 u16CNR = i;
130 break;
131 }
132 // Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register
133 i = u32PWMClockSrc / (u16Prescale * u16CNR);
134
135 // convert to real register value
136 // every two channels share a prescaler
137 PWM_SET_PRESCALER(pwm, u32ChannelNum, --u16Prescale);
138 // set PWM to down count type(edge aligned)
139 (pwm)->CTL1 = ((pwm)->CTL1 & ~(PWM_CTL1_CNTTYPE0_Msk << (2 * u32ChannelNum))) | (1UL << (2 * u32ChannelNum));
140 // set PWM to auto-reload mode
141 (pwm)->CTL1 &= ~(PWM_CTL1_CNTMODE0_Msk << u32ChannelNum);
142
143 PWM_SET_CNR(pwm, u32ChannelNum, --u16CNR);
144 if(u32DutyCycle)
145 {
146 PWM_SET_CMR(pwm, u32ChannelNum, u32DutyCycle * (u16CNR + 1) / 100 - 1);
147 (pwm)->WGCTL0 &= ~((PWM_WGCTL0_PRDPCTL0_Msk | PWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum * 2));
148 (pwm)->WGCTL0 |= (PWM_OUTPUT_LOW << (u32ChannelNum * 2 + PWM_WGCTL0_PRDPCTL0_Pos));
149 (pwm)->WGCTL1 &= ~((PWM_WGCTL1_CMPDCTL0_Msk | PWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum * 2));
150 (pwm)->WGCTL1 |= (PWM_OUTPUT_HIGH << (u32ChannelNum * 2 + PWM_WGCTL1_CMPDCTL0_Pos));
151 }
152 else
153 {
154 PWM_SET_CMR(pwm, u32ChannelNum, 0);
155 (pwm)->WGCTL0 &= ~((PWM_WGCTL0_PRDPCTL0_Msk | PWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum * 2));
156 (pwm)->WGCTL0 |= (PWM_OUTPUT_LOW << (u32ChannelNum * 2 + PWM_WGCTL0_ZPCTL0_Pos));
157 (pwm)->WGCTL1 &= ~((PWM_WGCTL1_CMPDCTL0_Msk | PWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum * 2));
158 (pwm)->WGCTL1 |= (PWM_OUTPUT_HIGH << (u32ChannelNum * 2 + PWM_WGCTL1_CMPDCTL0_Pos));
159 }
160
161 return(i);
162}
163
174void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask)
175{
176 (pwm)->CNTEN |= u32ChannelMask;
177}
178
189void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask)
190{
191 uint32_t i;
192 for(i = 0; i < PWM_CHANNEL_NUM; i ++)
193 {
194 if(u32ChannelMask & (1 << i))
195 {
196 (pwm)->PERIOD[i] = 0;
197 }
198 }
199}
200
211void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask)
212{
213 (pwm)->CNTEN &= ~u32ChannelMask;
214}
215
242void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
243{
244 if(u32ChannelNum < 4)
245 {
246 (pwm)->EADCTS0 &= ~((PWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum * 8));
247 (pwm)->EADCTS0 |= ((PWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum * 8));
248 }
249 else
250 {
251 (pwm)->EADCTS1 &= ~((PWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4) * 8));
252 (pwm)->EADCTS1 |= ((PWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4) * 8));
253 }
254}
255
265void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum)
266{
267 if(u32ChannelNum < 4)
268 {
269 (pwm)->EADCTS0 &= ~(PWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum * 8));
270 }
271 else
272 {
273 (pwm)->EADCTS1 &= ~(PWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4) * 8));
274 }
275}
276
287void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
288{
289 (pwm)->STATUS = (PWM_STATUS_ADCTRGF0_Msk << u32ChannelNum);
290}
291
302uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum)
303{
304 return (((pwm)->STATUS & (PWM_STATUS_ADCTRGF0_Msk << u32ChannelNum)) ? 1 : 0);
305}
306
307
331void PWM_EnableFaultBrake(PWM_T *pwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource)
332{
333 uint32_t i;
334 for(i = 0; i < PWM_CHANNEL_NUM; i ++)
335 {
336 if(u32ChannelMask & (1 << i))
337 {
338 if((u32BrakeSource == PWM_FB_EDGE_SYS_CSS) || (u32BrakeSource == PWM_FB_EDGE_SYS_BOD) || \
339 (u32BrakeSource == PWM_FB_EDGE_SYS_COR) || (u32BrakeSource == PWM_FB_LEVEL_SYS_CSS) || \
340 (u32BrakeSource == PWM_FB_LEVEL_SYS_BOD) || (u32BrakeSource == PWM_FB_LEVEL_SYS_COR))
341 {
342 *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= (u32BrakeSource & (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_BRKCTL0_1_SYSLBEN_Msk));
343 (pwm)->FAILBRK |= (u32BrakeSource & 0xF);
344 }
345 else
346 {
347 *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= u32BrakeSource;
348 }
349 }
350
351 if(u32LevelMask & (1 << i))
352 {
353 if(i % 2 == 0)
354 {
355 //set brake action as high level for even channel
356 *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) &= ~PWM_BRKCTL0_1_BRKAEVEN_Msk;
357 *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= ((3UL) << PWM_BRKCTL0_1_BRKAEVEN_Pos);
358 }
359 else
360 {
361 //set brake action as high level for odd channel
362 *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) &= ~PWM_BRKCTL0_1_BRKAODD_Msk;
363 *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= ((3UL) << PWM_BRKCTL0_1_BRKAODD_Pos);
364 }
365 }
366 else
367 {
368 if(i % 2 == 0)
369 {
370 //set brake action as low level for even channel
371 *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) &= ~PWM_BRKCTL0_1_BRKAEVEN_Msk;
372 *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= ((2UL) << PWM_BRKCTL0_1_BRKAEVEN_Pos);
373 }
374 else
375 {
376 //set brake action as low level for odd channel
377 *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) &= ~PWM_BRKCTL0_1_BRKAODD_Msk;
378 *(__IO uint32_t *)(&((pwm)->BRKCTL0_1) + (i >> 1)) |= ((2UL) << PWM_BRKCTL0_1_BRKAODD_Pos);
379 }
380 }
381 }
382
383}
384
395void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask)
396{
397 (pwm)->CAPINEN |= u32ChannelMask;
398 (pwm)->CAPCTL |= u32ChannelMask;
399}
400
411void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask)
412{
413 (pwm)->CAPINEN &= ~u32ChannelMask;
414 (pwm)->CAPCTL &= ~u32ChannelMask;
415}
416
427void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask)
428{
429 (pwm)->POEN |= u32ChannelMask;
430}
431
442void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask)
443{
444 (pwm)->POEN &= ~u32ChannelMask;
445}
446
462void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode)
463{
464 uint32_t u32IsOddCh;
465 u32IsOddCh = u32ChannelNum % 2;
466 (pwm)->PDMACTL = ((pwm)->PDMACTL & ~((PWM_PDMACTL_CHSEL0_1_Msk | PWM_PDMACTL_CAPORD0_1_Msk | PWM_PDMACTL_CAPMOD0_1_Msk) << ((u32ChannelNum >> 1) * 8))) | \
467 (((u32IsOddCh << PWM_PDMACTL_CHSEL0_1_Pos) | (u32RisingFirst << PWM_PDMACTL_CAPORD0_1_Pos) | \
468 u32Mode | PWM_PDMACTL_CHEN0_1_Msk) << ((u32ChannelNum >> 1) * 8));
469}
470
480void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum)
481{
482 (pwm)->PDMACTL &= ~(PWM_PDMACTL_CHEN0_1_Msk << ((u32ChannelNum >> 1) * 8));
483}
484
497void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration)
498{
499 // every two channels share the same setting
500 *(__IO uint32_t *)(&((pwm)->DTCTL0_1) + (u32ChannelNum >> 1)) &= ~PWM_DTCTL0_1_DTCNT_Msk;
501 *(__IO uint32_t *)(&((pwm)->DTCTL0_1) + (u32ChannelNum >> 1)) |= PWM_DTCTL0_1_DTEN_Msk | u32Duration;
502}
503
514void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum)
515{
516 // every two channels shares the same setting
517 *(__IO uint32_t *)(&((pwm)->DTCTL0_1) + (u32ChannelNum >> 1)) &= ~PWM_DTCTL0_1_DTEN_Msk;
518}
519
532void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
533{
534 (pwm)->CAPIEN |= (u32Edge << u32ChannelNum);
535}
536
549void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
550{
551 (pwm)->CAPIEN &= ~(u32Edge << u32ChannelNum);
552}
553
566void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
567{
568 (pwm)->CAPIF = (u32Edge << u32ChannelNum);
569}
570
583uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
584{
585 return (((((pwm)->CAPIF & (PWM_CAPIF_CFLIF0_Msk << u32ChannelNum)) ? 1 : 0) << 1) | \
586 (((pwm)->CAPIF & (PWM_CAPIF_CRLIF0_Msk << u32ChannelNum)) ? 1 : 0));
587}
600void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
601{
602 (pwm)->INTEN0 |= (u32IntDutyType << u32ChannelNum);
603}
604
614void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum)
615{
616 (pwm)->INTEN0 &= ~((PWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | PWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum);
617}
618
628void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
629{
630 (pwm)->INTSTS0 = (PWM_INTSTS0_CMPUIF0_Msk | PWM_INTSTS0_CMPDIF0_Msk) << u32ChannelNum;
631}
632
644uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
645{
646 return ((((pwm)->INTSTS0 & ((PWM_INTSTS0_CMPDIF0_Msk | PWM_INTSTS0_CMPUIF0_Msk) << u32ChannelNum))) ? 1 : 0);
647}
648
660void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource)
661{
662 (pwm)->INTEN1 |= (0x7 << u32BrakeSource);
663}
664
676void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource)
677{
678 (pwm)->INTEN1 &= ~(0x7 << u32BrakeSource);
679}
680
691void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource)
692{
693 (pwm)->INTSTS1 = (0x3f << u32BrakeSource);
694}
695
707uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource)
708{
709 return (((pwm)->INTSTS1 & (0x3f << u32BrakeSource)) ? 1 : 0);
710}
711
722void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
723{
724 (pwm)->INTEN0 |= (PWM_INTEN0_PIEN0_Msk << u32ChannelNum);
725}
726
736void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum)
737{
738 (pwm)->INTEN0 &= ~(PWM_INTEN0_PIEN0_Msk << u32ChannelNum);
739}
740
750void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
751{
752 (pwm)->INTSTS0 = (PWM_INTSTS0_PIF0_Msk << u32ChannelNum);
753}
754
766uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
767{
768 return ((((pwm)->INTSTS0 & (PWM_INTSTS0_PIF0_Msk << u32ChannelNum))) ? 1 : 0);
769}
770
780void PWM_EnableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum)
781{
782 (pwm)->INTEN0 |= (PWM_INTEN0_ZIEN0_Msk << u32ChannelNum);
783}
784
794void PWM_DisableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum)
795{
796 (pwm)->INTEN0 &= ~(PWM_INTEN0_ZIEN0_Msk << u32ChannelNum);
797}
798
808void PWM_ClearZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
809{
810 (pwm)->INTSTS0 = (PWM_INTSTS0_ZIF0_Msk << u32ChannelNum);
811}
812
824uint32_t PWM_GetZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
825{
826 return ((((pwm)->INTSTS0 & (PWM_INTSTS0_ZIF0_Msk << u32ChannelNum))) ? 1 : 0);
827}
828
849void PWM_EnableAcc(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc)
850{
851 (pwm)->IFA = ((pwm)->IFA & ~((PWM_IFA_IFCNT0_1_Msk | PWM_IFA_IFSEL0_1_Msk) << ((u32ChannelNum >> 1) * 8))) | \
852 ((PWM_IFA_IFAEN0_1_Msk | (u32IntAccSrc << PWM_IFA_IFSEL0_1_Pos) | u32IntFlagCnt) << ((u32ChannelNum >> 1) * 8));
853}
854
865void PWM_DisableAcc(PWM_T *pwm, uint32_t u32ChannelNum)
866{
867 (pwm)->IFA = (pwm)->IFA & ~(PWM_IFA_IFAEN0_1_Msk << ((u32ChannelNum >> 1) * 8));
868}
869
880void PWM_EnableAccInt(PWM_T *pwm, uint32_t u32ChannelNum)
881{
882 (pwm)->INTEN0 |= (PWM_INTEN0_IFAIEN0_1_Msk << ((u32ChannelNum >> 1) * 8));
883}
884
895void PWM_DisableAccInt(PWM_T *pwm, uint32_t u32ChannelNum)
896{
897 (pwm)->INTEN0 &= ~(PWM_INTEN0_IFAIEN0_1_Msk << ((u32ChannelNum >> 1) * 8));
898}
899
910void PWM_ClearAccInt(PWM_T *pwm, uint32_t u32ChannelNum)
911{
912 (pwm)->INTSTS0 = (PWM_INTSTS0_IFAIF0_1_Msk << ((u32ChannelNum >> 1) * 8));
913}
914
926uint32_t PWM_GetAccInt(PWM_T *pwm, uint32_t u32ChannelNum)
927{
928 return (((pwm)->INTSTS0 & (PWM_INTSTS0_IFAIF0_1_Msk << ((u32ChannelNum >> 1) * 8))) ? 1 : 0);
929}
930
940void PWM_ClearFTDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
941{
942 (pwm)->FTCI = ((PWM_FTCI_FTCMU0_Msk | PWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1));
943}
944
956uint32_t PWM_GetFTDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
957{
958 return (((pwm)->FTCI & ((PWM_FTCI_FTCMU0_Msk | PWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1))) ? 1 : 0);
959}
960
974void PWM_EnableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
975{
976 (pwm)->CTL0 |= (u32LoadMode << u32ChannelNum);
977}
978
992void PWM_DisableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
993{
994 (pwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum);
995}
996
1016void PWM_ConfigSyncPhase(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase)
1017{
1018 // every two channels shares the same setting
1019 u32ChannelNum >>= 1;
1020 (pwm)->SYNC = (((pwm)->SYNC & ~((PWM_SYNC_SINSRC0_Msk << (u32ChannelNum << 1)) | (PWM_SYNC_PHSDIR0_Msk << u32ChannelNum))) | \
1021 (u32Direction << PWM_SYNC_PHSDIR0_Pos << u32ChannelNum) | (u32SyncSrc << PWM_SYNC_SINSRC0_Pos) << (u32ChannelNum << 1));
1022 *(__IO uint32_t *)(&((pwm)->PHS0_1) + u32ChannelNum) = u32StartPhase;
1023}
1024
1025
1037void PWM_EnableSyncPhase(PWM_T *pwm, uint32_t u32ChannelMask)
1038{
1039 uint32_t i;
1040 for(i = 0; i < PWM_CHANNEL_NUM; i ++)
1041 {
1042 if(u32ChannelMask & (1 << i))
1043 {
1044 (pwm)->SYNC |= (PWM_SYNC_PHSEN0_Msk << (i >> 1));
1045 }
1046 }
1047}
1048
1060void PWM_DisableSyncPhase(PWM_T *pwm, uint32_t u32ChannelMask)
1061{
1062 uint32_t i;
1063 for(i = 0; i < PWM_CHANNEL_NUM; i ++)
1064 {
1065 if(u32ChannelMask & (1 << i))
1066 {
1067 (pwm)->SYNC &= ~(PWM_SYNC_PHSEN0_Msk << (i >> 1));
1068 }
1069 }
1070}
1071
1091void PWM_EnableSyncNoiseFilter(PWM_T *pwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel)
1092{
1093 (pwm)->SYNC = ((pwm)->SYNC & ~(PWM_SYNC_SFLTCNT_Msk | PWM_SYNC_SFLTCSEL_Msk)) | \
1094 ((u32ClkCnt << PWM_SYNC_SFLTCNT_Pos) | (u32ClkDivSel << PWM_SYNC_SFLTCSEL_Pos) | PWM_SYNC_SNFLTEN_Msk);
1095}
1096
1106{
1107 (pwm)->SYNC &= ~PWM_SYNC_SNFLTEN_Msk;
1108}
1109
1119{
1120 (pwm)->SYNC |= PWM_SYNC_SINPINV_Msk;
1121}
1122
1132{
1133 (pwm)->SYNC &= ~PWM_SYNC_SINPINV_Msk;
1134}
1135
1152void PWM_SetClockSource(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel)
1153{
1154 (pwm)->CLKSRC = (pwm)->CLKSRC & ~(PWM_CLKSRC_ECLKSRC0_Msk << ((u32ChannelNum >> 1) * PWM_CLKSRC_ECLKSRC2_Pos)) | \
1155 (u32ClkSrcSel << ((u32ChannelNum >> 1) * PWM_CLKSRC_ECLKSRC2_Pos));
1156}
1157
1177void PWM_EnableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel)
1178{
1179 (pwm)->BNF = ((pwm)->BNF & ~((PWM_BNF_BRK0FCNT_Msk | PWM_BNF_BRK0NFSEL_Msk) << (u32BrakePinNum * PWM_BNF_BRK1NFEN_Pos))) | \
1180 (((u32ClkCnt << PWM_BNF_BRK0FCNT_Pos) | (u32ClkDivSel << PWM_BNF_BRK0NFSEL_Pos) | PWM_BNF_BRK0NFEN_Msk) << (u32BrakePinNum * PWM_BNF_BRK1NFEN_Pos));
1181}
1182
1192void PWM_DisableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum)
1193{
1194 (pwm)->BNF &= ~(PWM_BNF_BRK0NFEN_Msk << (u32BrakePinNum * PWM_BNF_BRK1NFEN_Pos));
1195}
1196
1206void PWM_EnableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum)
1207{
1208 (pwm)->BNF |= (PWM_BNF_BRK0PINV_Msk << (u32BrakePinNum * PWM_BNF_BRK1NFEN_Pos));
1209}
1210
1220void PWM_DisableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum)
1221{
1222 (pwm)->BNF &= ~(PWM_BNF_BRK0PINV_Msk << (u32BrakePinNum * PWM_BNF_BRK1NFEN_Pos));
1223}
1224
1235void PWM_SetBrakePinSource(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule)
1236{
1237 (pwm)->BNF = ((pwm)->BNF & ~(PWM_BNF_BK0SRC_Msk << (u32BrakePinNum * 8))) | (u32SelAnotherModule << (PWM_BNF_BK0SRC_Pos + u32BrakePinNum * 8));
1238}
1239
1251uint32_t PWM_GetWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum)
1252{
1253 return (((pwm)->STATUS & (PWM_STATUS_CNTMAXF0_Msk << u32ChannelNum)) ? 1 : 0);
1254}
1255
1265void PWM_ClearWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum)
1266{
1267 (pwm)->STATUS = (PWM_STATUS_CNTMAXF0_Msk << u32ChannelNum);
1268}
1269
1270 /* end of group PWM_EXPORTED_FUNCTIONS */
1272 /* end of group PWM_Driver */
1274 /* end of group Standard_Driver */
1276
#define PWM_INTEN0_PIEN0_Msk
Definition: M471M_R1_S.h:6556
#define PWM_INTEN0_ZIEN0_Msk
Definition: M471M_R1_S.h:6532
#define PWM_CLKSRC_ECLKSRC0_Msk
Definition: M471M_R1_S.h:6097
#define PWM_SYNC_PHSEN0_Msk
Definition: M471M_R1_S.h:6040
#define PWM_BRKCTL0_1_BRKAODD_Pos
Definition: M471M_R1_S.h:6411
#define PWM_PDMACTL_CAPORD0_1_Pos
Definition: M471M_R1_S.h:7149
#define PWM_WGCTL1_CMPDCTL0_Msk
Definition: M471M_R1_S.h:6292
#define PWM_SYNC_SINPINV_Msk
Definition: M471M_R1_S.h:6070
#define PWM_INTSTS0_CMPDIF0_Msk
Definition: M471M_R1_S.h:6715
#define PWM_BNF_BRK0NFEN_Msk
Definition: M471M_R1_S.h:6352
#define PWM_BRKCTL0_1_BRKAEVEN_Pos
Definition: M471M_R1_S.h:6408
#define PWM_INTSTS0_ZIF0_Msk
Definition: M471M_R1_S.h:6643
#define PWM_SYNC_SFLTCNT_Msk
Definition: M471M_R1_S.h:6067
#define PWM_BNF_BRK0NFSEL_Msk
Definition: M471M_R1_S.h:6355
#define PWM_INTSTS0_CMPUIF0_Msk
Definition: M471M_R1_S.h:6691
#define PWM_SYNC_SFLTCSEL_Pos
Definition: M471M_R1_S.h:6063
#define PWM_SYNC_SINSRC0_Pos
Definition: M471M_R1_S.h:6051
#define PWM_WGCTL0_ZPCTL0_Pos
Definition: M471M_R1_S.h:6228
#define PWM_IFA_IFSEL0_1_Msk
Definition: M471M_R1_S.h:6814
#define PWM_INTSTS0_IFAIF0_1_Msk
Definition: M471M_R1_S.h:6661
#define PWM_BNF_BK0SRC_Pos
Definition: M471M_R1_S.h:6375
#define PWM_CAPIF_CRLIF0_Msk
Definition: M471M_R1_S.h:7234
#define PWM_SYNC_PHSDIR0_Pos
Definition: M471M_R1_S.h:6075
#define PWM_WGCTL1_CMPUCTL0_Msk
Definition: M471M_R1_S.h:6271
#define PWM_BNF_BRK0FCNT_Pos
Definition: M471M_R1_S.h:6357
#define PWM_PDMACTL_CHSEL0_1_Pos
Definition: M471M_R1_S.h:7152
#define PWM_WGCTL0_ZPCTL0_Msk
Definition: M471M_R1_S.h:6229
#define PWM_SYNC_SFLTCSEL_Msk
Definition: M471M_R1_S.h:6064
#define PWM_PDMACTL_CAPORD0_1_Msk
Definition: M471M_R1_S.h:7150
#define PWM_STATUS_ADCTRGF0_Msk
Definition: M471M_R1_S.h:6943
#define PWM_SYNC_SFLTCNT_Pos
Definition: M471M_R1_S.h:6066
#define PWM_SYNC_SINSRC0_Msk
Definition: M471M_R1_S.h:6052
#define PWM_FTCI_FTCMD0_Msk
Definition: M471M_R1_S.h:7303
#define PWM_SYNC_PHSDIR0_Msk
Definition: M471M_R1_S.h:6076
#define PWM_PDMACTL_CHSEL0_1_Msk
Definition: M471M_R1_S.h:7153
#define PWM_CLKSRC_ECLKSRC2_Pos
Definition: M471M_R1_S.h:6099
#define PWM_FTCI_FTCMU0_Msk
Definition: M471M_R1_S.h:7291
#define PWM_BNF_BRK1NFEN_Pos
Definition: M471M_R1_S.h:6363
#define PWM_BRKCTL0_1_SYSEBEN_Msk
Definition: M471M_R1_S.h:6397
#define PWM_BNF_BRK0NFSEL_Pos
Definition: M471M_R1_S.h:6354
#define PWM_CAPIF_CFLIF0_Msk
Definition: M471M_R1_S.h:7255
#define PWM_CTL1_CNTTYPE0_Msk
Definition: M471M_R1_S.h:5986
#define PWM_EADCTS1_TRGEN4_Msk
Definition: M471M_R1_S.h:6865
#define PWM_WGCTL1_CMPDCTL0_Pos
Definition: M471M_R1_S.h:6291
#define PWM_IFA_IFAEN0_1_Msk
Definition: M471M_R1_S.h:6817
#define PWM_PDMACTL_CHEN0_1_Msk
Definition: M471M_R1_S.h:7144
#define PWM_EADCTS0_TRGSEL0_Msk
Definition: M471M_R1_S.h:6838
#define PWM_WGCTL0_PRDPCTL0_Msk
Definition: M471M_R1_S.h:6250
#define PWM_BRKCTL0_1_BRKAODD_Msk
Definition: M471M_R1_S.h:6412
#define PWM_CTL1_CNTMODE0_Msk
Definition: M471M_R1_S.h:6007
#define PWM_INTSTS0_PIF0_Msk
Definition: M471M_R1_S.h:6667
#define PWM_EADCTS1_TRGSEL4_Msk
Definition: M471M_R1_S.h:6862
#define PWM_BRKCTL0_1_BRKAEVEN_Msk
Definition: M471M_R1_S.h:6409
#define PWM_PDMACTL_CAPMOD0_1_Msk
Definition: M471M_R1_S.h:7147
#define PWM_WGCTL0_PRDPCTL0_Pos
Definition: M471M_R1_S.h:6249
#define PWM_BRKCTL0_1_SYSLBEN_Msk
Definition: M471M_R1_S.h:6406
#define PWM_BNF_BRK0FCNT_Msk
Definition: M471M_R1_S.h:6358
#define PWM_BNF_BK0SRC_Msk
Definition: M471M_R1_S.h:6376
#define PWM_DTCTL0_1_DTEN_Msk
Definition: M471M_R1_S.h:6187
#define PWM_BNF_BRK0PINV_Msk
Definition: M471M_R1_S.h:6361
#define PWM_INTEN0_IFAIEN0_1_Msk
Definition: M471M_R1_S.h:6550
#define PWM_IFA_IFCNT0_1_Msk
Definition: M471M_R1_S.h:6811
#define PWM_STATUS_CNTMAXF0_Msk
Definition: M471M_R1_S.h:6910
#define PWM_IFA_IFSEL0_1_Pos
Definition: M471M_R1_S.h:6813
#define PWM_SYNC_SNFLTEN_Msk
Definition: M471M_R1_S.h:6061
#define PWM_EADCTS0_TRGEN0_Msk
Definition: M471M_R1_S.h:6841
NuMicro peripheral access layer header file.
__STATIC_INLINE uint32_t CLK_GetPLLClockFreq(void)
Get PLL clock frequency.
Definition: clk.h:326
#define CLK_CLKSEL2_PWM0SEL_Msk
Definition: M471M_R1_S.h:1601
#define CLK_CLKSEL2_PWM1SEL_Msk
Definition: M471M_R1_S.h:1604
#define PWM_DUTY_INT_UP_COUNT_MATCH_CMP
Definition: pwm.h:109
#define PWM_OUTPUT_HIGH
Definition: pwm.h:54
#define PWM_FB_LEVEL_SYS_COR
Definition: pwm.h:90
#define PWM_FB_LEVEL_SYS_CSS
Definition: pwm.h:88
#define PWM_FB_EDGE_SYS_COR
Definition: pwm.h:84
#define PWM_DUTY_INT_DOWN_COUNT_MATCH_CMP
Definition: pwm.h:108
#define PWM_FB_EDGE_SYS_BOD
Definition: pwm.h:83
#define PWM_CHANNEL_NUM
Definition: pwm.h:28
#define PWM_FB_EDGE_SYS_CSS
Definition: pwm.h:82
#define PWM_FB_LEVEL_SYS_BOD
Definition: pwm.h:89
#define PWM_OUTPUT_LOW
Definition: pwm.h:53
void PWM_ClearZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
Clear zero interrupt of selected channel.
Definition: pwm.c:808
void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask)
Stop PWM generation immediately by clear channel enable bit.
Definition: pwm.c:211
void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask)
Stop PWM module.
Definition: pwm.c:189
void PWM_EnableSyncPhase(PWM_T *pwm, uint32_t u32ChannelMask)
Enable SYNC phase of selected channel(s)
Definition: pwm.c:1037
void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask)
Enable capture of selected channel(s)
Definition: pwm.c:395
void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode)
Enables PDMA transfer of selected channel for PWM capture.
Definition: pwm.c:462
void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration)
Enable Dead zone of selected channel.
Definition: pwm.c:497
void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
Clear capture interrupt of selected channel.
Definition: pwm.c:566
void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
Clear selected channel trigger EADC flag.
Definition: pwm.c:287
void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum)
Disable selected channel to trigger EADC.
Definition: pwm.c:265
uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)
Configure PWM capture and get the nearest unit time.
Definition: pwm.c:34
void PWM_EnableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel)
Enable PWM brake noise filter function.
Definition: pwm.c:1177
void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum)
Disable period interrupt of selected channel.
Definition: pwm.c:736
void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
Enable duty interrupt of selected channel.
Definition: pwm.c:600
uint32_t PWM_GetAccInt(PWM_T *pwm, uint32_t u32ChannelNum)
Get interrupt flag accumulator interrupt of selected channel.
Definition: pwm.c:926
uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource)
This function get fault brake interrupt flag of selected source.
Definition: pwm.c:707
uint32_t PWM_GetFTDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
Get free trigger duty interrupt flag of selected channel.
Definition: pwm.c:956
void PWM_ClearFTDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
Clear free trigger duty interrupt flag of selected channel.
Definition: pwm.c:940
void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
Disable capture interrupt of selected channel.
Definition: pwm.c:549
void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource)
This function disable fault brake interrupt.
Definition: pwm.c:676
uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
This function Configure PWM generator and get the nearest frequency in edge aligned auto-reload mode.
Definition: pwm.c:98
void PWM_DisableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
Disable load mode of selected channel.
Definition: pwm.c:992
void PWM_ConfigSyncPhase(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase)
Configure synchronization phase of selected channel.
Definition: pwm.c:1016
void PWM_DisableSyncNoiseFilter(PWM_T *pwm)
Disable PWM SYNC_IN noise filter function.
Definition: pwm.c:1105
void PWM_DisableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum)
Disable PWM brake noise filter function.
Definition: pwm.c:1192
void PWM_SetClockSource(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel)
Set PWM clock source.
Definition: pwm.c:1152
uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum)
Get selected channel trigger EADC flag.
Definition: pwm.c:302
void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask)
Disable capture of selected channel(s)
Definition: pwm.c:411
void PWM_ClearWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum)
Clear the time-base counter reached its maximum value flag of selected channel.
Definition: pwm.c:1265
uint32_t PWM_GetZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
Get zero interrupt of selected channel.
Definition: pwm.c:824
void PWM_EnableAcc(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc)
Enable interrupt flag accumulator of selected channel.
Definition: pwm.c:849
#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR)
This macro set the comparator of the selected channel.
Definition: pwm.h:305
void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum)
Disable duty interrupt of selected channel.
Definition: pwm.c:614
void PWM_EnableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum)
Enable PWM brake pin inverse function.
Definition: pwm.c:1206
void PWM_EnableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
Enable load mode of selected channel.
Definition: pwm.c:974
void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
Clear duty interrupt flag of selected channel.
Definition: pwm.c:628
#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR)
This macro set the period of the selected channel.
Definition: pwm.h:330
void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
Enable period interrupt of selected channel.
Definition: pwm.c:722
void PWM_EnableFaultBrake(PWM_T *pwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource)
This function enable fault brake of selected channel(s)
Definition: pwm.c:331
uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
Get duty interrupt flag of selected channel.
Definition: pwm.c:644
void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum)
Disable Dead zone of selected channel.
Definition: pwm.c:514
void PWM_ClearAccInt(PWM_T *pwm, uint32_t u32ChannelNum)
Clear interrupt flag accumulator interrupt of selected channel.
Definition: pwm.c:910
uint32_t PWM_GetWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum)
Get the time-base counter reached its maximum value flag of selected channel.
Definition: pwm.c:1251
void PWM_EnableAccInt(PWM_T *pwm, uint32_t u32ChannelNum)
Enable interrupt flag accumulator interrupt of selected channel.
Definition: pwm.c:880
void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask)
Disables PWM output generation of selected channel(s)
Definition: pwm.c:442
void PWM_SetBrakePinSource(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule)
Set PWM brake pin source.
Definition: pwm.c:1235
void PWM_DisableAcc(PWM_T *pwm, uint32_t u32ChannelNum)
Disable interrupt flag accumulator of selected channel.
Definition: pwm.c:865
void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource)
This function clear fault brake interrupt of selected source.
Definition: pwm.c:691
void PWM_EnableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum)
Enable zero interrupt of selected channel.
Definition: pwm.c:780
#define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler)
This macro set the prescaler of the selected channel.
Definition: pwm.h:293
void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum)
Disables PDMA transfer of selected channel for PWM capture.
Definition: pwm.c:480
void PWM_DisableSyncPinInverse(PWM_T *pwm)
Disable PWM SYNC input pin inverse function.
Definition: pwm.c:1131
void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask)
Start PWM module.
Definition: pwm.c:174
void PWM_DisableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum)
Disable zero interrupt of selected channel.
Definition: pwm.c:794
void PWM_DisableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum)
Disable PWM brake pin inverse function.
Definition: pwm.c:1220
void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
Clear period interrupt of selected channel.
Definition: pwm.c:750
void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask)
Enables PWM output generation of selected channel(s)
Definition: pwm.c:427
void PWM_DisableSyncPhase(PWM_T *pwm, uint32_t u32ChannelMask)
Disable SYNC phase of selected channel(s)
Definition: pwm.c:1060
void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource)
This function enable fault brake interrupt.
Definition: pwm.c:660
void PWM_EnableSyncPinInverse(PWM_T *pwm)
Enable PWM SYNC input pin inverse function.
Definition: pwm.c:1118
void PWM_DisableAccInt(PWM_T *pwm, uint32_t u32ChannelNum)
Disable interrupt flag accumulator interrupt of selected channel.
Definition: pwm.c:895
uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
Get capture interrupt of selected channel.
Definition: pwm.c:583
uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum)
Get period interrupt of selected channel.
Definition: pwm.c:766
void PWM_EnableSyncNoiseFilter(PWM_T *pwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel)
Enable PWM SYNC_IN noise filter function.
Definition: pwm.c:1091
void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge)
Enable capture interrupt of selected channel.
Definition: pwm.c:532
void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
Enable selected channel to trigger EADC.
Definition: pwm.c:242
#define CLK
Definition: M471M_R1_S.h:13818
#define PWM0
Definition: M471M_R1_S.h:13842
uint32_t SystemCoreClock
void SystemCoreClockUpdate(void)
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.