51void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel)
53 volatile uint32_t *pu32EBICTL = (uint32_t *)((uint32_t)&
EBI->CTL0 + (u32Bank * 0x10));
54 volatile uint32_t *pu32EBITCTL = (uint32_t *)((uint32_t)&
EBI->TCTL0 + (u32Bank * 0x10));
57 *pu32EBICTL &= ~EBI_CTL0_DW16_Msk;
61 switch(u32TimingClass)
75 *pu32EBITCTL = 0x03003318;
90 *pu32EBITCTL = 0x03003318;
98 *pu32EBITCTL = 0x07007738;
106 *pu32EBITCTL = 0x07007738;
114 *pu32EBITCTL = 0x07007738;
118 *pu32EBICTL &= ~EBI_CTL0_EN_Msk;
136 volatile uint32_t *pu32EBICTL = (uint32_t *)((uint32_t)&
EBI->CTL0 + (u32Bank * 0x10));
138 *pu32EBICTL &= ~EBI_CTL0_EN_Msk;
162 volatile uint32_t *pu32EBICTL = (uint32_t *)((uint32_t)&
EBI->CTL0 + (u32Bank * 0x10));
163 volatile uint32_t *pu32EBITCTL = (uint32_t *)((uint32_t)&
EBI->TCTL0 + (u32Bank * 0x10));
166 *pu32EBITCTL = u32TimingConfig;
#define EBI_CTL0_TALE_Msk
#define EBI_CTL0_CSPOLINV_Pos
#define EBI_CTL0_TALE_Pos
#define EBI_CTL0_MCLKDIV_Msk
#define EBI_CTL0_DW16_Msk
#define EBI_CTL0_MCLKDIV_Pos
NuMicro peripheral access layer header file.
#define EBI_TIMING_VERYFAST
#define EBI_TIMING_FASTEST
#define EBI_BUSWIDTH_8BIT
#define EBI_TIMING_VERYSLOW
#define EBI_TIMING_NORMAL
#define EBI_TIMING_SLOWEST
void EBI_Close(uint32_t u32Bank)
Disable EBI on specify Bank.
void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel)
Initialize EBI for specify Bank.
void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv)
Set EBI Bus Timing for specify Bank.