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M4521_BSP V3.02.000
The Board Support Package for M4521
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M4521_BSP V3.02.000
The Board Support Package for M4521
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Modules | |
| CLK Exported Functions | |
Variables | |
| int32_t | g_CLK_i32ErrCode |
| #define CLK_CLKDIV0_EADC | ( | x | ) | (((x)-1) << CLK_CLKDIV0_EADCDIV_Pos) |
| #define CLK_CLKDIV0_HCLK | ( | x | ) | (((x)-1) << CLK_CLKDIV0_HCLKDIV_Pos) |
| #define CLK_CLKDIV0_UART | ( | x | ) | (((x)-1) << CLK_CLKDIV0_UARTDIV_Pos) |
| #define CLK_CLKDIV0_USB | ( | x | ) | (((x)-1) << CLK_CLKDIV0_USBDIV_Pos) |
| #define CLK_CLKDIV1_SC0 | ( | x | ) | (((x)-1) << CLK_CLKDIV1_SC0DIV_Pos) |
| #define CLK_CLKSEL0_HCLKSEL_HIRC (0x07UL<<CLK_CLKSEL0_HCLKSEL_Pos) |
| #define CLK_CLKSEL0_HCLKSEL_HXT (0x00UL<<CLK_CLKSEL0_HCLKSEL_Pos) |
| #define CLK_CLKSEL0_HCLKSEL_LIRC (0x03UL<<CLK_CLKSEL0_HCLKSEL_Pos) |
| #define CLK_CLKSEL0_HCLKSEL_LXT (0x01UL<<CLK_CLKSEL0_HCLKSEL_Pos) |
| #define CLK_CLKSEL0_HCLKSEL_PLL (0x02UL<<CLK_CLKSEL0_HCLKSEL_Pos) |
| #define CLK_CLKSEL0_PCLK0SEL_HCLK (0x00UL<<CLK_CLKSEL0_PCLK0SEL_Pos) |
| #define CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2 (0x01UL<<CLK_CLKSEL0_PCLK0SEL_Pos) |
| #define CLK_CLKSEL0_PCLK1SEL_HCLK (0x00UL<<CLK_CLKSEL0_PCLK1SEL_Pos) |
| #define CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2 (0x01UL<<CLK_CLKSEL0_PCLK1SEL_Pos) |
| #define CLK_CLKSEL0_STCLKSEL_HCLK (0x01UL<<SysTick_CTRL_CLKSOURCE_Pos) |
| #define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 (0x03UL<<CLK_CLKSEL0_STCLKSEL_Pos) |
| #define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 (0x07UL<<CLK_CLKSEL0_STCLKSEL_Pos) |
| #define CLK_CLKSEL0_STCLKSEL_HXT (0x00UL<<CLK_CLKSEL0_STCLKSEL_Pos) |
| #define CLK_CLKSEL0_STCLKSEL_HXT_DIV2 (0x02UL<<CLK_CLKSEL0_STCLKSEL_Pos) |
| #define CLK_CLKSEL0_STCLKSEL_LXT (0x01UL<<CLK_CLKSEL0_STCLKSEL_Pos) |
| #define CLK_CLKSEL1_CLKOSEL_HCLK (0x2UL<<CLK_CLKSEL1_CLKOSEL_Pos) |
| #define CLK_CLKSEL1_CLKOSEL_HIRC (0x3UL<<CLK_CLKSEL1_CLKOSEL_Pos) |
| #define CLK_CLKSEL1_CLKOSEL_HXT (0x0UL<<CLK_CLKSEL1_CLKOSEL_Pos) |
| #define CLK_CLKSEL1_CLKOSEL_LXT (0x1UL<<CLK_CLKSEL1_CLKOSEL_Pos) |
| #define CLK_CLKSEL1_TMR0SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR0SEL_Pos) |
| #define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR0SEL_Pos) |
| #define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR0SEL_Pos) |
| #define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR0SEL_Pos) |
| #define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR0SEL_Pos) |
| #define CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL<<CLK_CLKSEL1_TMR0SEL_Pos) |
| #define CLK_CLKSEL1_TMR1SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR1SEL_Pos) |
| #define CLK_CLKSEL1_TMR1SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR1SEL_Pos) |
| #define CLK_CLKSEL1_TMR1SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR1SEL_Pos) |
| #define CLK_CLKSEL1_TMR1SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR1SEL_Pos) |
| #define CLK_CLKSEL1_TMR1SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR1SEL_Pos) |
| #define CLK_CLKSEL1_TMR1SEL_PCLK0 (0x2UL<<CLK_CLKSEL1_TMR1SEL_Pos) |
| #define CLK_CLKSEL1_TMR2SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR2SEL_Pos) |
| #define CLK_CLKSEL1_TMR2SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR2SEL_Pos) |
| #define CLK_CLKSEL1_TMR2SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR2SEL_Pos) |
| #define CLK_CLKSEL1_TMR2SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR2SEL_Pos) |
| #define CLK_CLKSEL1_TMR2SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR2SEL_Pos) |
| #define CLK_CLKSEL1_TMR2SEL_PCLK1 (0x2UL<<CLK_CLKSEL1_TMR2SEL_Pos) |
| #define CLK_CLKSEL1_TMR3SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR3SEL_Pos) |
| #define CLK_CLKSEL1_TMR3SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR3SEL_Pos) |
| #define CLK_CLKSEL1_TMR3SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR3SEL_Pos) |
| #define CLK_CLKSEL1_TMR3SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR3SEL_Pos) |
| #define CLK_CLKSEL1_TMR3SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR3SEL_Pos) |
| #define CLK_CLKSEL1_TMR3SEL_PCLK1 (0x2UL<<CLK_CLKSEL1_TMR3SEL_Pos) |
| #define CLK_CLKSEL1_UARTSEL_HIRC (0x3UL<<CLK_CLKSEL1_UARTSEL_Pos) |
| #define CLK_CLKSEL1_UARTSEL_HXT (0x0UL<<CLK_CLKSEL1_UARTSEL_Pos) |
| #define CLK_CLKSEL1_UARTSEL_LXT (0x2UL<<CLK_CLKSEL1_UARTSEL_Pos) |
| #define CLK_CLKSEL1_UARTSEL_PLL (0x1UL<<CLK_CLKSEL1_UARTSEL_Pos) |
| #define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_WDTSEL_Pos) |
| #define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WDTSEL_Pos) |
| #define CLK_CLKSEL1_WDTSEL_LXT (0x1UL<<CLK_CLKSEL1_WDTSEL_Pos) |
| #define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_WWDTSEL_Pos) |
| #define CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WWDTSEL_Pos) |
| #define CLK_CLKSEL2_PWM0SEL_PCLK0 (0x1UL<<CLK_CLKSEL2_PWM0SEL_Pos) |
| #define CLK_CLKSEL2_PWM0SEL_PLL (0x0UL<<CLK_CLKSEL2_PWM0SEL_Pos) |
| #define CLK_CLKSEL2_PWM1SEL_PCLK1 (0x1UL<<CLK_CLKSEL2_PWM1SEL_Pos) |
| #define CLK_CLKSEL2_PWM1SEL_PLL (0x0UL<<CLK_CLKSEL2_PWM1SEL_Pos) |
| #define CLK_CLKSEL2_SPI0SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI0SEL_Pos) |
| #define CLK_CLKSEL2_SPI0SEL_HXT (0x0UL<<CLK_CLKSEL2_SPI0SEL_Pos) |
| #define CLK_CLKSEL2_SPI0SEL_PCLK0 (0x2UL<<CLK_CLKSEL2_SPI0SEL_Pos) |
| #define CLK_CLKSEL2_SPI0SEL_PLL (0x1UL<<CLK_CLKSEL2_SPI0SEL_Pos) |
| #define CLK_CLKSEL2_SPI1SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI1SEL_Pos) |
| #define CLK_CLKSEL2_SPI1SEL_HXT (0x0UL<<CLK_CLKSEL2_SPI1SEL_Pos) |
| #define CLK_CLKSEL2_SPI1SEL_PCLK1 (0x2UL<<CLK_CLKSEL2_SPI1SEL_Pos) |
| #define CLK_CLKSEL2_SPI1SEL_PLL (0x1UL<<CLK_CLKSEL2_SPI1SEL_Pos) |
| #define CLK_CLKSEL3_RTCSEL_LIRC (0x1UL<<CLK_CLKSEL3_RTCSEL_Pos) |
| #define CLK_CLKSEL3_RTCSEL_LXT (0x0UL<<CLK_CLKSEL3_RTCSEL_Pos) |
| #define CLK_CLKSEL3_SC0SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC0SEL_Pos) |
| #define CLK_CLKSEL3_SC0SEL_HXT (0x0UL<<CLK_CLKSEL3_SC0SEL_Pos) |
| #define CLK_CLKSEL3_SC0SEL_PCLK0 (0x2UL<<CLK_CLKSEL3_SC0SEL_Pos) |
| #define CLK_CLKSEL3_SC0SEL_PLL (0x1UL<<CLK_CLKSEL3_SC0SEL_Pos) |
| #define CLK_PLLCTL_144MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 48) | CLK_PLLCTL_NO_2) |
| #define CLK_PLLCTL_72MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 52) | CLK_PLLCTL_NO_4) |
| #define CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 48) | CLK_PLLCTL_NO_4) |
| #define CLK_PLLCTL_NF | ( | x | ) | ((x)-2) |
| #define CLK_PLLCTL_NR | ( | x | ) | (((x)-2)<<9) |
| #define CLK_PLLCTL_PLLSRC_HIRC 0x00080000UL |
| #define CLK_PLLCTL_PLLSRC_HXT 0x00000000UL |
| #define CLKO_MODULE |
CLKO Module
| #define CRC_MODULE |
CRC Module
| #define EADC_MODULE |
EADC Module
| #define EBI_MODULE |
EBI Module
| #define I2C0_MODULE |
I2C0 Module
| #define I2C1_MODULE |
I2C1 Module
| #define ISP_MODULE |
ISP Module
| #define MODULE_APBCLK | ( | x | ) | (((x) >>30) & 0x3) |
| #define MODULE_APBCLK_ENC | ( | x | ) | (((x) & 0x03) << 30) |
| #define MODULE_CLKDIV | ( | x | ) | (((x) >>18) & 0x3) |
| #define MODULE_CLKDIV_ENC | ( | x | ) | (((x) & 0x03) << 18) |
| #define MODULE_CLKDIV_Msk | ( | x | ) | (((x) >>10) & 0xff) |
| #define MODULE_CLKDIV_Msk_ENC | ( | x | ) | (((x) & 0xff) << 10) |
| #define MODULE_CLKDIV_Pos | ( | x | ) | (((x) >>5 ) & 0x1f) |
| #define MODULE_CLKDIV_Pos_ENC | ( | x | ) | (((x) & 0x1f) << 5) |
| #define MODULE_CLKSEL | ( | x | ) | (((x) >>28) & 0x3) |
| #define MODULE_CLKSEL_ENC | ( | x | ) | (((x) & 0x03) << 28) |
| #define MODULE_CLKSEL_Msk | ( | x | ) | (((x) >>25) & 0x7) |
| #define MODULE_CLKSEL_Msk_ENC | ( | x | ) | (((x) & 0x07) << 25) |
| #define MODULE_CLKSEL_Pos | ( | x | ) | (((x) >>20) & 0x1f) |
| #define MODULE_CLKSEL_Pos_ENC | ( | x | ) | (((x) & 0x1f) << 20) |
| #define MODULE_IP_EN_Pos | ( | x | ) | (((x) >>0 ) & 0x1f) |
| #define MODULE_IP_EN_Pos_ENC | ( | x | ) | (((x) & 0x1f) << 0) |
| #define NA MODULE_NoMsk |
| #define PDMA_MODULE |
PDMA Module
| #define PWM0_MODULE |
PWM0 Module
| #define PWM1_MODULE |
PWM1 Module
| #define RTC_MODULE |
RTC Module
| #define SC0_MODULE |
SC0 Module
| #define SPI0_MODULE |
SPI0 Module
| #define SPI1_MODULE |
SPI1 Module
| #define TMR0_MODULE |
TMR0 Module
| #define TMR1_MODULE |
TMR1 Module
| #define TMR2_MODULE |
TMR2 Module
| #define TMR3_MODULE |
TMR3 Module
| #define UART0_MODULE |
UART0 Module
| #define UART1_MODULE |
UART1 Module
| #define UART2_MODULE |
UART2 Module
| #define UART3_MODULE |
UART3 Module
| #define USBD_MODULE |
USBD Module
| #define USBH_MODULE |
USBH Module
| #define WDT_MODULE |
WDT Module
| #define WWDT_MODULE |
WWDT Module
1.9.3