|
| enum | IRQn {
NonMaskableInt_IRQn = -14
,
MemoryManagement_IRQn = -12
,
BusFault_IRQn = -11
,
UsageFault_IRQn = -10
,
SVCall_IRQn = -5
,
DebugMonitor_IRQn = -4
,
PendSV_IRQn = -2
,
SysTick_IRQn = -1
,
BOD_IRQn = 0
,
IRC_IRQn = 1
,
PWRWU_IRQn = 2
,
CKFAIL_IRQn = 4
,
RTC_IRQn = 6
,
TAMPER_IRQn = 7
,
WDT_IRQn = 8
,
WWDT_IRQn = 9
,
EINT0_IRQn = 10
,
EINT1_IRQn = 11
,
EINT2_IRQn = 12
,
EINT3_IRQn = 13
,
EINT4_IRQn = 14
,
EINT5_IRQn = 15
,
GPA_IRQn = 16
,
GPB_IRQn = 17
,
GPC_IRQn = 18
,
GPD_IRQn = 19
,
GPE_IRQn = 20
,
GPF_IRQn = 21
,
SPI0_IRQn = 22
,
SPI1_IRQn = 23
,
BRAKE0_IRQn = 24
,
PWM0P0_IRQn = 25
,
PWM0P1_IRQn = 26
,
PWM0P2_IRQn = 27
,
BRAKE1_IRQn = 28
,
PWM1P0_IRQn = 29
,
PWM1P1_IRQn = 30
,
PWM1P2_IRQn = 31
,
TMR0_IRQn = 32
,
TMR1_IRQn = 33
,
TMR2_IRQn = 34
,
TMR3_IRQn = 35
,
UART0_IRQn = 36
,
UART1_IRQn = 37
,
I2C0_IRQn = 38
,
I2C1_IRQn = 39
,
PDMA_IRQn = 40
,
ADC00_IRQn = 42
,
ADC01_IRQn = 43
,
ADC02_IRQn = 46
,
ADC03_IRQn = 47
,
UART2_IRQn = 48
,
UART3_IRQn = 49
,
USBD_IRQn = 53
,
USBH_IRQn = 54
,
SC0_IRQn = 58
} |
| |
| #define | CLK_PWRCTL_HXTEN_Pos (0) |
| |
| #define | CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) |
| |
| #define | CLK_PWRCTL_LXTEN_Pos (1) |
| |
| #define | CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) |
| |
| #define | CLK_PWRCTL_HIRCEN_Pos (2) |
| |
| #define | CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) |
| |
| #define | CLK_PWRCTL_LIRCEN_Pos (3) |
| |
| #define | CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) |
| |
| #define | CLK_PWRCTL_PDWKDLY_Pos (4) |
| |
| #define | CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) |
| |
| #define | CLK_PWRCTL_PDWKIEN_Pos (5) |
| |
| #define | CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) |
| |
| #define | CLK_PWRCTL_PDWKIF_Pos (6) |
| |
| #define | CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) |
| |
| #define | CLK_PWRCTL_PDEN_Pos (7) |
| |
| #define | CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) |
| |
| #define | CLK_PWRCTL_PDWTCPU_Pos (8) |
| |
| #define | CLK_PWRCTL_PDWTCPU_Msk (0x1ul << CLK_PWRCTL_PDWTCPU_Pos) |
| |
| #define | CLK_PWRCTL_HXTGAIN_Pos (10) |
| |
| #define | CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos) |
| |
| #define | CLK_PWRCTL_HXTSELTYP_Pos (12) |
| |
| #define | CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos) |
| |
| #define | CLK_PWRCTL_HIRC48MEN_Pos (24) |
| |
| #define | CLK_PWRCTL_HIRC48MEN_Msk (0x1ul << CLK_PWRCTL_HIRC48MEN_Pos) |
| |
| #define | CLK_AHBCLK_PDMACKEN_Pos (1) |
| |
| #define | CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos) |
| |
| #define | CLK_AHBCLK_ISPCKEN_Pos (2) |
| |
| #define | CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) |
| |
| #define | CLK_AHBCLK_EBICKEN_Pos (3) |
| |
| #define | CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) |
| |
| #define | CLK_AHBCLK_USBHCKEN_Pos (4) |
| |
| #define | CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos) |
| |
| #define | CLK_AHBCLK_CRCCKEN_Pos (7) |
| |
| #define | CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) |
| |
| #define | CLK_AHBCLK_FMCIDLE_Pos (15) |
| |
| #define | CLK_AHBCLK_FMCIDLE_Msk (0x1ul << CLK_AHBCLK_FMCIDLE_Pos) |
| |
| #define | CLK_APBCLK0_WDTCKEN_Pos (0) |
| |
| #define | CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) |
| |
| #define | CLK_APBCLK0_RTCCKEN_Pos (1) |
| |
| #define | CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) |
| |
| #define | CLK_APBCLK0_TMR0CKEN_Pos (2) |
| |
| #define | CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) |
| |
| #define | CLK_APBCLK0_TMR1CKEN_Pos (3) |
| |
| #define | CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) |
| |
| #define | CLK_APBCLK0_TMR2CKEN_Pos (4) |
| |
| #define | CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) |
| |
| #define | CLK_APBCLK0_TMR3CKEN_Pos (5) |
| |
| #define | CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) |
| |
| #define | CLK_APBCLK0_CLKOCKEN_Pos (6) |
| |
| #define | CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) |
| |
| #define | CLK_APBCLK0_I2C0CKEN_Pos (8) |
| |
| #define | CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) |
| |
| #define | CLK_APBCLK0_I2C1CKEN_Pos (9) |
| |
| #define | CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) |
| |
| #define | CLK_APBCLK0_SPI0CKEN_Pos (12) |
| |
| #define | CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) |
| |
| #define | CLK_APBCLK0_SPI1CKEN_Pos (13) |
| |
| #define | CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) |
| |
| #define | CLK_APBCLK0_UART0CKEN_Pos (16) |
| |
| #define | CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) |
| |
| #define | CLK_APBCLK0_UART1CKEN_Pos (17) |
| |
| #define | CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) |
| |
| #define | CLK_APBCLK0_UART2CKEN_Pos (18) |
| |
| #define | CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) |
| |
| #define | CLK_APBCLK0_UART3CKEN_Pos (19) |
| |
| #define | CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) |
| |
| #define | CLK_APBCLK0_USBDCKEN_Pos (27) |
| |
| #define | CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) |
| |
| #define | CLK_APBCLK0_EADCCKEN_Pos (28) |
| |
| #define | CLK_APBCLK0_EADCCKEN_Msk (0x1ul << CLK_APBCLK0_EADCCKEN_Pos) |
| |
| #define | CLK_APBCLK1_SC0CKEN_Pos (0) |
| |
| #define | CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) |
| |
| #define | CLK_APBCLK1_PWM0CKEN_Pos (16) |
| |
| #define | CLK_APBCLK1_PWM0CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CKEN_Pos) |
| |
| #define | CLK_APBCLK1_PWM1CKEN_Pos (17) |
| |
| #define | CLK_APBCLK1_PWM1CKEN_Msk (0x1ul << CLK_APBCLK1_PWM1CKEN_Pos) |
| |
| #define | CLK_APBCLK1_TKCKEN_Pos (25) |
| |
| #define | CLK_APBCLK1_TKCKEN_Msk (0x1ul << CLK_APBCLK1_TKCKEN_Pos) |
| |
| #define | CLK_CLKSEL0_HCLKSEL_Pos (0) |
| |
| #define | CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) |
| |
| #define | CLK_CLKSEL0_STCLKSEL_Pos (3) |
| |
| #define | CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) |
| |
| #define | CLK_CLKSEL0_PCLK0SEL_Pos (6) |
| |
| #define | CLK_CLKSEL0_PCLK0SEL_Msk (0x1ul << CLK_CLKSEL0_PCLK0SEL_Pos) |
| |
| #define | CLK_CLKSEL0_PCLK1SEL_Pos (7) |
| |
| #define | CLK_CLKSEL0_PCLK1SEL_Msk (0x1ul << CLK_CLKSEL0_PCLK1SEL_Pos) |
| |
| #define | CLK_CLKSEL0_USBCKSEL_Pos (8) |
| |
| #define | CLK_CLKSEL0_USBCKSEL_Msk (0x1ul << CLK_CLKSEL0_USBCKSEL_Pos) |
| |
| #define | CLK_CLKSEL1_WDTSEL_Pos (0) |
| |
| #define | CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) |
| |
| #define | CLK_CLKSEL1_TMR0SEL_Pos (8) |
| |
| #define | CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) |
| |
| #define | CLK_CLKSEL1_TMR1SEL_Pos (12) |
| |
| #define | CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) |
| |
| #define | CLK_CLKSEL1_TMR2SEL_Pos (16) |
| |
| #define | CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) |
| |
| #define | CLK_CLKSEL1_TMR3SEL_Pos (20) |
| |
| #define | CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) |
| |
| #define | CLK_CLKSEL1_UARTSEL_Pos (24) |
| |
| #define | CLK_CLKSEL1_UARTSEL_Msk (0x3ul << CLK_CLKSEL1_UARTSEL_Pos) |
| |
| #define | CLK_CLKSEL1_CLKOSEL_Pos (28) |
| |
| #define | CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos) |
| |
| #define | CLK_CLKSEL1_WWDTSEL_Pos (30) |
| |
| #define | CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) |
| |
| #define | CLK_CLKSEL2_PWM0SEL_Pos (0) |
| |
| #define | CLK_CLKSEL2_PWM0SEL_Msk (0x1ul << CLK_CLKSEL2_PWM0SEL_Pos) |
| |
| #define | CLK_CLKSEL2_PWM1SEL_Pos (1) |
| |
| #define | CLK_CLKSEL2_PWM1SEL_Msk (0x1ul << CLK_CLKSEL2_PWM1SEL_Pos) |
| |
| #define | CLK_CLKSEL2_SPI0SEL_Pos (2) |
| |
| #define | CLK_CLKSEL2_SPI0SEL_Msk (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos) |
| |
| #define | CLK_CLKSEL2_SPI1SEL_Pos (4) |
| |
| #define | CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos) |
| |
| #define | CLK_CLKSEL3_SC0SEL_Pos (0) |
| |
| #define | CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) |
| |
| #define | CLK_CLKSEL3_RTCSEL_Pos (8) |
| |
| #define | CLK_CLKSEL3_RTCSEL_Msk (0x1ul << CLK_CLKSEL3_RTCSEL_Pos) |
| |
| #define | CLK_CLKDIV0_HCLKDIV_Pos (0) |
| |
| #define | CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) |
| |
| #define | CLK_CLKDIV0_USBDIV_Pos (4) |
| |
| #define | CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) |
| |
| #define | CLK_CLKDIV0_UARTDIV_Pos (8) |
| |
| #define | CLK_CLKDIV0_UARTDIV_Msk (0xful << CLK_CLKDIV0_UARTDIV_Pos) |
| |
| #define | CLK_CLKDIV0_EADCDIV_Pos (16) |
| |
| #define | CLK_CLKDIV0_EADCDIV_Msk (0xfful << CLK_CLKDIV0_EADCDIV_Pos) |
| |
| #define | CLK_CLKDIV1_SC0DIV_Pos (0) |
| |
| #define | CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) |
| |
| #define | CLK_PLLCTL_FBDIV_Pos (0) |
| |
| #define | CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) |
| |
| #define | CLK_PLLCTL_INDIV_Pos (9) |
| |
| #define | CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) |
| |
| #define | CLK_PLLCTL_OUTDIV_Pos (14) |
| |
| #define | CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) |
| |
| #define | CLK_PLLCTL_PD_Pos (16) |
| |
| #define | CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) |
| |
| #define | CLK_PLLCTL_BP_Pos (17) |
| |
| #define | CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) |
| |
| #define | CLK_PLLCTL_OE_Pos (18) |
| |
| #define | CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) |
| |
| #define | CLK_PLLCTL_PLLSRC_Pos (19) |
| |
| #define | CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) |
| |
| #define | CLK_PLLCTL_STBSEL_Pos (23) |
| |
| #define | CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) |
| |
| #define | CLK_STATUS_HXTSTB_Pos (0) |
| |
| #define | CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) |
| |
| #define | CLK_STATUS_LXTSTB_Pos (1) |
| |
| #define | CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) |
| |
| #define | CLK_STATUS_PLLSTB_Pos (2) |
| |
| #define | CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) |
| |
| #define | CLK_STATUS_LIRCSTB_Pos (3) |
| |
| #define | CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) |
| |
| #define | CLK_STATUS_HIRCSTB_Pos (4) |
| |
| #define | CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) |
| |
| #define | CLK_STATUS_CLKSFAIL_Pos (7) |
| |
| #define | CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) |
| |
| #define | CLK_CLKOCTL_FREQSEL_Pos (0) |
| |
| #define | CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) |
| |
| #define | CLK_CLKOCTL_CLKOEN_Pos (4) |
| |
| #define | CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) |
| |
| #define | CLK_CLKOCTL_DIV1EN_Pos (5) |
| |
| #define | CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) |
| |
| #define | CLK_CLKOCTL_CLK1HZEN_Pos (6) |
| |
| #define | CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) |
| |
| #define | CLK_CLKDCTL_HXTFDEN_Pos (4) |
| |
| #define | CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) |
| |
| #define | CLK_CLKDCTL_HXTFIEN_Pos (5) |
| |
| #define | CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) |
| |
| #define | CLK_CLKDCTL_LXTFDEN_Pos (12) |
| |
| #define | CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) |
| |
| #define | CLK_CLKDCTL_LXTFIEN_Pos (13) |
| |
| #define | CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) |
| |
| #define | CLK_CLKDCTL_HXTFQDEN_Pos (16) |
| |
| #define | CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) |
| |
| #define | CLK_CLKDCTL_HXTFQIEN_Pos (17) |
| |
| #define | CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) |
| |
| #define | CLK_CLKDSTS_HXTFIF_Pos (0) |
| |
| #define | CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) |
| |
| #define | CLK_CLKDSTS_LXTFIF_Pos (1) |
| |
| #define | CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) |
| |
| #define | CLK_CLKDSTS_HXTFQIF_Pos (8) |
| |
| #define | CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) |
| |
| #define | CLK_CDUPB_UPERBD_Pos (0) |
| |
| #define | CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) |
| |
| #define | CLK_CDLOWB_LOWERBD_Pos (0) |
| |
| #define | CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) |
| |
1.9.3