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M4521_BSP V3.02.000
The Board Support Package for M4521
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| #define EADC_CMP_ADCMPEN_Msk (0x1ul << EADC_CMP_ADCMPEN_Pos) |
EADC_T::CMP: ADCMPEN Mask
| #define EADC_CMP_ADCMPEN_Pos (0) |
EADC_T::CMP: ADCMPEN Position
| #define EADC_CMP_ADCMPIE_Msk (0x1ul << EADC_CMP_ADCMPIE_Pos) |
EADC_T::CMP: ADCMPIE Mask
| #define EADC_CMP_ADCMPIE_Pos (1) |
EADC_T::CMP: ADCMPIE Position
| #define EADC_CMP_CMPCOND_Msk (0x1ul << EADC_CMP_CMPCOND_Pos) |
EADC_T::CMP: CMPCOND Mask
| #define EADC_CMP_CMPCOND_Pos (2) |
EADC_T::CMP: CMPCOND Position
| #define EADC_CMP_CMPDAT_Msk (0xffful << EADC_CMP_CMPDAT_Pos) |
EADC_T::CMP: CMPDAT Mask
| #define EADC_CMP_CMPDAT_Pos (16) |
EADC_T::CMP: CMPDAT Position
| #define EADC_CMP_CMPMCNT_Msk (0xful << EADC_CMP_CMPMCNT_Pos) |
EADC_T::CMP: CMPMCNT Mask
| #define EADC_CMP_CMPMCNT_Pos (8) |
EADC_T::CMP: CMPMCNT Position
| #define EADC_CMP_CMPSPL_Msk (0x1ful << EADC_CMP_CMPSPL_Pos) |
EADC_T::CMP: CMPSPL Mask
| #define EADC_CMP_CMPSPL_Pos (3) |
EADC_T::CMP: CMPSPL Position
| #define EADC_CMP_CMPWEN_Msk (0x1ul << EADC_CMP_CMPWEN_Pos) |
EADC_T::CMP: CMPWEN Mask
| #define EADC_CMP_CMPWEN_Pos (15) |
EADC_T::CMP: CMPWEN Position
| #define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) |
EADC_T::CTL: ADCEN Mask
| #define EADC_CTL_ADCEN_Pos (0) |
EADC_T::CTL: ADCEN Position
| #define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) |
EADC_T::CTL: ADCIEN0 Mask
| #define EADC_CTL_ADCIEN0_Pos (2) |
EADC_T::CTL: ADCIEN0 Position
| #define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) |
EADC_T::CTL: ADCIEN1 Mask
| #define EADC_CTL_ADCIEN1_Pos (3) |
EADC_T::CTL: ADCIEN1 Position
| #define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) |
EADC_T::CTL: ADCIEN2 Mask
| #define EADC_CTL_ADCIEN2_Pos (4) |
EADC_T::CTL: ADCIEN2 Position
| #define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) |
EADC_T::CTL: ADCIEN3 Mask
| #define EADC_CTL_ADCIEN3_Pos (5) |
EADC_T::CTL: ADCIEN3 Position
| #define EADC_CTL_ADRST_Msk (0x1ul << EADC_CTL_ADRST_Pos) |
EADC_T::CTL: ADRST Mask
| #define EADC_CTL_ADRST_Pos (1) |
EADC_T::CTL: ADRST Position
| #define EADC_CTL_DIFFEN_Msk (0x1ul << EADC_CTL_DIFFEN_Pos) |
EADC_T::CTL: DIFFEN Mask
| #define EADC_CTL_DIFFEN_Pos (8) |
EADC_T::CTL: DIFFEN Position
| #define EADC_CTL_DMOF_Msk (0x1ul << EADC_CTL_DMOF_Pos) |
EADC_T::CTL: DMOF Mask
| #define EADC_CTL_DMOF_Pos (9) |
EADC_T::CTL: DMOF Position
| #define EADC_CTL_PDMAEN_Msk (0x1ul << EADC_CTL_PDMAEN_Pos) |
EADC_T::CTL: PDMAEN Mask
| #define EADC_CTL_PDMAEN_Pos (11) |
EADC_T::CTL: PDMAEN Position
| #define EADC_CTL_SMPTSEL_Msk (0x7ul << EADC_CTL_SMPTSEL_Pos) |
EADC_T::CTL: SMPTSEL Mask
| #define EADC_CTL_SMPTSEL_Pos (16) |
EADC_T::CTL: SMPTSEL Position
| #define EADC_CURDAT_CURDAT_Msk (0x3fffful << EADC_CURDAT_CURDAT_Pos) |
EADC_T::CURDAT: CURDAT Mask
| #define EADC_CURDAT_CURDAT_Pos (0) |
EADC_T::CURDAT: CURDAT Position
| #define EADC_DAT_OV_Msk (0x1ul << EADC_DAT_OV_Pos) |
EADC_T::DAT: OV Mask
| #define EADC_DAT_OV_Pos (16) |
EADC_T::DAT: OV Position
| #define EADC_DAT_RESULT_Msk (0xfffful << EADC_DAT_RESULT_Pos) |
EADC_T::DAT: RESULT Mask
| #define EADC_DAT_RESULT_Pos (0) |
@addtogroup EADC_CONST EADC Bit Field Definition Constant Definitions for EADC Controller
EADC_T::DAT: RESULT Position
| #define EADC_DAT_VALID_Msk (0x1ul << EADC_DAT_VALID_Pos) |
EADC_T::DAT: VALID Mask
| #define EADC_DAT_VALID_Pos (17) |
EADC_T::DAT: VALID Position
| #define EADC_DDAT_OV_Msk (0x1ul << EADC_DDAT_OV_Pos) |
EADC_T::DDAT: OV Mask
| #define EADC_DDAT_OV_Pos (16) |
EADC_T::DDAT: OV Position
| #define EADC_DDAT_RESULT_Msk (0xfffful << EADC_DDAT_RESULT_Pos) |
EADC_T::DDAT: RESULT Mask
| #define EADC_DDAT_RESULT_Pos (0) |
EADC_T::DDAT: RESULT Position
| #define EADC_DDAT_VALID_Msk (0x1ul << EADC_DDAT_VALID_Pos) |
EADC_T::DDAT: VALID Mask
| #define EADC_DDAT_VALID_Pos (17) |
EADC_T::DDAT: VALID Position
| #define EADC_INTSRC_SPLIE_Msk (0x7FFFFul << EADC_INTSRC_SPLIE_Pos) |
EADC_T::INTSRC: SPLIE Mask
| #define EADC_INTSRC_SPLIE_Pos (0) |
EADC_T::INTSRC: SPLIE Position
| #define EADC_OVSTS_SPOVF_Msk (0x7fffful << EADC_OVSTS_SPOVF_Pos) |
EADC_T::OVSTS: SPOVF Mask
| #define EADC_OVSTS_SPOVF_Pos (0) |
EADC_T::OVSTS: SPOVF Position
| #define EADC_PENDSTS_STPF_Msk (0x7fffful << EADC_PENDSTS_STPF_Pos) |
EADC_T::PENDSTS: STPF Mask
| #define EADC_PENDSTS_STPF_Pos (0) |
EADC_T::PENDSTS: STPF Position
| #define EADC_SCTL_CHSEL_Msk (0xful << EADC_SCTL_CHSEL_Pos) |
EADC_T::SCTL: CHSEL Mask
| #define EADC_SCTL_CHSEL_Pos (0) |
EADC_T::SCTL: CHSEL Position
| #define EADC_SCTL_DBMEN_Msk (0x1ul << EADC_SCTL_DBMEN_Pos) |
EADC_T::SCTL: DBMEN Mask
| #define EADC_SCTL_DBMEN_Pos (23) |
EADC_T::SCTL: DBMEN Position
| #define EADC_SCTL_EXTFEN_Msk (0x1ul << EADC_SCTL_EXTFEN_Pos) |
EADC_T::SCTL: EXTFEN Mask
| #define EADC_SCTL_EXTFEN_Pos (5) |
EADC_T::SCTL: EXTFEN Position
| #define EADC_SCTL_EXTREN_Msk (0x1ul << EADC_SCTL_EXTREN_Pos) |
EADC_T::SCTL: EXTREN Mask
| #define EADC_SCTL_EXTREN_Pos (4) |
EADC_T::SCTL: EXTREN Position
| #define EADC_SCTL_EXTSMPT_Msk (0xfful << EADC_SCTL_EXTSMPT_Pos) |
EADC_T::SCTL: EXTSMPT Mask
| #define EADC_SCTL_EXTSMPT_Pos (24) |
EADC_T::SCTL: EXTSMPT Position
| #define EADC_SCTL_INTPOS_Msk (0x1ul << EADC_SCTL_INTPOS_Pos) |
EADC_T::SCTL: INTPOS Mask
| #define EADC_SCTL_INTPOS_Pos (22) |
EADC_T::SCTL: INTPOS Position
| #define EADC_SCTL_TRGDLYCNT_Msk (0xfful << EADC_SCTL_TRGDLYCNT_Pos) |
EADC_T::SCTL: TRGDLYCNT Mask
| #define EADC_SCTL_TRGDLYCNT_Pos (8) |
EADC_T::SCTL: TRGDLYCNT Position
| #define EADC_SCTL_TRGDLYDIV_Msk (0x3ul << EADC_SCTL_TRGDLYDIV_Pos) |
EADC_T::SCTL: TRGDLYDIV Mask
| #define EADC_SCTL_TRGDLYDIV_Pos (6) |
EADC_T::SCTL: TRGDLYDIV Position
| #define EADC_SCTL_TRGSEL_Msk (0x1ful << EADC_SCTL_TRGSEL_Pos) |
EADC_T::SCTL: TRGSEL Mask
| #define EADC_SCTL_TRGSEL_Pos (16) |
EADC_T::SCTL: TRGSEL Position
| #define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) |
EADC_T::STATUS0: OV Mask
| #define EADC_STATUS0_OV_Pos (16) |
EADC_T::STATUS0: OV Position
| #define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) |
EADC_T::STATUS0: VALID Mask
| #define EADC_STATUS0_VALID_Pos (0) |
EADC_T::STATUS0: VALID Position
| #define EADC_STATUS1_OV_Msk (0x7ul << EADC_STATUS1_OV_Pos) |
EADC_T::STATUS1: OV Mask
| #define EADC_STATUS1_OV_Pos (16) |
EADC_T::STATUS1: OV Position
| #define EADC_STATUS1_VALID_Msk (0x7ul << EADC_STATUS1_VALID_Pos) |
EADC_T::STATUS1: VALID Mask
| #define EADC_STATUS1_VALID_Pos (0) |
EADC_T::STATUS1: VALID Position
| #define EADC_STATUS2_ADCMPF0_Msk (0x1ul << EADC_STATUS2_ADCMPF0_Pos) |
EADC_T::STATUS2: ADCMPF0 Mask
| #define EADC_STATUS2_ADCMPF0_Pos (4) |
EADC_T::STATUS2: ADCMPF0 Position
| #define EADC_STATUS2_ADCMPF1_Msk (0x1ul << EADC_STATUS2_ADCMPF1_Pos) |
EADC_T::STATUS2: ADCMPF1 Mask
| #define EADC_STATUS2_ADCMPF1_Pos (5) |
EADC_T::STATUS2: ADCMPF1 Position
| #define EADC_STATUS2_ADCMPF2_Msk (0x1ul << EADC_STATUS2_ADCMPF2_Pos) |
EADC_T::STATUS2: ADCMPF2 Mask
| #define EADC_STATUS2_ADCMPF2_Pos (6) |
EADC_T::STATUS2: ADCMPF2 Position
| #define EADC_STATUS2_ADCMPF3_Msk (0x1ul << EADC_STATUS2_ADCMPF3_Pos) |
EADC_T::STATUS2: ADCMPF3 Mask
| #define EADC_STATUS2_ADCMPF3_Pos (7) |
EADC_T::STATUS2: ADCMPF3 Position
| #define EADC_STATUS2_ADCMPO0_Msk (0x1ul << EADC_STATUS2_ADCMPO0_Pos) |
EADC_T::STATUS2: ADCMPO0 Mask
| #define EADC_STATUS2_ADCMPO0_Pos (12) |
EADC_T::STATUS2: ADCMPO0 Position
| #define EADC_STATUS2_ADCMPO1_Msk (0x1ul << EADC_STATUS2_ADCMPO1_Pos) |
EADC_T::STATUS2: ADCMPO1 Mask
| #define EADC_STATUS2_ADCMPO1_Pos (13) |
EADC_T::STATUS2: ADCMPO1 Position
| #define EADC_STATUS2_ADCMPO2_Msk (0x1ul << EADC_STATUS2_ADCMPO2_Pos) |
EADC_T::STATUS2: ADCMPO2 Mask
| #define EADC_STATUS2_ADCMPO2_Pos (14) |
EADC_T::STATUS2: ADCMPO2 Position
| #define EADC_STATUS2_ADCMPO3_Msk (0x1ul << EADC_STATUS2_ADCMPO3_Pos) |
EADC_T::STATUS2: ADCMPO3 Mask
| #define EADC_STATUS2_ADCMPO3_Pos (15) |
EADC_T::STATUS2: ADCMPO3 Position
| #define EADC_STATUS2_ADIF0_Msk (0x1ul << EADC_STATUS2_ADIF0_Pos) |
EADC_T::STATUS2: ADIF0 Mask
| #define EADC_STATUS2_ADIF0_Pos (0) |
EADC_T::STATUS2: ADIF0 Position
| #define EADC_STATUS2_ADIF1_Msk (0x1ul << EADC_STATUS2_ADIF1_Pos) |
EADC_T::STATUS2: ADIF1 Mask
| #define EADC_STATUS2_ADIF1_Pos (1) |
EADC_T::STATUS2: ADIF1 Position
| #define EADC_STATUS2_ADIF2_Msk (0x1ul << EADC_STATUS2_ADIF2_Pos) |
EADC_T::STATUS2: ADIF2 Mask
| #define EADC_STATUS2_ADIF2_Pos (2) |
EADC_T::STATUS2: ADIF2 Position
| #define EADC_STATUS2_ADIF3_Msk (0x1ul << EADC_STATUS2_ADIF3_Pos) |
EADC_T::STATUS2: ADIF3 Mask
| #define EADC_STATUS2_ADIF3_Pos (3) |
EADC_T::STATUS2: ADIF3 Position
| #define EADC_STATUS2_ADOVIF0_Msk (0x1ul << EADC_STATUS2_ADOVIF0_Pos) |
EADC_T::STATUS2: ADOVIF0 Mask
| #define EADC_STATUS2_ADOVIF0_Pos (8) |
EADC_T::STATUS2: ADOVIF0 Position
| #define EADC_STATUS2_ADOVIF1_Msk (0x1ul << EADC_STATUS2_ADOVIF1_Pos) |
EADC_T::STATUS2: ADOVIF1 Mask
| #define EADC_STATUS2_ADOVIF1_Pos (9) |
EADC_T::STATUS2: ADOVIF1 Position
| #define EADC_STATUS2_ADOVIF2_Msk (0x1ul << EADC_STATUS2_ADOVIF2_Pos) |
EADC_T::STATUS2: ADOVIF2 Mask
| #define EADC_STATUS2_ADOVIF2_Pos (10) |
EADC_T::STATUS2: ADOVIF2 Position
| #define EADC_STATUS2_ADOVIF3_Msk (0x1ul << EADC_STATUS2_ADOVIF3_Pos) |
EADC_T::STATUS2: ADOVIF3 Mask
| #define EADC_STATUS2_ADOVIF3_Pos (11) |
EADC_T::STATUS2: ADOVIF3 Position
| #define EADC_STATUS2_ADOVIF_Msk (0x1ul << EADC_STATUS2_ADOVIF_Pos) |
EADC_T::STATUS2: ADOVIF Mask
| #define EADC_STATUS2_ADOVIF_Pos (24) |
EADC_T::STATUS2: ADOVIF Position
| #define EADC_STATUS2_AOV_Msk (0x1ul << EADC_STATUS2_AOV_Pos) |
EADC_T::STATUS2: AOV Mask
| #define EADC_STATUS2_AOV_Pos (27) |
EADC_T::STATUS2: AOV Position
| #define EADC_STATUS2_AVALID_Msk (0x1ul << EADC_STATUS2_AVALID_Pos) |
EADC_T::STATUS2: AVALID Mask
| #define EADC_STATUS2_AVALID_Pos (26) |
EADC_T::STATUS2: AVALID Position
| #define EADC_STATUS2_BUSY_Msk (0x1ul << EADC_STATUS2_BUSY_Pos) |
EADC_T::STATUS2: BUSY Mask
| #define EADC_STATUS2_BUSY_Pos (23) |
EADC_T::STATUS2: BUSY Position
| #define EADC_STATUS2_CHANNEL_Msk (0x1ful << EADC_STATUS2_CHANNEL_Pos) |
EADC_T::STATUS2: CHANNEL Mask
| #define EADC_STATUS2_CHANNEL_Pos (16) |
EADC_T::STATUS2: CHANNEL Position
| #define EADC_STATUS2_STOVF_Msk (0x1ul << EADC_STATUS2_STOVF_Pos) |
EADC_T::STATUS2: STOVF Mask
| #define EADC_STATUS2_STOVF_Pos (25) |
EADC_T::STATUS2: STOVF Position
| #define EADC_STATUS3_CURSPL_Msk (0x1ful << EADC_STATUS3_CURSPL_Pos) |
EADC_T::STATUS3: CURSPL Mask
| #define EADC_STATUS3_CURSPL_Pos (0) |
EADC_T::STATUS3: CURSPL Position
| #define EADC_SWTRG_SWTRG_Msk (0x7fffful << EADC_SWTRG_SWTRG_Pos) |
EADC_T::SWTRG: SWTRG Mask
| #define EADC_SWTRG_SWTRG_Pos (0) |
EADC_T::SWTRG: SWTRG Position