M4521 CLK Header File. More...

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Macros
#define	FREQ_25MHZ 25000000

#define	FREQ_50MHZ 50000000

#define	FREQ_72MHZ 72000000

#define	FREQ_125MHZ 125000000

#define	FREQ_200MHZ 200000000

#define	FREQ_250MHZ 250000000

#define	FREQ_500MHZ 500000000

#define	CLK_CLKSEL0_HCLKSEL_HXT (0x00UL<<CLK_CLKSEL0_HCLKSEL_Pos)

#define	CLK_CLKSEL0_HCLKSEL_LXT (0x01UL<<CLK_CLKSEL0_HCLKSEL_Pos)

#define	CLK_CLKSEL0_HCLKSEL_PLL (0x02UL<<CLK_CLKSEL0_HCLKSEL_Pos)

#define	CLK_CLKSEL0_HCLKSEL_LIRC (0x03UL<<CLK_CLKSEL0_HCLKSEL_Pos)

#define	CLK_CLKSEL0_HCLKSEL_HIRC (0x07UL<<CLK_CLKSEL0_HCLKSEL_Pos)

#define	CLK_CLKSEL0_STCLKSEL_HXT (0x00UL<<CLK_CLKSEL0_STCLKSEL_Pos)

#define	CLK_CLKSEL0_STCLKSEL_LXT (0x01UL<<CLK_CLKSEL0_STCLKSEL_Pos)

#define	CLK_CLKSEL0_STCLKSEL_HXT_DIV2 (0x02UL<<CLK_CLKSEL0_STCLKSEL_Pos)

#define	CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 (0x03UL<<CLK_CLKSEL0_STCLKSEL_Pos)

#define	CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 (0x07UL<<CLK_CLKSEL0_STCLKSEL_Pos)

#define	CLK_CLKSEL0_STCLKSEL_HCLK (0x01UL<<SysTick_CTRL_CLKSOURCE_Pos)

#define	CLK_CLKSEL0_PCLK0SEL_HCLK (0x00UL<<CLK_CLKSEL0_PCLK0SEL_Pos)

#define	CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2 (0x01UL<<CLK_CLKSEL0_PCLK0SEL_Pos)

#define	CLK_CLKSEL0_PCLK1SEL_HCLK (0x00UL<<CLK_CLKSEL0_PCLK1SEL_Pos)

#define	CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2 (0x01UL<<CLK_CLKSEL0_PCLK1SEL_Pos)

#define	CLK_CLKSEL1_WDTSEL_LXT (0x1UL<<CLK_CLKSEL1_WDTSEL_Pos)

#define	CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_WDTSEL_Pos)

#define	CLK_CLKSEL1_WDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WDTSEL_Pos)

#define	CLK_CLKSEL1_TMR0SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR0SEL_Pos)

#define	CLK_CLKSEL1_TMR0SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR0SEL_Pos)

#define	CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL<<CLK_CLKSEL1_TMR0SEL_Pos)

#define	CLK_CLKSEL1_TMR0SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR0SEL_Pos)

#define	CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR0SEL_Pos)

#define	CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR0SEL_Pos)

#define	CLK_CLKSEL1_TMR1SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR1SEL_Pos)

#define	CLK_CLKSEL1_TMR1SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR1SEL_Pos)

#define	CLK_CLKSEL1_TMR1SEL_PCLK0 (0x2UL<<CLK_CLKSEL1_TMR1SEL_Pos)

#define	CLK_CLKSEL1_TMR1SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR1SEL_Pos)

#define	CLK_CLKSEL1_TMR1SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR1SEL_Pos)

#define	CLK_CLKSEL1_TMR1SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR1SEL_Pos)

#define	CLK_CLKSEL1_TMR2SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR2SEL_Pos)

#define	CLK_CLKSEL1_TMR2SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR2SEL_Pos)

#define	CLK_CLKSEL1_TMR2SEL_PCLK1 (0x2UL<<CLK_CLKSEL1_TMR2SEL_Pos)

#define	CLK_CLKSEL1_TMR2SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR2SEL_Pos)

#define	CLK_CLKSEL1_TMR2SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR2SEL_Pos)

#define	CLK_CLKSEL1_TMR2SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR2SEL_Pos)

#define	CLK_CLKSEL1_TMR3SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR3SEL_Pos)

#define	CLK_CLKSEL1_TMR3SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR3SEL_Pos)

#define	CLK_CLKSEL1_TMR3SEL_PCLK1 (0x2UL<<CLK_CLKSEL1_TMR3SEL_Pos)

#define	CLK_CLKSEL1_TMR3SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR3SEL_Pos)

#define	CLK_CLKSEL1_TMR3SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR3SEL_Pos)

#define	CLK_CLKSEL1_TMR3SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR3SEL_Pos)

#define	CLK_CLKSEL1_UARTSEL_HXT (0x0UL<<CLK_CLKSEL1_UARTSEL_Pos)

#define	CLK_CLKSEL1_UARTSEL_PLL (0x1UL<<CLK_CLKSEL1_UARTSEL_Pos)

#define	CLK_CLKSEL1_UARTSEL_LXT (0x2UL<<CLK_CLKSEL1_UARTSEL_Pos)

#define	CLK_CLKSEL1_UARTSEL_HIRC (0x3UL<<CLK_CLKSEL1_UARTSEL_Pos)

#define	CLK_CLKSEL1_CLKOSEL_HXT (0x0UL<<CLK_CLKSEL1_CLKOSEL_Pos)

#define	CLK_CLKSEL1_CLKOSEL_LXT (0x1UL<<CLK_CLKSEL1_CLKOSEL_Pos)

#define	CLK_CLKSEL1_CLKOSEL_HCLK (0x2UL<<CLK_CLKSEL1_CLKOSEL_Pos)

#define	CLK_CLKSEL1_CLKOSEL_HIRC (0x3UL<<CLK_CLKSEL1_CLKOSEL_Pos)

#define	CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_WWDTSEL_Pos)

#define	CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WWDTSEL_Pos)

#define	CLK_CLKSEL2_PWM0SEL_PLL (0x0UL<<CLK_CLKSEL2_PWM0SEL_Pos)

#define	CLK_CLKSEL2_PWM0SEL_PCLK0 (0x1UL<<CLK_CLKSEL2_PWM0SEL_Pos)

#define	CLK_CLKSEL2_PWM1SEL_PLL (0x0UL<<CLK_CLKSEL2_PWM1SEL_Pos)

#define	CLK_CLKSEL2_PWM1SEL_PCLK1 (0x1UL<<CLK_CLKSEL2_PWM1SEL_Pos)

#define	CLK_CLKSEL2_SPI0SEL_HXT (0x0UL<<CLK_CLKSEL2_SPI0SEL_Pos)

#define	CLK_CLKSEL2_SPI0SEL_PLL (0x1UL<<CLK_CLKSEL2_SPI0SEL_Pos)

#define	CLK_CLKSEL2_SPI0SEL_PCLK0 (0x2UL<<CLK_CLKSEL2_SPI0SEL_Pos)

#define	CLK_CLKSEL2_SPI0SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI0SEL_Pos)

#define	CLK_CLKSEL2_SPI1SEL_HXT (0x0UL<<CLK_CLKSEL2_SPI1SEL_Pos)

#define	CLK_CLKSEL2_SPI1SEL_PLL (0x1UL<<CLK_CLKSEL2_SPI1SEL_Pos)

#define	CLK_CLKSEL2_SPI1SEL_PCLK1 (0x2UL<<CLK_CLKSEL2_SPI1SEL_Pos)

#define	CLK_CLKSEL2_SPI1SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI1SEL_Pos)

#define	CLK_CLKSEL3_SC0SEL_HXT (0x0UL<<CLK_CLKSEL3_SC0SEL_Pos)

#define	CLK_CLKSEL3_SC0SEL_PLL (0x1UL<<CLK_CLKSEL3_SC0SEL_Pos)

#define	CLK_CLKSEL3_SC0SEL_PCLK0 (0x2UL<<CLK_CLKSEL3_SC0SEL_Pos)

#define	CLK_CLKSEL3_SC0SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC0SEL_Pos)

#define	CLK_CLKSEL3_RTCSEL_LXT (0x0UL<<CLK_CLKSEL3_RTCSEL_Pos)

#define	CLK_CLKSEL3_RTCSEL_LIRC (0x1UL<<CLK_CLKSEL3_RTCSEL_Pos)

#define	CLK_CLKDIV0_HCLK(x) (((x)-1) << CLK_CLKDIV0_HCLKDIV_Pos)

#define	CLK_CLKDIV0_USB(x) (((x)-1) << CLK_CLKDIV0_USBDIV_Pos)

#define	CLK_CLKDIV0_UART(x) (((x)-1) << CLK_CLKDIV0_UARTDIV_Pos)

#define	CLK_CLKDIV0_EADC(x) (((x)-1) << CLK_CLKDIV0_EADCDIV_Pos)

#define	CLK_CLKDIV1_SC0(x) (((x)-1) << CLK_CLKDIV1_SC0DIV_Pos)

#define	CLK_PLLCTL_PLLSRC_HXT 0x00000000UL

#define	CLK_PLLCTL_PLLSRC_HIRC 0x00080000UL

#define	CLK_PLLCTL_NF(x) ((x)-2)

#define	CLK_PLLCTL_NR(x) (((x)-2)<<9)

#define	CLK_PLLCTL_NO_1 0x0000UL

#define	CLK_PLLCTL_NO_2 0x4000UL

#define	CLK_PLLCTL_NO_4 0xC000UL

#define	CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT \| CLK_PLLCTL_NR(2) \| CLK_PLLCTL_NF( 48) \| CLK_PLLCTL_NO_4)

#define	CLK_PLLCTL_144MHz_HXT (CLK_PLLCTL_PLLSRC_HXT \| CLK_PLLCTL_NR(2) \| CLK_PLLCTL_NF( 48) \| CLK_PLLCTL_NO_2)

#define	CLK_PLLCTL_72MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC \| CLK_PLLCTL_NR(4) \| CLK_PLLCTL_NF( 52) \| CLK_PLLCTL_NO_4)

#define	MODULE_APBCLK(x) (((x) >>30) & 0x3)

#define	MODULE_CLKSEL(x) (((x) >>28) & 0x3)

#define	MODULE_CLKSEL_Msk(x) (((x) >>25) & 0x7)

#define	MODULE_CLKSEL_Pos(x) (((x) >>20) & 0x1f)

#define	MODULE_CLKDIV(x) (((x) >>18) & 0x3)

#define	MODULE_CLKDIV_Msk(x) (((x) >>10) & 0xff)

#define	MODULE_CLKDIV_Pos(x) (((x) >>5 ) & 0x1f)

#define	MODULE_IP_EN_Pos(x) (((x) >>0 ) & 0x1f)

#define	MODULE_NoMsk 0x0

#define	NA MODULE_NoMsk

#define	MODULE_APBCLK_ENC(x) (((x) & 0x03) << 30)

#define	MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 28)

#define	MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x07) << 25)

#define	MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20)

#define	MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18)

#define	MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10)

#define	MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5)

#define	MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0)

#define	PDMA_MODULE

#define	ISP_MODULE

#define	EBI_MODULE

#define	USBH_MODULE

#define	CRC_MODULE

#define	WDT_MODULE

#define	WWDT_MODULE

#define	RTC_MODULE

#define	TMR0_MODULE

#define	TMR1_MODULE

#define	TMR2_MODULE

#define	TMR3_MODULE

#define	CLKO_MODULE

#define	I2C0_MODULE

#define	I2C1_MODULE

#define	SPI0_MODULE

#define	SPI1_MODULE

#define	UART0_MODULE

#define	UART1_MODULE

#define	UART2_MODULE

#define	UART3_MODULE

#define	USBD_MODULE

#define	EADC_MODULE

#define	SC0_MODULE

#define	PWM0_MODULE

#define	PWM1_MODULE

#define	CLK_TIMEOUT_ERR

Functions
__STATIC_INLINE uint32_t	CLK_GetPLLClockFreq (void)
	Get PLL clock frequency. More...

__STATIC_INLINE int32_t	CLK_SysTickDelay (uint32_t us)
	This function execute delay function. More...

void	CLK_DisableCKO (void)
	Disable clock divider output function. More...

void	CLK_EnableCKO (uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
	This function enable clock divider output module clock, enable clock divider output function and set frequency selection. More...

void	CLK_PowerDown (void)
	Enter to Power-down mode. More...

void	CLK_Idle (void)
	Enter to Idle mode. More...

uint32_t	CLK_GetHXTFreq (void)
	Get external high speed crystal clock frequency. More...

uint32_t	CLK_GetLXTFreq (void)
	Get external low speed crystal clock frequency. More...

uint32_t	CLK_GetHCLKFreq (void)
	Get HCLK frequency. More...

uint32_t	CLK_GetPCLK0Freq (void)
	Get PCLK0 frequency. More...

uint32_t	CLK_GetPCLK1Freq (void)
	Get PCLK1 frequency. More...

uint32_t	CLK_GetCPUFreq (void)
	Get CPU frequency. More...

uint32_t	CLK_SetCoreClock (uint32_t u32Hclk)
	Set HCLK frequency. More...

void	CLK_SetHCLK (uint32_t u32ClkSrc, uint32_t u32ClkDiv)
	This function set HCLK clock source and HCLK clock divider. More...

void	CLK_SetModuleClock (uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
	This function set selected module clock source and module clock divider. More...

void	CLK_SetSysTickClockSrc (uint32_t u32ClkSrc)
	Set SysTick clock source. More...

void	CLK_EnableXtalRC (uint32_t u32ClkMask)
	Enable clock source. More...

void	CLK_DisableXtalRC (uint32_t u32ClkMask)
	Disable clock source. More...

void	CLK_EnableModuleClock (uint32_t u32ModuleIdx)
	Enable module clock. More...

void	CLK_DisableModuleClock (uint32_t u32ModuleIdx)
	Disable module clock. More...

uint32_t	CLK_EnablePLL (uint32_t u32PllClkSrc, uint32_t u32PllFreq)
	Set PLL frequency. More...

void	CLK_DisablePLL (void)
	Disable PLL. More...

uint32_t	CLK_WaitClockReady (uint32_t u32ClkMask)
	This function check selected clock source status. More...

void	CLK_EnableSysTick (uint32_t u32ClkSrc, uint32_t u32Count)
	Enable System Tick counter. More...

void	CLK_DisableSysTick (void)
	Disable System Tick counter. More...

Variables
int32_t	g_CLK_i32ErrCode

Detailed Description

M4521 CLK Header File.

Version: V3.0 $Revision 1 $

Date: 16/07/07 2:59p

Definition in file clk.h.

Macros

Functions

Variables

Detailed Description