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/******************************************************************************

 * @file     M4521.h

 * @version  V3.10

 * $Revision: 180 $

 * $Date: 16/07/07 2:55p $

 * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File for M4521 MCU

 *

 * @note

 * SPDX-License-Identifier: Apache-2.0

 * Copyright (C) 2022 Nuvoton Technology Corp. All rights reserved.

*****************************************************************************/

#ifndef __M4521_H__

#define __M4521_H__


#ifdef __cplusplus

extern "C" {

#endif


/******************************************************************************/

/*                Processor and Core Peripherals                              */

/******************************************************************************/

/*

 * ==========================================================================

 * ---------- Interrupt Number Definition -----------------------------------

 * ==========================================================================

 */


typedef enum IRQn

{

    /******  Cortex-M4 Processor Exceptions Numbers ***************************************************/

    NonMaskableInt_IRQn           = -14,

    MemoryManagement_IRQn         = -12,

    BusFault_IRQn                 = -11,

    UsageFault_IRQn               = -10,

    SVCall_IRQn                   = -5,

    DebugMonitor_IRQn             = -4,

    PendSV_IRQn                   = -2,

    SysTick_IRQn                  = -1,

    /******  M4521 Specific Interrupt Numbers ********************************************************/


    BOD_IRQn                      = 0,

    IRC_IRQn                      = 1,

    PWRWU_IRQn                    = 2,

    CKFAIL_IRQn                   = 4,

    RTC_IRQn                      = 6,

    TAMPER_IRQn                   = 7,

    WDT_IRQn                      = 8,

    WWDT_IRQn                     = 9,

    EINT0_IRQn                    = 10,

    EINT1_IRQn                    = 11,

    EINT2_IRQn                    = 12,

    EINT3_IRQn                    = 13,

    EINT4_IRQn                    = 14,

    EINT5_IRQn                    = 15,

    GPA_IRQn                      = 16,

    GPB_IRQn                      = 17,

    GPC_IRQn                      = 18,

    GPD_IRQn                      = 19,

    GPE_IRQn                      = 20,

    GPF_IRQn                      = 21,

    SPI0_IRQn                     = 22,

    SPI1_IRQn                     = 23,

    BRAKE0_IRQn                   = 24,

    PWM0P0_IRQn                   = 25,

    PWM0P1_IRQn                   = 26,

    PWM0P2_IRQn                   = 27,

    BRAKE1_IRQn                   = 28,

    PWM1P0_IRQn                   = 29,

    PWM1P1_IRQn                   = 30,

    PWM1P2_IRQn                   = 31,

    TMR0_IRQn                     = 32,

    TMR1_IRQn                     = 33,

    TMR2_IRQn                     = 34,

    TMR3_IRQn                     = 35,

    UART0_IRQn                    = 36,

    UART1_IRQn                    = 37,

    I2C0_IRQn                     = 38,

    I2C1_IRQn                     = 39,

    PDMA_IRQn                     = 40,

    ADC00_IRQn                    = 42,

    ADC01_IRQn                    = 43,

    ADC02_IRQn                    = 46,

    ADC03_IRQn                    = 47,

    UART2_IRQn                    = 48,

    UART3_IRQn                    = 49,

    USBD_IRQn                     = 53,

    USBH_IRQn                     = 54,

    SC0_IRQn                      = 58,

} IRQn_Type;


/*

 * ==========================================================================

 * ----------- Processor and Core Peripheral Section ------------------------

 * ==========================================================================

 */


/* Configuration of the Cortex-M# Processor and Core Peripherals */

#define __CM4_REV                 0x0201

#define __NVIC_PRIO_BITS          4

#define __Vendor_SysTickConfig    0

#define __MPU_PRESENT             1

#define __FPU_PRESENT             1          /* end of group CMSIS */


#include "core_cm4.h"                       /* Cortex-M4 processor and core peripherals           */

#include "system_M4521.h"              /* M4521 System include file                           */

#include <stdint.h>


/******************************************************************************/

/*                Device Specific Peripheral registers structures             */

/******************************************************************************/


/*---------------------- Enhanced Analog to Digital Converter -------------------------*/

typedef struct

{


    __I  uint32_t DAT[19];       /* Offset: 0x00-0x48  A/D Data Register n for Sample Module n, n=0~18               */

    __I  uint32_t CURDAT;        /* Offset: 0x4C  EADC PDMA Current Transfer Data Register                           */

    __IO uint32_t CTL;           /* Offset: 0x50  A/D Control Register                                               */

    __O  uint32_t SWTRG;         /* Offset: 0x54  A/D Sample Module Software Start Register                          */

    __IO uint32_t PENDSTS;       /* Offset: 0x58  A/D Start of Conversion Pending Flag Register                      */

    __IO uint32_t OVSTS;         /* Offset: 0x5C  A/D Sample Module Start of Conversion Overrun Flag Register        */

    __I  uint32_t RESERVE0[8];

    __IO uint32_t SCTL[19];      /* Offset: 0x80-0xC8  A/D Sample Module n Control Register, n=0~3                   */

    __I  uint32_t RESERVE1[1];

    __IO uint32_t INTSRC[4];     /* Offset: 0xDC  ADC interrupt n Source Enable Control Register, n=0~3              */

    __IO uint32_t CMP[4];        /* Offset: 0xEC  A/D Result Compare Register n, n=0~3                               */

    __I  uint32_t STATUS0;       /* Offset: 0xF0  A/D Status Register 0                                              */

    __I  uint32_t STATUS1;       /* Offset: 0xF4  A/D Status Register 1                                              */

    __IO uint32_t STATUS2;       /* Offset: 0xF8  A/D Status Register 2                                              */

    __I  uint32_t STATUS3;       /* Offset: 0xFC  A/D Status Register 3                                              */

    __I  uint32_t DDAT[4];       /* Offset: 0x100-0x10C  A/D Double Data Register n for Sample Module n, n=0~3       */


} EADC_T;


#define EADC_DAT_RESULT_Pos               (0)

#define EADC_DAT_RESULT_Msk               (0xfffful << EADC_DAT_RESULT_Pos)

#define EADC_DAT_OV_Pos                   (16)

#define EADC_DAT_OV_Msk                   (0x1ul << EADC_DAT_OV_Pos)

#define EADC_DAT_VALID_Pos                (17)

#define EADC_DAT_VALID_Msk                (0x1ul << EADC_DAT_VALID_Pos)

#define EADC_CURDAT_CURDAT_Pos            (0)

#define EADC_CURDAT_CURDAT_Msk            (0x3fffful << EADC_CURDAT_CURDAT_Pos)

#define EADC_CTL_ADCEN_Pos                (0)

#define EADC_CTL_ADCEN_Msk                (0x1ul << EADC_CTL_ADCEN_Pos)

#define EADC_CTL_ADRST_Pos                (1)

#define EADC_CTL_ADRST_Msk                (0x1ul << EADC_CTL_ADRST_Pos)

#define EADC_CTL_ADCIEN0_Pos              (2)

#define EADC_CTL_ADCIEN0_Msk              (0x1ul << EADC_CTL_ADCIEN0_Pos)

#define EADC_CTL_ADCIEN1_Pos              (3)

#define EADC_CTL_ADCIEN1_Msk              (0x1ul << EADC_CTL_ADCIEN1_Pos)

#define EADC_CTL_ADCIEN2_Pos              (4)

#define EADC_CTL_ADCIEN2_Msk              (0x1ul << EADC_CTL_ADCIEN2_Pos)

#define EADC_CTL_ADCIEN3_Pos              (5)

#define EADC_CTL_ADCIEN3_Msk              (0x1ul << EADC_CTL_ADCIEN3_Pos)

#define EADC_CTL_DIFFEN_Pos               (8)

#define EADC_CTL_DIFFEN_Msk               (0x1ul << EADC_CTL_DIFFEN_Pos)

#define EADC_CTL_DMOF_Pos                 (9)

#define EADC_CTL_DMOF_Msk                 (0x1ul << EADC_CTL_DMOF_Pos)

#define EADC_CTL_PDMAEN_Pos               (11)

#define EADC_CTL_PDMAEN_Msk               (0x1ul << EADC_CTL_PDMAEN_Pos)

#define EADC_CTL_SMPTSEL_Pos              (16)

#define EADC_CTL_SMPTSEL_Msk              (0x7ul << EADC_CTL_SMPTSEL_Pos)

#define EADC_SWTRG_SWTRG_Pos              (0)

#define EADC_SWTRG_SWTRG_Msk              (0x7fffful << EADC_SWTRG_SWTRG_Pos)

#define EADC_PENDSTS_STPF_Pos             (0)

#define EADC_PENDSTS_STPF_Msk             (0x7fffful << EADC_PENDSTS_STPF_Pos)

#define EADC_OVSTS_SPOVF_Pos              (0)

#define EADC_OVSTS_SPOVF_Msk              (0x7fffful << EADC_OVSTS_SPOVF_Pos)

#define EADC_SCTL_CHSEL_Pos               (0)

#define EADC_SCTL_CHSEL_Msk               (0xful << EADC_SCTL_CHSEL_Pos)

#define EADC_SCTL_EXTREN_Pos              (4)

#define EADC_SCTL_EXTREN_Msk              (0x1ul << EADC_SCTL_EXTREN_Pos)

#define EADC_SCTL_EXTFEN_Pos              (5)

#define EADC_SCTL_EXTFEN_Msk              (0x1ul << EADC_SCTL_EXTFEN_Pos)

#define EADC_SCTL_TRGDLYDIV_Pos           (6)

#define EADC_SCTL_TRGDLYDIV_Msk           (0x3ul << EADC_SCTL_TRGDLYDIV_Pos)

#define EADC_SCTL_TRGDLYCNT_Pos           (8)

#define EADC_SCTL_TRGDLYCNT_Msk           (0xfful << EADC_SCTL_TRGDLYCNT_Pos)

#define EADC_SCTL_TRGSEL_Pos              (16)

#define EADC_SCTL_TRGSEL_Msk              (0x1ful << EADC_SCTL_TRGSEL_Pos)

#define EADC_SCTL_INTPOS_Pos              (22)

#define EADC_SCTL_INTPOS_Msk              (0x1ul << EADC_SCTL_INTPOS_Pos)

#define EADC_SCTL_DBMEN_Pos               (23)

#define EADC_SCTL_DBMEN_Msk               (0x1ul << EADC_SCTL_DBMEN_Pos)

#define EADC_SCTL_EXTSMPT_Pos             (24)

#define EADC_SCTL_EXTSMPT_Msk             (0xfful << EADC_SCTL_EXTSMPT_Pos)

#define EADC_INTSRC_SPLIE_Pos             (0)

#define EADC_INTSRC_SPLIE_Msk             (0x7FFFFul << EADC_INTSRC_SPLIE_Pos)

#define EADC_CMP_ADCMPEN_Pos              (0)

#define EADC_CMP_ADCMPEN_Msk              (0x1ul << EADC_CMP_ADCMPEN_Pos)

#define EADC_CMP_ADCMPIE_Pos              (1)

#define EADC_CMP_ADCMPIE_Msk              (0x1ul << EADC_CMP_ADCMPIE_Pos)

#define EADC_CMP_CMPCOND_Pos              (2)

#define EADC_CMP_CMPCOND_Msk              (0x1ul << EADC_CMP_CMPCOND_Pos)

#define EADC_CMP_CMPSPL_Pos               (3)

#define EADC_CMP_CMPSPL_Msk               (0x1ful << EADC_CMP_CMPSPL_Pos)

#define EADC_CMP_CMPMCNT_Pos              (8)

#define EADC_CMP_CMPMCNT_Msk              (0xful << EADC_CMP_CMPMCNT_Pos)

#define EADC_CMP_CMPWEN_Pos               (15)

#define EADC_CMP_CMPWEN_Msk               (0x1ul << EADC_CMP_CMPWEN_Pos)

#define EADC_CMP_CMPDAT_Pos               (16)

#define EADC_CMP_CMPDAT_Msk               (0xffful << EADC_CMP_CMPDAT_Pos)

#define EADC_STATUS0_VALID_Pos            (0)

#define EADC_STATUS0_VALID_Msk            (0xfffful << EADC_STATUS0_VALID_Pos)

#define EADC_STATUS0_OV_Pos               (16)

#define EADC_STATUS0_OV_Msk               (0xfffful << EADC_STATUS0_OV_Pos)

#define EADC_STATUS1_VALID_Pos            (0)

#define EADC_STATUS1_VALID_Msk            (0x7ul << EADC_STATUS1_VALID_Pos)

#define EADC_STATUS1_OV_Pos               (16)

#define EADC_STATUS1_OV_Msk               (0x7ul << EADC_STATUS1_OV_Pos)

#define EADC_STATUS2_ADIF0_Pos            (0)

#define EADC_STATUS2_ADIF0_Msk            (0x1ul << EADC_STATUS2_ADIF0_Pos)

#define EADC_STATUS2_ADIF1_Pos            (1)

#define EADC_STATUS2_ADIF1_Msk            (0x1ul << EADC_STATUS2_ADIF1_Pos)

#define EADC_STATUS2_ADIF2_Pos            (2)

#define EADC_STATUS2_ADIF2_Msk            (0x1ul << EADC_STATUS2_ADIF2_Pos)

#define EADC_STATUS2_ADIF3_Pos            (3)

#define EADC_STATUS2_ADIF3_Msk            (0x1ul << EADC_STATUS2_ADIF3_Pos)

#define EADC_STATUS2_ADCMPF0_Pos          (4)

#define EADC_STATUS2_ADCMPF0_Msk          (0x1ul << EADC_STATUS2_ADCMPF0_Pos)

#define EADC_STATUS2_ADCMPF1_Pos          (5)

#define EADC_STATUS2_ADCMPF1_Msk          (0x1ul << EADC_STATUS2_ADCMPF1_Pos)

#define EADC_STATUS2_ADCMPF2_Pos          (6)

#define EADC_STATUS2_ADCMPF2_Msk          (0x1ul << EADC_STATUS2_ADCMPF2_Pos)

#define EADC_STATUS2_ADCMPF3_Pos          (7)

#define EADC_STATUS2_ADCMPF3_Msk          (0x1ul << EADC_STATUS2_ADCMPF3_Pos)

#define EADC_STATUS2_ADOVIF0_Pos          (8)

#define EADC_STATUS2_ADOVIF0_Msk          (0x1ul << EADC_STATUS2_ADOVIF0_Pos)

#define EADC_STATUS2_ADOVIF1_Pos          (9)

#define EADC_STATUS2_ADOVIF1_Msk          (0x1ul << EADC_STATUS2_ADOVIF1_Pos)

#define EADC_STATUS2_ADOVIF2_Pos          (10)

#define EADC_STATUS2_ADOVIF2_Msk          (0x1ul << EADC_STATUS2_ADOVIF2_Pos)

#define EADC_STATUS2_ADOVIF3_Pos          (11)

#define EADC_STATUS2_ADOVIF3_Msk          (0x1ul << EADC_STATUS2_ADOVIF3_Pos)

#define EADC_STATUS2_ADCMPO0_Pos          (12)

#define EADC_STATUS2_ADCMPO0_Msk          (0x1ul << EADC_STATUS2_ADCMPO0_Pos)

#define EADC_STATUS2_ADCMPO1_Pos          (13)

#define EADC_STATUS2_ADCMPO1_Msk          (0x1ul << EADC_STATUS2_ADCMPO1_Pos)

#define EADC_STATUS2_ADCMPO2_Pos          (14)

#define EADC_STATUS2_ADCMPO2_Msk          (0x1ul << EADC_STATUS2_ADCMPO2_Pos)

#define EADC_STATUS2_ADCMPO3_Pos          (15)

#define EADC_STATUS2_ADCMPO3_Msk          (0x1ul << EADC_STATUS2_ADCMPO3_Pos)

#define EADC_STATUS2_CHANNEL_Pos          (16)

#define EADC_STATUS2_CHANNEL_Msk          (0x1ful << EADC_STATUS2_CHANNEL_Pos)

#define EADC_STATUS2_BUSY_Pos             (23)

#define EADC_STATUS2_BUSY_Msk             (0x1ul << EADC_STATUS2_BUSY_Pos)

#define EADC_STATUS2_ADOVIF_Pos           (24)

#define EADC_STATUS2_ADOVIF_Msk           (0x1ul << EADC_STATUS2_ADOVIF_Pos)

#define EADC_STATUS2_STOVF_Pos            (25)

#define EADC_STATUS2_STOVF_Msk            (0x1ul << EADC_STATUS2_STOVF_Pos)

#define EADC_STATUS2_AVALID_Pos           (26)

#define EADC_STATUS2_AVALID_Msk           (0x1ul << EADC_STATUS2_AVALID_Pos)

#define EADC_STATUS2_AOV_Pos              (27)

#define EADC_STATUS2_AOV_Msk              (0x1ul << EADC_STATUS2_AOV_Pos)

#define EADC_STATUS3_CURSPL_Pos           (0)

#define EADC_STATUS3_CURSPL_Msk           (0x1ful << EADC_STATUS3_CURSPL_Pos)

#define EADC_DDAT_RESULT_Pos              (0)

#define EADC_DDAT_RESULT_Msk              (0xfffful << EADC_DDAT_RESULT_Pos)

#define EADC_DDAT_OV_Pos                  (16)

#define EADC_DDAT_OV_Msk                  (0x1ul << EADC_DDAT_OV_Pos)

#define EADC_DDAT_VALID_Pos               (17)

#define EADC_DDAT_VALID_Msk               (0x1ul << EADC_DDAT_VALID_Pos)                     /* EADC_CONST */ /* end of EADC register group */


/*---------------------- System Clock Controller -------------------------*/

typedef struct

{


    __IO uint32_t PWRCTL;        /* Offset: 0x00  System Power-down Control Register                                 */

    __IO uint32_t AHBCLK;        /* Offset: 0x04  AHB Devices Clock Enable Control Register                          */

    __IO uint32_t APBCLK0;       /* Offset: 0x08  APB Devices Clock Enable Control Register 0                        */

    __IO uint32_t APBCLK1;       /* Offset: 0x0C  APB Devices Clock Enable Control Register 1                        */

    __IO uint32_t CLKSEL0;       /* Offset: 0x10  Clock Source Select Control Register 0                             */

    __IO uint32_t CLKSEL1;       /* Offset: 0x14  Clock Source Select Control Register 1                             */

    __IO uint32_t CLKSEL2;       /* Offset: 0x18  Clock Source Select Control Register 2                             */

    __IO uint32_t CLKSEL3;       /* Offset: 0x1C  Clock Source Select Control Register 3                             */

    __IO uint32_t CLKDIV0;       /* Offset: 0x20  Clock Divider Number Register 0                                    */

    __IO uint32_t CLKDIV1;       /* Offset: 0x24  Clock Divider Number Register 1                                    */

    __I  uint32_t RESERVE0[6];

    __IO uint32_t PLLCTL;        /* Offset: 0x40  PLL Control Register                                               */

    __I  uint32_t RESERVE1[3];

    __I  uint32_t STATUS;        /* Offset: 0x50  Clock Status Monitor Register                                      */

    __I  uint32_t RESERVE2[3];

    __IO uint32_t CLKOCTL;       /* Offset: 0x60  Clock Output Control Register                                      */

    __I  uint32_t RESERVE3[3];

    __IO uint32_t CLKDCTL;       /* Offset: 0x70  Clock Fail Detector Control Register                               */

    __IO uint32_t CLKDSTS;       /* Offset: 0x74  Clock Fail Detector Status Register                                */

    __IO uint32_t CDUPB;         /* Offset: 0x78  Clock Frequency Detector Upper Boundary Register                   */

    __IO uint32_t CDLOWB;        /* Offset: 0x7C  Clock Frequency Detector Low Boundary Register                     */


} CLK_T;


#define CLK_PWRCTL_HXTEN_Pos             (0)

#define CLK_PWRCTL_HXTEN_Msk             (0x1ul << CLK_PWRCTL_HXTEN_Pos)

#define CLK_PWRCTL_LXTEN_Pos             (1)

#define CLK_PWRCTL_LXTEN_Msk             (0x1ul << CLK_PWRCTL_LXTEN_Pos)

#define CLK_PWRCTL_HIRCEN_Pos            (2)

#define CLK_PWRCTL_HIRCEN_Msk            (0x1ul << CLK_PWRCTL_HIRCEN_Pos)

#define CLK_PWRCTL_LIRCEN_Pos            (3)

#define CLK_PWRCTL_LIRCEN_Msk            (0x1ul << CLK_PWRCTL_LIRCEN_Pos)

#define CLK_PWRCTL_PDWKDLY_Pos           (4)

#define CLK_PWRCTL_PDWKDLY_Msk           (0x1ul << CLK_PWRCTL_PDWKDLY_Pos)

#define CLK_PWRCTL_PDWKIEN_Pos           (5)

#define CLK_PWRCTL_PDWKIEN_Msk           (0x1ul << CLK_PWRCTL_PDWKIEN_Pos)

#define CLK_PWRCTL_PDWKIF_Pos            (6)

#define CLK_PWRCTL_PDWKIF_Msk            (0x1ul << CLK_PWRCTL_PDWKIF_Pos)

#define CLK_PWRCTL_PDEN_Pos              (7)

#define CLK_PWRCTL_PDEN_Msk              (0x1ul << CLK_PWRCTL_PDEN_Pos)

#define CLK_PWRCTL_PDWTCPU_Pos           (8)

#define CLK_PWRCTL_PDWTCPU_Msk           (0x1ul << CLK_PWRCTL_PDWTCPU_Pos)

#define CLK_PWRCTL_HXTGAIN_Pos           (10)

#define CLK_PWRCTL_HXTGAIN_Msk           (0x3ul << CLK_PWRCTL_HXTGAIN_Pos)

#define CLK_PWRCTL_HXTSELTYP_Pos         (12)

#define CLK_PWRCTL_HXTSELTYP_Msk         (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos)

#define CLK_PWRCTL_HIRC48MEN_Pos         (24)

#define CLK_PWRCTL_HIRC48MEN_Msk         (0x1ul << CLK_PWRCTL_HIRC48MEN_Pos)

#define CLK_AHBCLK_PDMACKEN_Pos          (1)

#define CLK_AHBCLK_PDMACKEN_Msk          (0x1ul << CLK_AHBCLK_PDMACKEN_Pos)

#define CLK_AHBCLK_ISPCKEN_Pos           (2)

#define CLK_AHBCLK_ISPCKEN_Msk           (0x1ul << CLK_AHBCLK_ISPCKEN_Pos)

#define CLK_AHBCLK_EBICKEN_Pos           (3)

#define CLK_AHBCLK_EBICKEN_Msk           (0x1ul << CLK_AHBCLK_EBICKEN_Pos)

#define CLK_AHBCLK_USBHCKEN_Pos          (4)

#define CLK_AHBCLK_USBHCKEN_Msk          (0x1ul << CLK_AHBCLK_USBHCKEN_Pos)

#define CLK_AHBCLK_CRCCKEN_Pos           (7)

#define CLK_AHBCLK_CRCCKEN_Msk           (0x1ul << CLK_AHBCLK_CRCCKEN_Pos)

#define CLK_AHBCLK_FMCIDLE_Pos           (15)

#define CLK_AHBCLK_FMCIDLE_Msk           (0x1ul << CLK_AHBCLK_FMCIDLE_Pos)

#define CLK_APBCLK0_WDTCKEN_Pos          (0)

#define CLK_APBCLK0_WDTCKEN_Msk          (0x1ul << CLK_APBCLK0_WDTCKEN_Pos)

#define CLK_APBCLK0_RTCCKEN_Pos          (1)

#define CLK_APBCLK0_RTCCKEN_Msk          (0x1ul << CLK_APBCLK0_RTCCKEN_Pos)

#define CLK_APBCLK0_TMR0CKEN_Pos         (2)

#define CLK_APBCLK0_TMR0CKEN_Msk         (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos)

#define CLK_APBCLK0_TMR1CKEN_Pos         (3)

#define CLK_APBCLK0_TMR1CKEN_Msk         (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos)

#define CLK_APBCLK0_TMR2CKEN_Pos         (4)

#define CLK_APBCLK0_TMR2CKEN_Msk         (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos)

#define CLK_APBCLK0_TMR3CKEN_Pos         (5)

#define CLK_APBCLK0_TMR3CKEN_Msk         (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos)

#define CLK_APBCLK0_CLKOCKEN_Pos         (6)

#define CLK_APBCLK0_CLKOCKEN_Msk         (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos)

#define CLK_APBCLK0_I2C0CKEN_Pos         (8)

#define CLK_APBCLK0_I2C0CKEN_Msk         (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos)

#define CLK_APBCLK0_I2C1CKEN_Pos         (9)

#define CLK_APBCLK0_I2C1CKEN_Msk         (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos)

#define CLK_APBCLK0_SPI0CKEN_Pos         (12)

#define CLK_APBCLK0_SPI0CKEN_Msk         (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos)

#define CLK_APBCLK0_SPI1CKEN_Pos         (13)

#define CLK_APBCLK0_SPI1CKEN_Msk         (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos)

#define CLK_APBCLK0_UART0CKEN_Pos        (16)

#define CLK_APBCLK0_UART0CKEN_Msk        (0x1ul << CLK_APBCLK0_UART0CKEN_Pos)

#define CLK_APBCLK0_UART1CKEN_Pos        (17)

#define CLK_APBCLK0_UART1CKEN_Msk        (0x1ul << CLK_APBCLK0_UART1CKEN_Pos)

#define CLK_APBCLK0_UART2CKEN_Pos        (18)

#define CLK_APBCLK0_UART2CKEN_Msk        (0x1ul << CLK_APBCLK0_UART2CKEN_Pos)

#define CLK_APBCLK0_UART3CKEN_Pos        (19)

#define CLK_APBCLK0_UART3CKEN_Msk        (0x1ul << CLK_APBCLK0_UART3CKEN_Pos)

#define CLK_APBCLK0_USBDCKEN_Pos         (27)

#define CLK_APBCLK0_USBDCKEN_Msk         (0x1ul << CLK_APBCLK0_USBDCKEN_Pos)

#define CLK_APBCLK0_EADCCKEN_Pos         (28)

#define CLK_APBCLK0_EADCCKEN_Msk         (0x1ul << CLK_APBCLK0_EADCCKEN_Pos)

#define CLK_APBCLK1_SC0CKEN_Pos          (0)

#define CLK_APBCLK1_SC0CKEN_Msk          (0x1ul << CLK_APBCLK1_SC0CKEN_Pos)

#define CLK_APBCLK1_PWM0CKEN_Pos         (16)

#define CLK_APBCLK1_PWM0CKEN_Msk         (0x1ul << CLK_APBCLK1_PWM0CKEN_Pos)

#define CLK_APBCLK1_PWM1CKEN_Pos         (17)

#define CLK_APBCLK1_PWM1CKEN_Msk         (0x1ul << CLK_APBCLK1_PWM1CKEN_Pos)

#define CLK_APBCLK1_TKCKEN_Pos           (25)

#define CLK_APBCLK1_TKCKEN_Msk           (0x1ul << CLK_APBCLK1_TKCKEN_Pos)

#define CLK_CLKSEL0_HCLKSEL_Pos          (0)

#define CLK_CLKSEL0_HCLKSEL_Msk          (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos)

#define CLK_CLKSEL0_STCLKSEL_Pos         (3)

#define CLK_CLKSEL0_STCLKSEL_Msk         (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos)

#define CLK_CLKSEL0_PCLK0SEL_Pos         (6)

#define CLK_CLKSEL0_PCLK0SEL_Msk         (0x1ul << CLK_CLKSEL0_PCLK0SEL_Pos)

#define CLK_CLKSEL0_PCLK1SEL_Pos         (7)

#define CLK_CLKSEL0_PCLK1SEL_Msk         (0x1ul << CLK_CLKSEL0_PCLK1SEL_Pos)

#define CLK_CLKSEL0_USBCKSEL_Pos         (8)

#define CLK_CLKSEL0_USBCKSEL_Msk         (0x1ul << CLK_CLKSEL0_USBCKSEL_Pos)

#define CLK_CLKSEL1_WDTSEL_Pos           (0)

#define CLK_CLKSEL1_WDTSEL_Msk           (0x3ul << CLK_CLKSEL1_WDTSEL_Pos)

#define CLK_CLKSEL1_TMR0SEL_Pos          (8)

#define CLK_CLKSEL1_TMR0SEL_Msk          (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos)

#define CLK_CLKSEL1_TMR1SEL_Pos          (12)

#define CLK_CLKSEL1_TMR1SEL_Msk          (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos)

#define CLK_CLKSEL1_TMR2SEL_Pos          (16)

#define CLK_CLKSEL1_TMR2SEL_Msk          (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos)

#define CLK_CLKSEL1_TMR3SEL_Pos          (20)

#define CLK_CLKSEL1_TMR3SEL_Msk          (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos)

#define CLK_CLKSEL1_UARTSEL_Pos          (24)

#define CLK_CLKSEL1_UARTSEL_Msk          (0x3ul << CLK_CLKSEL1_UARTSEL_Pos)

#define CLK_CLKSEL1_CLKOSEL_Pos          (28)

#define CLK_CLKSEL1_CLKOSEL_Msk          (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos)

#define CLK_CLKSEL1_WWDTSEL_Pos          (30)

#define CLK_CLKSEL1_WWDTSEL_Msk          (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos)

#define CLK_CLKSEL2_PWM0SEL_Pos          (0)

#define CLK_CLKSEL2_PWM0SEL_Msk          (0x1ul << CLK_CLKSEL2_PWM0SEL_Pos)

#define CLK_CLKSEL2_PWM1SEL_Pos          (1)

#define CLK_CLKSEL2_PWM1SEL_Msk          (0x1ul << CLK_CLKSEL2_PWM1SEL_Pos)

#define CLK_CLKSEL2_SPI0SEL_Pos          (2)

#define CLK_CLKSEL2_SPI0SEL_Msk          (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos)

#define CLK_CLKSEL2_SPI1SEL_Pos          (4)

#define CLK_CLKSEL2_SPI1SEL_Msk          (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos)

#define CLK_CLKSEL3_SC0SEL_Pos           (0)

#define CLK_CLKSEL3_SC0SEL_Msk           (0x3ul << CLK_CLKSEL3_SC0SEL_Pos)

#define CLK_CLKSEL3_RTCSEL_Pos           (8)

#define CLK_CLKSEL3_RTCSEL_Msk           (0x1ul << CLK_CLKSEL3_RTCSEL_Pos)

#define CLK_CLKDIV0_HCLKDIV_Pos          (0)

#define CLK_CLKDIV0_HCLKDIV_Msk          (0xful << CLK_CLKDIV0_HCLKDIV_Pos)

#define CLK_CLKDIV0_USBDIV_Pos           (4)

#define CLK_CLKDIV0_USBDIV_Msk           (0xful << CLK_CLKDIV0_USBDIV_Pos)

#define CLK_CLKDIV0_UARTDIV_Pos          (8)

#define CLK_CLKDIV0_UARTDIV_Msk          (0xful << CLK_CLKDIV0_UARTDIV_Pos)

#define CLK_CLKDIV0_EADCDIV_Pos          (16)

#define CLK_CLKDIV0_EADCDIV_Msk          (0xfful << CLK_CLKDIV0_EADCDIV_Pos)

#define CLK_CLKDIV1_SC0DIV_Pos           (0)

#define CLK_CLKDIV1_SC0DIV_Msk           (0xfful << CLK_CLKDIV1_SC0DIV_Pos)

#define CLK_PLLCTL_FBDIV_Pos             (0)

#define CLK_PLLCTL_FBDIV_Msk             (0x1fful << CLK_PLLCTL_FBDIV_Pos)

#define CLK_PLLCTL_INDIV_Pos             (9)

#define CLK_PLLCTL_INDIV_Msk             (0x1ful << CLK_PLLCTL_INDIV_Pos)

#define CLK_PLLCTL_OUTDIV_Pos            (14)

#define CLK_PLLCTL_OUTDIV_Msk            (0x3ul << CLK_PLLCTL_OUTDIV_Pos)

#define CLK_PLLCTL_PD_Pos                (16)

#define CLK_PLLCTL_PD_Msk                (0x1ul << CLK_PLLCTL_PD_Pos)

#define CLK_PLLCTL_BP_Pos                (17)

#define CLK_PLLCTL_BP_Msk                (0x1ul << CLK_PLLCTL_BP_Pos)

#define CLK_PLLCTL_OE_Pos                (18)

#define CLK_PLLCTL_OE_Msk                (0x1ul << CLK_PLLCTL_OE_Pos)

#define CLK_PLLCTL_PLLSRC_Pos            (19)

#define CLK_PLLCTL_PLLSRC_Msk            (0x1ul << CLK_PLLCTL_PLLSRC_Pos)

#define CLK_PLLCTL_STBSEL_Pos            (23)

#define CLK_PLLCTL_STBSEL_Msk            (0x1ul << CLK_PLLCTL_STBSEL_Pos)

#define CLK_STATUS_HXTSTB_Pos            (0)

#define CLK_STATUS_HXTSTB_Msk            (0x1ul << CLK_STATUS_HXTSTB_Pos)

#define CLK_STATUS_LXTSTB_Pos            (1)

#define CLK_STATUS_LXTSTB_Msk            (0x1ul << CLK_STATUS_LXTSTB_Pos)

#define CLK_STATUS_PLLSTB_Pos            (2)

#define CLK_STATUS_PLLSTB_Msk            (0x1ul << CLK_STATUS_PLLSTB_Pos)

#define CLK_STATUS_LIRCSTB_Pos           (3)

#define CLK_STATUS_LIRCSTB_Msk           (0x1ul << CLK_STATUS_LIRCSTB_Pos)

#define CLK_STATUS_HIRCSTB_Pos           (4)

#define CLK_STATUS_HIRCSTB_Msk           (0x1ul << CLK_STATUS_HIRCSTB_Pos)

#define CLK_STATUS_CLKSFAIL_Pos          (7)

#define CLK_STATUS_CLKSFAIL_Msk          (0x1ul << CLK_STATUS_CLKSFAIL_Pos)

#define CLK_CLKOCTL_FREQSEL_Pos          (0)

#define CLK_CLKOCTL_FREQSEL_Msk          (0xful << CLK_CLKOCTL_FREQSEL_Pos)

#define CLK_CLKOCTL_CLKOEN_Pos           (4)

#define CLK_CLKOCTL_CLKOEN_Msk           (0x1ul << CLK_CLKOCTL_CLKOEN_Pos)

#define CLK_CLKOCTL_DIV1EN_Pos           (5)

#define CLK_CLKOCTL_DIV1EN_Msk           (0x1ul << CLK_CLKOCTL_DIV1EN_Pos)

#define CLK_CLKOCTL_CLK1HZEN_Pos         (6)

#define CLK_CLKOCTL_CLK1HZEN_Msk         (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos)

#define CLK_CLKDCTL_HXTFDEN_Pos          (4)

#define CLK_CLKDCTL_HXTFDEN_Msk          (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos)

#define CLK_CLKDCTL_HXTFIEN_Pos          (5)

#define CLK_CLKDCTL_HXTFIEN_Msk          (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos)

#define CLK_CLKDCTL_LXTFDEN_Pos          (12)

#define CLK_CLKDCTL_LXTFDEN_Msk          (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos)

#define CLK_CLKDCTL_LXTFIEN_Pos          (13)

#define CLK_CLKDCTL_LXTFIEN_Msk          (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos)

#define CLK_CLKDCTL_HXTFQDEN_Pos         (16)

#define CLK_CLKDCTL_HXTFQDEN_Msk         (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos)

#define CLK_CLKDCTL_HXTFQIEN_Pos         (17)

#define CLK_CLKDCTL_HXTFQIEN_Msk         (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos)

#define CLK_CLKDSTS_HXTFIF_Pos           (0)

#define CLK_CLKDSTS_HXTFIF_Msk           (0x1ul << CLK_CLKDSTS_HXTFIF_Pos)

#define CLK_CLKDSTS_LXTFIF_Pos           (1)

#define CLK_CLKDSTS_LXTFIF_Msk           (0x1ul << CLK_CLKDSTS_LXTFIF_Pos)

#define CLK_CLKDSTS_HXTFQIF_Pos          (8)

#define CLK_CLKDSTS_HXTFQIF_Msk          (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos)

#define CLK_CDUPB_UPERBD_Pos             (0)

#define CLK_CDUPB_UPERBD_Msk             (0x3fful << CLK_CDUPB_UPERBD_Pos)

#define CLK_CDLOWB_LOWERBD_Pos           (0)

#define CLK_CDLOWB_LOWERBD_Msk           (0x3fful << CLK_CDLOWB_LOWERBD_Pos)                /* CLK_CONST */ /* end of CLK register group */


/*---------------------- Cyclic Redundancy Check Controller -------------------------*/

typedef struct

{


    __IO uint32_t CTL;           /* Offset: 0x00  CRC Control Register                                               */

    __IO uint32_t DAT;           /* Offset: 0x04  CRC Write Data Register                                            */

    __IO uint32_t SEED;          /* Offset: 0x08  CRC Seed Register                                                  */

    __I  uint32_t CHECKSUM;      /* Offset: 0x0C  CRC Checksum Register                                              */


} CRC_T;


#define CRC_CTL_CRCEN_Pos                (0)

#define CRC_CTL_CRCEN_Msk                (0x1ul << CRC_CTL_CRCEN_Pos)

#define CRC_CTL_CRCRST_Pos               (1)

#define CRC_CTL_CRCRST_Msk               (0x1ul << CRC_CTL_CRCRST_Pos)

#define CRC_CTL_DATREV_Pos               (24)

#define CRC_CTL_DATREV_Msk               (0x1ul << CRC_CTL_DATREV_Pos)

#define CRC_CTL_CHKSREV_Pos              (25)

#define CRC_CTL_CHKSREV_Msk              (0x1ul << CRC_CTL_CHKSREV_Pos)

#define CRC_CTL_DATFMT_Pos               (26)

#define CRC_CTL_DATFMT_Msk               (0x1ul << CRC_CTL_DATFMT_Pos)

#define CRC_CTL_CHKSFMT_Pos              (27)

#define CRC_CTL_CHKSFMT_Msk              (0x1ul << CRC_CTL_CHKSFMT_Pos)

#define CRC_CTL_DATLEN_Pos               (28)

#define CRC_CTL_DATLEN_Msk               (0x3ul << CRC_CTL_DATLEN_Pos)

#define CRC_CTL_CRCMODE_Pos              (30)

#define CRC_CTL_CRCMODE_Msk              (0x3ul << CRC_CTL_CRCMODE_Pos)

#define CRC_DAT_DATA_Pos                 (0)

#define CRC_DAT_DATA_Msk                 (0xfffffffful << CRC_DAT_DATA_Pos)

#define CRC_SEED_SEED_Pos                (0)

#define CRC_SEED_SEED_Msk                (0xfffffffful << CRC_SEED_SEED_Pos)

#define CRC_CHECKSUM_CHECKSUM_Pos        (0)

#define CRC_CHECKSUM_CHECKSUM_Msk        (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos)        /* CRC_CONST */ /* end of CRC register group */


/*---------------------- External Bus Interface Controller -------------------------*/

typedef struct

{


    __IO uint32_t CTL0;          /* Offset: 0x00  External Bus Interface Bank0 Control Register                      */

    __IO uint32_t TCTL0;         /* Offset: 0x04  External Bus Interface Bank0 Timing Control Register               */

    __I  uint32_t RESERVE0[2];

    __IO uint32_t CTL1;          /* Offset: 0x10  External Bus Interface Bank1 Control Register                      */

    __IO uint32_t TCTL1;         /* Offset: 0x14  External Bus Interface Bank1 Timing Control Register               */


} EBI_T;


#define EBI_CTL0_EN_Pos                  (0)

#define EBI_CTL0_EN_Msk                  (0x1ul << EBI_CTL0_EN_Pos)

#define EBI_CTL0_DW16_Pos                (1)

#define EBI_CTL0_DW16_Msk                (0x1ul << EBI_CTL0_DW16_Pos)

#define EBI_CTL0_CSPOLINV_Pos            (2)

#define EBI_CTL0_CSPOLINV_Msk            (0x1ul << EBI_CTL0_CSPOLINV_Pos)

#define EBI_CTL0_MCLKDIV_Pos             (8)

#define EBI_CTL0_MCLKDIV_Msk             (0x7ul << EBI_CTL0_MCLKDIV_Pos)

#define EBI_CTL0_TALE_Pos                (16)

#define EBI_CTL0_TALE_Msk                (0x7ul << EBI_CTL0_TALE_Pos)

#define EBI_CTL0_WBUFEN_Pos              (24)

#define EBI_CTL0_WBUFEN_Msk              (0x1ul << EBI_CTL0_WBUFEN_Pos)

#define EBI_TCTL0_TACC_Pos               (3)

#define EBI_TCTL0_TACC_Msk               (0x1ful << EBI_TCTL0_TACC_Pos)

#define EBI_TCTL0_TAHD_Pos               (8)

#define EBI_TCTL0_TAHD_Msk               (0x7ul << EBI_TCTL0_TAHD_Pos)

#define EBI_TCTL0_W2X_Pos                (12)

#define EBI_TCTL0_W2X_Msk                (0xful << EBI_TCTL0_W2X_Pos)

#define EBI_TCTL0_RAHDOFF_Pos            (22)

#define EBI_TCTL0_RAHDOFF_Msk            (0x1ul << EBI_TCTL0_RAHDOFF_Pos)

#define EBI_TCTL0_WAHDOFF_Pos            (23)

#define EBI_TCTL0_WAHDOFF_Msk            (0x1ul << EBI_TCTL0_WAHDOFF_Pos)

#define EBI_TCTL0_R2R_Pos                (24)

#define EBI_TCTL0_R2R_Msk                (0xful << EBI_TCTL0_R2R_Pos)

#define EBI_CTL1_EN_Pos                  (0)

#define EBI_CTL1_EN_Msk                  (0x1ul << EBI_CTL1_EN_Pos)

#define EBI_CTL1_DW16_Pos                (1)

#define EBI_CTL1_DW16_Msk                (0x1ul << EBI_CTL1_DW16_Pos)

#define EBI_CTL1_CSPOLINV_Pos            (2)

#define EBI_CTL1_CSPOLINV_Msk            (0x1ul << EBI_CTL1_CSPOLINV_Pos)

#define EBI_CTL1_MCLKDIV_Pos             (8)

#define EBI_CTL1_MCLKDIV_Msk             (0x7ul << EBI_CTL1_MCLKDIV_Pos)

#define EBI_CTL1_TALE_Pos                (16)

#define EBI_CTL1_TALE_Msk                (0x7ul << EBI_CTL1_TALE_Pos)

#define EBI_CTL1_WBUFEN_Pos              (24)

#define EBI_CTL1_WBUFEN_Msk              (0x1ul << EBI_CTL1_WBUFEN_Pos)

#define EBI_TCTL1_TACC_Pos               (3)

#define EBI_TCTL1_TACC_Msk               (0x1ful << EBI_TCTL1_TACC_Pos)

#define EBI_TCTL1_TAHD_Pos               (8)

#define EBI_TCTL1_TAHD_Msk               (0x7ul << EBI_TCTL1_TAHD_Pos)

#define EBI_TCTL1_W2X_Pos                (12)

#define EBI_TCTL1_W2X_Msk                (0xful << EBI_TCTL1_W2X_Pos)

#define EBI_TCTL1_RAHDOFF_Pos            (22)

#define EBI_TCTL1_RAHDOFF_Msk            (0x1ul << EBI_TCTL1_RAHDOFF_Pos)

#define EBI_TCTL1_WAHDOFF_Pos            (23)

#define EBI_TCTL1_WAHDOFF_Msk            (0x1ul << EBI_TCTL1_WAHDOFF_Pos)

#define EBI_TCTL1_R2R_Pos                (24)

#define EBI_TCTL1_R2R_Msk                (0xful << EBI_TCTL1_R2R_Pos)                       /* EBI_CONST */ /* end of EBI register group */


/*---------------------- Flash Memory Controller -------------------------*/

typedef struct

{


    __IO uint32_t ISPCTL;        /* Offset: 0x00  ISP Control Register                                               */

    __IO uint32_t ISPADDR;       /* Offset: 0x04  ISP Address Register                                               */

    __IO uint32_t ISPDAT;        /* Offset: 0x08  ISP Data Register                                                  */

    __IO uint32_t ISPCMD;        /* Offset: 0x0C  ISP CMD Register                                                   */

    __IO uint32_t ISPTRG;        /* Offset: 0x10  ISP Trigger Control Register                                       */

    __I  uint32_t DFBA;          /* Offset: 0x14  Data Flash Base Address                                            */

    __IO uint32_t FTCTL;         /* Offset: 0x18  Flash Access Time Control Register                                 */

    __I  uint32_t RESERVE0[9];

    __IO uint32_t ISPSTS;        /* Offset: 0x40  ISP Status Register                                                */

    __I  uint32_t RESERVE1[15];

    __IO uint32_t MPDAT0;        /* Offset: 0x80  ISP Data0 Register                                                 */

    __IO uint32_t MPDAT1;        /* Offset: 0x84  ISP Data1 Register                                                 */

    __IO uint32_t MPDAT2;        /* Offset: 0x88  ISP Data2 Register                                                 */

    __IO uint32_t MPDAT3;        /* Offset: 0x8C  ISP Data3 Register                                                 */

    __I  uint32_t RESERVE2[12];

    __I  uint32_t MPSTS;         /* Offset: 0xC0  ISP Multi-Program Status Register                                  */

    __I  uint32_t MPADDR;        /* Offset: 0xC4  ISP Multi-Program Address Register                                 */


} FMC_T;


#define FMC_ISPCTL_ISPEN_Pos             (0)

#define FMC_ISPCTL_ISPEN_Msk             (0x1ul << FMC_ISPCTL_ISPEN_Pos)

#define FMC_ISPCTL_BS_Pos                (1)

#define FMC_ISPCTL_BS_Msk                (0x1ul << FMC_ISPCTL_BS_Pos)

#define FMC_ISPCTL_APUEN_Pos             (3)

#define FMC_ISPCTL_APUEN_Msk             (0x1ul << FMC_ISPCTL_APUEN_Pos)

#define FMC_ISPCTL_CFGUEN_Pos            (4)

#define FMC_ISPCTL_CFGUEN_Msk            (0x1ul << FMC_ISPCTL_CFGUEN_Pos)

#define FMC_ISPCTL_LDUEN_Pos             (5)

#define FMC_ISPCTL_LDUEN_Msk             (0x1ul << FMC_ISPCTL_LDUEN_Pos)

#define FMC_ISPCTL_ISPFF_Pos             (6)

#define FMC_ISPCTL_ISPFF_Msk             (0x1ul << FMC_ISPCTL_ISPFF_Pos)

#define FMC_ISPCTL_BL_Pos                (16)

#define FMC_ISPCTL_BL_Msk                (0x1ul << FMC_ISPCTL_BL_Pos)

#define FMC_ISPADDR_ISPADDR_Pos          (0)

#define FMC_ISPADDR_ISPADDR_Msk          (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos)

#define FMC_ISPDAT_ISPDAT_Pos            (0)

#define FMC_ISPDAT_ISPDAT_Msk            (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos)

#define FMC_ISPCMD_CMD_Pos               (0)

#define FMC_ISPCMD_CMD_Msk               (0x7ful << FMC_ISPCMD_CMD_Pos)

#define FMC_ISPTRG_ISPGO_Pos             (0)

#define FMC_ISPTRG_ISPGO_Msk             (0x1ul << FMC_ISPTRG_ISPGO_Pos)

#define FMC_DFBA_DFBA_Pos                (0)

#define FMC_DFBA_DFBA_Msk                (0xfffffffful << FMC_DFBA_DFBA_Pos)

#define FMC_FTCTL_FOM_Pos                (4)

#define FMC_FTCTL_FOM_Msk                (0x7ul << FMC_FTCTL_FOM_Pos)

#define FMC_ISPSTS_ISPBUSY_Pos           (0)

#define FMC_ISPSTS_ISPBUSY_Msk           (0x1ul << FMC_ISPSTS_ISPBUSY_Pos)

#define FMC_ISPSTS_CBS_Pos               (1)

#define FMC_ISPSTS_CBS_Msk               (0x3ul << FMC_ISPSTS_CBS_Pos)

#define FMC_ISPSTS_MBS_Pos               (3)

#define FMC_ISPSTS_MBS_Msk               (0x1ul << FMC_ISPSTS_MBS_Pos)

#define FMC_ISPSTS_PGFF_Pos              (5)

#define FMC_ISPSTS_PGFF_Msk              (0x1ul << FMC_ISPSTS_PGFF_Pos)

#define FMC_ISPSTS_ISPFF_Pos             (6)

#define FMC_ISPSTS_ISPFF_Msk             (0x1ul << FMC_ISPSTS_ISPFF_Pos)

#define FMC_ISPSTS_VECMAP_Pos            (9)

#define FMC_ISPSTS_VECMAP_Msk            (0x7ffful << FMC_ISPSTS_VECMAP_Pos)

#define FMC_MPDAT0_ISPDAT0_Pos           (0)

#define FMC_MPDAT0_ISPDAT0_Msk           (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos)

#define FMC_MPDAT1_ISPDAT1_Pos           (0)

#define FMC_MPDAT1_ISPDAT1_Msk           (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos)

#define FMC_MPDAT2_ISPDAT2_Pos           (0)

#define FMC_MPDAT2_ISPDAT2_Msk           (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos)

#define FMC_MPDAT3_ISPDAT3_Pos           (0)

#define FMC_MPDAT3_ISPDAT3_Msk           (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos)

#define FMC_MPSTS_MPBUSY_Pos             (0)

#define FMC_MPSTS_MPBUSY_Msk             (0x1ul << FMC_MPSTS_MPBUSY_Pos)

#define FMC_MPSTS_PPGO_Pos               (1)

#define FMC_MPSTS_PPGO_Msk               (0x1ul << FMC_MPSTS_PPGO_Pos)

#define FMC_MPSTS_ISPFF_Pos              (2)

#define FMC_MPSTS_ISPFF_Msk              (0x1ul << FMC_MPSTS_ISPFF_Pos)

#define FMC_MPSTS_D0_Pos                 (4)

#define FMC_MPSTS_D0_Msk                 (0x1ul << FMC_MPSTS_D0_Pos)

#define FMC_MPSTS_D1_Pos                 (5)

#define FMC_MPSTS_D1_Msk                 (0x1ul << FMC_MPSTS_D1_Pos)

#define FMC_MPSTS_D2_Pos                 (6)

#define FMC_MPSTS_D2_Msk                 (0x1ul << FMC_MPSTS_D2_Pos)

#define FMC_MPSTS_D3_Pos                 (7)

#define FMC_MPSTS_D3_Msk                 (0x1ul << FMC_MPSTS_D3_Pos)

#define FMC_MPADDR_MPADDR_Pos            (0)

#define FMC_MPADDR_MPADDR_Msk            (0xfffffffful << FMC_MPADDR_MPADDR_Pos)            /* FMC_CONST */ /* end of FMC register group */


/*---------------------- General Purpose Input/Output Controller -------------------------*/

typedef struct

{


    __IO uint32_t MODE;          /* Offset: 0x00/0x40/0x80/0xC0/0x100/0x140  Port A-F I/O Mode Control                       */

    __IO uint32_t DINOFF;        /* Offset: 0x04/0x44/0x84/0xC4/0x104/0x144  Port A-F Digital Input Path Disable Control     */

    __IO uint32_t DOUT;          /* Offset: 0x08/0x48/0x88/0xC8/0x108/0x148  Port A-F Data Output Value                      */

    __IO uint32_t DATMSK;        /* Offset: 0x0C/0x4C/0x8C/0xCC/0x10C/0x14C  Port A-F Data Output Write Mask                 */

    __I  uint32_t PIN;           /* Offset: 0x10/0x50/0x90/0xD0/0x110/0x150  Port A-F Pin Value                              */

    __IO uint32_t DBEN;          /* Offset: 0x14/0x54/0x94/0xD4/0x114/0x154  Port A-F De-Bounce Enable Control Register      */

    __IO uint32_t INTTYPE;       /* Offset: 0x18/0x58/0x98/0xD8/0x118/0x158  Port A-F Interrupt Trigger Type Control         */

    __IO uint32_t INTEN;         /* Offset: 0x1C/0x5C/0x9C/0xDC/0x11C/0x15C  Port A-F Interrupt Enable Control Register      */

    __IO uint32_t INTSRC;        /* Offset: 0x20/0x60/0xA0/0xE0/0x120/0x160  Port A-F Interrupt Source Flag                  */

    __IO uint32_t SMTEN;         /* Offset: 0x24/0x64/0xA4/0xE4/0x124/0x164  Port A-F Input Schmitt Trigger Enable Register  */

    __IO uint32_t SLEWCTL;       /* Offset: 0x28/0x68/0xA8/0xE8/0x128/0x168  Port A-F High Slew Rate Control Register        */

    __IO uint32_t DRVCTL;        /* Offset: 0x12C  Port E High Drive Strength Control Register                               */


} GPIO_T;


typedef struct

{


    __IO uint32_t DBCTL;         /* Offset: 0x440  Interrupt De-bounce Control Register                              */


} GPIO_DBCTL_T;


#define GPIO_MODE_MODE0_Pos              (0)

#define GPIO_MODE_MODE0_Msk              (0x3ul << GPIO_MODE_MODE0_Pos)

#define GPIO_MODE_MODE1_Pos              (2)

#define GPIO_MODE_MODE1_Msk              (0x3ul << GPIO_MODE_MODE1_Pos)

#define GPIO_MODE_MODE2_Pos              (4)

#define GPIO_MODE_MODE2_Msk              (0x3ul << GPIO_MODE_MODE2_Pos)

#define GPIO_MODE_MODE3_Pos              (6)

#define GPIO_MODE_MODE3_Msk              (0x3ul << GPIO_MODE_MODE3_Pos)

#define GPIO_MODE_MODE4_Pos              (8)

#define GPIO_MODE_MODE4_Msk              (0x3ul << GPIO_MODE_MODE4_Pos)

#define GPIO_MODE_MODE5_Pos              (10)

#define GPIO_MODE_MODE5_Msk              (0x3ul << GPIO_MODE_MODE5_Pos)

#define GPIO_MODE_MODE6_Pos              (12)

#define GPIO_MODE_MODE6_Msk              (0x3ul << GPIO_MODE_MODE6_Pos)

#define GPIO_MODE_MODE7_Pos              (14)

#define GPIO_MODE_MODE7_Msk              (0x3ul << GPIO_MODE_MODE7_Pos)

#define GPIO_MODE_MODE8_Pos              (16)

#define GPIO_MODE_MODE8_Msk              (0x3ul << GPIO_MODE_MODE8_Pos)

#define GPIO_MODE_MODE9_Pos              (18)

#define GPIO_MODE_MODE9_Msk              (0x3ul << GPIO_MODE_MODE9_Pos)

#define GPIO_MODE_MODE10_Pos             (20)

#define GPIO_MODE_MODE10_Msk             (0x3ul << GPIO_MODE_MODE10_Pos)

#define GPIO_MODE_MODE11_Pos             (22)

#define GPIO_MODE_MODE11_Msk             (0x3ul << GPIO_MODE_MODE11_Pos)

#define GPIO_MODE_MODE12_Pos             (24)

#define GPIO_MODE_MODE12_Msk             (0x3ul << GPIO_MODE_MODE12_Pos)

#define GPIO_MODE_MODE13_Pos             (26)

#define GPIO_MODE_MODE13_Msk             (0x3ul << GPIO_MODE_MODE13_Pos)

#define GPIO_MODE_MODE14_Pos             (28)

#define GPIO_MODE_MODE14_Msk             (0x3ul << GPIO_MODE_MODE14_Pos)

#define GPIO_MODE_MODE15_Pos             (30)

#define GPIO_MODE_MODE15_Msk             (0x3ul << GPIO_MODE_MODE15_Pos)

#define GPIO_DINOFF_DINOFF0_Pos          (16)

#define GPIO_DINOFF_DINOFF0_Msk          (0x1ul << GPIO_DINOFF_DINOFF0_Pos)

#define GPIO_DINOFF_DINOFF1_Pos          (17)

#define GPIO_DINOFF_DINOFF1_Msk          (0x1ul << GPIO_DINOFF_DINOFF1_Pos)

#define GPIO_DINOFF_DINOFF2_Pos          (18)

#define GPIO_DINOFF_DINOFF2_Msk          (0x1ul << GPIO_DINOFF_DINOFF2_Pos)

#define GPIO_DINOFF_DINOFF3_Pos          (19)

#define GPIO_DINOFF_DINOFF3_Msk          (0x1ul << GPIO_DINOFF_DINOFF3_Pos)

#define GPIO_DINOFF_DINOFF4_Pos          (20)

#define GPIO_DINOFF_DINOFF4_Msk          (0x1ul << GPIO_DINOFF_DINOFF4_Pos)

#define GPIO_DINOFF_DINOFF5_Pos          (21)

#define GPIO_DINOFF_DINOFF5_Msk          (0x1ul << GPIO_DINOFF_DINOFF5_Pos)

#define GPIO_DINOFF_DINOFF6_Pos          (22)

#define GPIO_DINOFF_DINOFF6_Msk          (0x1ul << GPIO_DINOFF_DINOFF6_Pos)

#define GPIO_DINOFF_DINOFF7_Pos          (23)

#define GPIO_DINOFF_DINOFF7_Msk          (0x1ul << GPIO_DINOFF_DINOFF7_Pos)

#define GPIO_DINOFF_DINOFF8_Pos          (24)

#define GPIO_DINOFF_DINOFF8_Msk          (0x1ul << GPIO_DINOFF_DINOFF8_Pos)

#define GPIO_DINOFF_DINOFF9_Pos          (25)

#define GPIO_DINOFF_DINOFF9_Msk          (0x1ul << GPIO_DINOFF_DINOFF9_Pos)

#define GPIO_DINOFF_DINOFF10_Pos         (26)

#define GPIO_DINOFF_DINOFF10_Msk         (0x1ul << GPIO_DINOFF_DINOFF10_Pos)

#define GPIO_DINOFF_DINOFF11_Pos         (27)

#define GPIO_DINOFF_DINOFF11_Msk         (0x1ul << GPIO_DINOFF_DINOFF11_Pos)

#define GPIO_DINOFF_DINOFF12_Pos         (28)

#define GPIO_DINOFF_DINOFF12_Msk         (0x1ul << GPIO_DINOFF_DINOFF12_Pos)

#define GPIO_DINOFF_DINOFF13_Pos         (29)

#define GPIO_DINOFF_DINOFF13_Msk         (0x1ul << GPIO_DINOFF_DINOFF13_Pos)

#define GPIO_DINOFF_DINOFF14_Pos         (30)

#define GPIO_DINOFF_DINOFF14_Msk         (0x1ul << GPIO_DINOFF_DINOFF14_Pos)

#define GPIO_DINOFF_DINOFF15_Pos         (31)

#define GPIO_DINOFF_DINOFF15_Msk         (0x1ul << GPIO_DINOFF_DINOFF15_Pos)

#define GPIO_DOUT_DOUT0_Pos              (0)

#define GPIO_DOUT_DOUT0_Msk              (0x1ul << GPIO_DOUT_DOUT0_Pos)

#define GPIO_DOUT_DOUT1_Pos              (1)

#define GPIO_DOUT_DOUT1_Msk              (0x1ul << GPIO_DOUT_DOUT1_Pos)

#define GPIO_DOUT_DOUT2_Pos              (2)

#define GPIO_DOUT_DOUT2_Msk              (0x1ul << GPIO_DOUT_DOUT2_Pos)

#define GPIO_DOUT_DOUT3_Pos              (3)

#define GPIO_DOUT_DOUT3_Msk              (0x1ul << GPIO_DOUT_DOUT3_Pos)

#define GPIO_DOUT_DOUT4_Pos              (4)

#define GPIO_DOUT_DOUT4_Msk              (0x1ul << GPIO_DOUT_DOUT4_Pos)

#define GPIO_DOUT_DOUT5_Pos              (5)

#define GPIO_DOUT_DOUT5_Msk              (0x1ul << GPIO_DOUT_DOUT5_Pos)

#define GPIO_DOUT_DOUT6_Pos              (6)

#define GPIO_DOUT_DOUT6_Msk              (0x1ul << GPIO_DOUT_DOUT6_Pos)

#define GPIO_DOUT_DOUT7_Pos              (7)

#define GPIO_DOUT_DOUT7_Msk              (0x1ul << GPIO_DOUT_DOUT7_Pos)

#define GPIO_DOUT_DOUT8_Pos              (8)

#define GPIO_DOUT_DOUT8_Msk              (0x1ul << GPIO_DOUT_DOUT8_Pos)

#define GPIO_DOUT_DOUT9_Pos              (9)

#define GPIO_DOUT_DOUT9_Msk              (0x1ul << GPIO_DOUT_DOUT9_Pos)

#define GPIO_DOUT_DOUT10_Pos             (10)

#define GPIO_DOUT_DOUT10_Msk             (0x1ul << GPIO_DOUT_DOUT10_Pos)

#define GPIO_DOUT_DOUT11_Pos             (11)

#define GPIO_DOUT_DOUT11_Msk             (0x1ul << GPIO_DOUT_DOUT11_Pos)

#define GPIO_DOUT_DOUT12_Pos             (12)

#define GPIO_DOUT_DOUT12_Msk             (0x1ul << GPIO_DOUT_DOUT12_Pos)

#define GPIO_DOUT_DOUT13_Pos             (13)

#define GPIO_DOUT_DOUT13_Msk             (0x1ul << GPIO_DOUT_DOUT13_Pos)

#define GPIO_DOUT_DOUT14_Pos             (14)

#define GPIO_DOUT_DOUT14_Msk             (0x1ul << GPIO_DOUT_DOUT14_Pos)

#define GPIO_DOUT_DOUT15_Pos             (15)

#define GPIO_DOUT_DOUT15_Msk             (0x1ul << GPIO_DOUT_DOUT15_Pos)

#define GPIO_DATMSK_DMASK0_Pos           (0)

#define GPIO_DATMSK_DMASK0_Msk           (0x1ul << GPIO_DATMSK_DMASK0_Pos)

#define GPIO_DATMSK_DMASK1_Pos           (1)

#define GPIO_DATMSK_DMASK1_Msk           (0x1ul << GPIO_DATMSK_DMASK1_Pos)

#define GPIO_DATMSK_DMASK2_Pos           (2)

#define GPIO_DATMSK_DMASK2_Msk           (0x1ul << GPIO_DATMSK_DMASK2_Pos)

#define GPIO_DATMSK_DMASK3_Pos           (3)

#define GPIO_DATMSK_DMASK3_Msk           (0x1ul << GPIO_DATMSK_DMASK3_Pos)

#define GPIO_DATMSK_DMASK4_Pos           (4)

#define GPIO_DATMSK_DMASK4_Msk           (0x1ul << GPIO_DATMSK_DMASK4_Pos)

#define GPIO_DATMSK_DMASK5_Pos           (5)

#define GPIO_DATMSK_DMASK5_Msk           (0x1ul << GPIO_DATMSK_DMASK5_Pos)

#define GPIO_DATMSK_DMASK6_Pos           (6)

#define GPIO_DATMSK_DMASK6_Msk           (0x1ul << GPIO_DATMSK_DMASK6_Pos)

#define GPIO_DATMSK_DMASK7_Pos           (7)

#define GPIO_DATMSK_DMASK7_Msk           (0x1ul << GPIO_DATMSK_DMASK7_Pos)

#define GPIO_DATMSK_DMASK8_Pos           (8)

#define GPIO_DATMSK_DMASK8_Msk           (0x1ul << GPIO_DATMSK_DMASK8_Pos)

#define GPIO_DATMSK_DMASK9_Pos           (9)

#define GPIO_DATMSK_DMASK9_Msk           (0x1ul << GPIO_DATMSK_DMASK9_Pos)

#define GPIO_DATMSK_DMASK10_Pos          (10)

#define GPIO_DATMSK_DMASK10_Msk          (0x1ul << GPIO_DATMSK_DMASK10_Pos)

#define GPIO_DATMSK_DMASK11_Pos          (11)

#define GPIO_DATMSK_DMASK11_Msk          (0x1ul << GPIO_DATMSK_DMASK11_Pos)

#define GPIO_DATMSK_DMASK12_Pos          (12)

#define GPIO_DATMSK_DMASK12_Msk          (0x1ul << GPIO_DATMSK_DMASK12_Pos)

#define GPIO_DATMSK_DMASK13_Pos          (13)

#define GPIO_DATMSK_DMASK13_Msk          (0x1ul << GPIO_DATMSK_DMASK13_Pos)

#define GPIO_DATMSK_DMASK14_Pos          (14)

#define GPIO_DATMSK_DMASK14_Msk          (0x1ul << GPIO_DATMSK_DMASK14_Pos)

#define GPIO_DATMSK_DMASK15_Pos          (15)

#define GPIO_DATMSK_DMASK15_Msk          (0x1ul << GPIO_DATMSK_DMASK15_Pos)

#define GPIO_PIN_PIN0_Pos                (0)

#define GPIO_PIN_PIN0_Msk                (0x1ul << GPIO_PIN_PIN0_Pos)

#define GPIO_PIN_PIN1_Pos                (1)

#define GPIO_PIN_PIN1_Msk                (0x1ul << GPIO_PIN_PIN1_Pos)

#define GPIO_PIN_PIN2_Pos                (2)

#define GPIO_PIN_PIN2_Msk                (0x1ul << GPIO_PIN_PIN2_Pos)

#define GPIO_PIN_PIN3_Pos                (3)

#define GPIO_PIN_PIN3_Msk                (0x1ul << GPIO_PIN_PIN3_Pos)

#define GPIO_PIN_PIN4_Pos                (4)

#define GPIO_PIN_PIN4_Msk                (0x1ul << GPIO_PIN_PIN4_Pos)

#define GPIO_PIN_PIN5_Pos                (5)

#define GPIO_PIN_PIN5_Msk                (0x1ul << GPIO_PIN_PIN5_Pos)

#define GPIO_PIN_PIN6_Pos                (6)

#define GPIO_PIN_PIN6_Msk                (0x1ul << GPIO_PIN_PIN6_Pos)

#define GPIO_PIN_PIN7_Pos                (7)

#define GPIO_PIN_PIN7_Msk                (0x1ul << GPIO_PIN_PIN7_Pos)

#define GPIO_PIN_PIN8_Pos                (8)

#define GPIO_PIN_PIN8_Msk                (0x1ul << GPIO_PIN_PIN8_Pos)

#define GPIO_PIN_PIN9_Pos                (9)

#define GPIO_PIN_PIN9_Msk                (0x1ul << GPIO_PIN_PIN9_Pos)

#define GPIO_PIN_PIN10_Pos               (10)

#define GPIO_PIN_PIN10_Msk               (0x1ul << GPIO_PIN_PIN10_Pos)

#define GPIO_PIN_PIN11_Pos               (11)

#define GPIO_PIN_PIN11_Msk               (0x1ul << GPIO_PIN_PIN11_Pos)

#define GPIO_PIN_PIN12_Pos               (12)

#define GPIO_PIN_PIN12_Msk               (0x1ul << GPIO_PIN_PIN12_Pos)

#define GPIO_PIN_PIN13_Pos               (13)

#define GPIO_PIN_PIN13_Msk               (0x1ul << GPIO_PIN_PIN13_Pos)

#define GPIO_PIN_PIN14_Pos               (14)

#define GPIO_PIN_PIN14_Msk               (0x1ul << GPIO_PIN_PIN14_Pos)

#define GPIO_PIN_PIN15_Pos               (15)

#define GPIO_PIN_PIN15_Msk               (0x1ul << GPIO_PIN_PIN15_Pos)

#define GPIO_DBEN_DBEN0_Pos              (0)

#define GPIO_DBEN_DBEN0_Msk              (0x1ul << GPIO_DBEN_DBEN0_Pos)

#define GPIO_DBEN_DBEN1_Pos              (1)

#define GPIO_DBEN_DBEN1_Msk              (0x1ul << GPIO_DBEN_DBEN1_Pos)

#define GPIO_DBEN_DBEN2_Pos              (2)

#define GPIO_DBEN_DBEN2_Msk              (0x1ul << GPIO_DBEN_DBEN2_Pos)

#define GPIO_DBEN_DBEN3_Pos              (3)

#define GPIO_DBEN_DBEN3_Msk              (0x1ul << GPIO_DBEN_DBEN3_Pos)

#define GPIO_DBEN_DBEN4_Pos              (4)

#define GPIO_DBEN_DBEN4_Msk              (0x1ul << GPIO_DBEN_DBEN4_Pos)

#define GPIO_DBEN_DBEN5_Pos              (5)

#define GPIO_DBEN_DBEN5_Msk              (0x1ul << GPIO_DBEN_DBEN5_Pos)

#define GPIO_DBEN_DBEN6_Pos              (6)

#define GPIO_DBEN_DBEN6_Msk              (0x1ul << GPIO_DBEN_DBEN6_Pos)

#define GPIO_DBEN_DBEN7_Pos              (7)

#define GPIO_DBEN_DBEN7_Msk              (0x1ul << GPIO_DBEN_DBEN7_Pos)

#define GPIO_DBEN_DBEN8_Pos              (8)

#define GPIO_DBEN_DBEN8_Msk              (0x1ul << GPIO_DBEN_DBEN8_Pos)

#define GPIO_DBEN_DBEN9_Pos              (9)

#define GPIO_DBEN_DBEN9_Msk              (0x1ul << GPIO_DBEN_DBEN9_Pos)

#define GPIO_DBEN_DBEN10_Pos             (10)

#define GPIO_DBEN_DBEN10_Msk             (0x1ul << GPIO_DBEN_DBEN10_Pos)

#define GPIO_DBEN_DBEN11_Pos             (11)

#define GPIO_DBEN_DBEN11_Msk             (0x1ul << GPIO_DBEN_DBEN11_Pos)

#define GPIO_DBEN_DBEN12_Pos             (12)

#define GPIO_DBEN_DBEN12_Msk             (0x1ul << GPIO_DBEN_DBEN12_Pos)

#define GPIO_DBEN_DBEN13_Pos             (13)

#define GPIO_DBEN_DBEN13_Msk             (0x1ul << GPIO_DBEN_DBEN13_Pos)

#define GPIO_DBEN_DBEN14_Pos             (14)

#define GPIO_DBEN_DBEN14_Msk             (0x1ul << GPIO_DBEN_DBEN14_Pos)

#define GPIO_DBEN_DBEN15_Pos             (15)

#define GPIO_DBEN_DBEN15_Msk             (0x1ul << GPIO_DBEN_DBEN15_Pos)

#define GPIO_INTTYPE_TYPE0_Pos           (0)

#define GPIO_INTTYPE_TYPE0_Msk           (0x1ul << GPIO_INTTYPE_TYPE0_Pos)

#define GPIO_INTTYPE_TYPE1_Pos           (1)

#define GPIO_INTTYPE_TYPE1_Msk           (0x1ul << GPIO_INTTYPE_TYPE1_Pos)

#define GPIO_INTTYPE_TYPE2_Pos           (2)

#define GPIO_INTTYPE_TYPE2_Msk           (0x1ul << GPIO_INTTYPE_TYPE2_Pos)

#define GPIO_INTTYPE_TYPE3_Pos           (3)

#define GPIO_INTTYPE_TYPE3_Msk           (0x1ul << GPIO_INTTYPE_TYPE3_Pos)

#define GPIO_INTTYPE_TYPE4_Pos           (4)

#define GPIO_INTTYPE_TYPE4_Msk           (0x1ul << GPIO_INTTYPE_TYPE4_Pos)

#define GPIO_INTTYPE_TYPE5_Pos           (5)

#define GPIO_INTTYPE_TYPE5_Msk           (0x1ul << GPIO_INTTYPE_TYPE5_Pos)

#define GPIO_INTTYPE_TYPE6_Pos           (6)

#define GPIO_INTTYPE_TYPE6_Msk           (0x1ul << GPIO_INTTYPE_TYPE6_Pos)

#define GPIO_INTTYPE_TYPE7_Pos           (7)

#define GPIO_INTTYPE_TYPE7_Msk           (0x1ul << GPIO_INTTYPE_TYPE7_Pos)

#define GPIO_INTTYPE_TYPE8_Pos           (8)

#define GPIO_INTTYPE_TYPE8_Msk           (0x1ul << GPIO_INTTYPE_TYPE8_Pos)

#define GPIO_INTTYPE_TYPE9_Pos           (9)

#define GPIO_INTTYPE_TYPE9_Msk           (0x1ul << GPIO_INTTYPE_TYPE9_Pos)

#define GPIO_INTTYPE_TYPE10_Pos          (10)

#define GPIO_INTTYPE_TYPE10_Msk          (0x1ul << GPIO_INTTYPE_TYPE10_Pos)

#define GPIO_INTTYPE_TYPE11_Pos          (11)

#define GPIO_INTTYPE_TYPE11_Msk          (0x1ul << GPIO_INTTYPE_TYPE11_Pos)

#define GPIO_INTTYPE_TYPE12_Pos          (12)

#define GPIO_INTTYPE_TYPE12_Msk          (0x1ul << GPIO_INTTYPE_TYPE12_Pos)

#define GPIO_INTTYPE_TYPE13_Pos          (13)

#define GPIO_INTTYPE_TYPE13_Msk          (0x1ul << GPIO_INTTYPE_TYPE13_Pos)

#define GPIO_INTTYPE_TYPE14_Pos          (14)

#define GPIO_INTTYPE_TYPE14_Msk          (0x1ul << GPIO_INTTYPE_TYPE14_Pos)

#define GPIO_INTTYPE_TYPE15_Pos          (15)

#define GPIO_INTTYPE_TYPE15_Msk          (0x1ul << GPIO_INTTYPE_TYPE15_Pos)

#define GPIO_INTEN_FLIEN0_Pos            (0)

#define GPIO_INTEN_FLIEN0_Msk            (0x1ul << GPIO_INTEN_FLIEN0_Pos)

#define GPIO_INTEN_FLIEN1_Pos            (1)

#define GPIO_INTEN_FLIEN1_Msk            (0x1ul << GPIO_INTEN_FLIEN1_Pos)

#define GPIO_INTEN_FLIEN2_Pos            (2)

#define GPIO_INTEN_FLIEN2_Msk            (0x1ul << GPIO_INTEN_FLIEN2_Pos)

#define GPIO_INTEN_FLIEN3_Pos            (3)

#define GPIO_INTEN_FLIEN3_Msk            (0x1ul << GPIO_INTEN_FLIEN3_Pos)

#define GPIO_INTEN_FLIEN4_Pos            (4)

#define GPIO_INTEN_FLIEN4_Msk            (0x1ul << GPIO_INTEN_FLIEN4_Pos)

#define GPIO_INTEN_FLIEN5_Pos            (5)

#define GPIO_INTEN_FLIEN5_Msk            (0x1ul << GPIO_INTEN_FLIEN5_Pos)

#define GPIO_INTEN_FLIEN6_Pos            (6)

#define GPIO_INTEN_FLIEN6_Msk            (0x1ul << GPIO_INTEN_FLIEN6_Pos)

#define GPIO_INTEN_FLIEN7_Pos            (7)

#define GPIO_INTEN_FLIEN7_Msk            (0x1ul << GPIO_INTEN_FLIEN7_Pos)

#define GPIO_INTEN_FLIEN8_Pos            (8)

#define GPIO_INTEN_FLIEN8_Msk            (0x1ul << GPIO_INTEN_FLIEN8_Pos)

#define GPIO_INTEN_FLIEN9_Pos            (9)

#define GPIO_INTEN_FLIEN9_Msk            (0x1ul << GPIO_INTEN_FLIEN9_Pos)

#define GPIO_INTEN_FLIEN10_Pos           (10)

#define GPIO_INTEN_FLIEN10_Msk           (0x1ul << GPIO_INTEN_FLIEN10_Pos)

#define GPIO_INTEN_FLIEN11_Pos           (11)

#define GPIO_INTEN_FLIEN11_Msk           (0x1ul << GPIO_INTEN_FLIEN11_Pos)

#define GPIO_INTEN_FLIEN12_Pos           (12)

#define GPIO_INTEN_FLIEN12_Msk           (0x1ul << GPIO_INTEN_FLIEN12_Pos)

#define GPIO_INTEN_FLIEN13_Pos           (13)

#define GPIO_INTEN_FLIEN13_Msk           (0x1ul << GPIO_INTEN_FLIEN13_Pos)

#define GPIO_INTEN_FLIEN14_Pos           (14)

#define GPIO_INTEN_FLIEN14_Msk           (0x1ul << GPIO_INTEN_FLIEN14_Pos)

#define GPIO_INTEN_FLIEN15_Pos           (15)

#define GPIO_INTEN_FLIEN15_Msk           (0x1ul << GPIO_INTEN_FLIEN15_Pos)

#define GPIO_INTEN_RHIEN0_Pos            (16)

#define GPIO_INTEN_RHIEN0_Msk            (0x1ul << GPIO_INTEN_RHIEN0_Pos)

#define GPIO_INTEN_RHIEN1_Pos            (17)

#define GPIO_INTEN_RHIEN1_Msk            (0x1ul << GPIO_INTEN_RHIEN1_Pos)

#define GPIO_INTEN_RHIEN2_Pos            (18)

#define GPIO_INTEN_RHIEN2_Msk            (0x1ul << GPIO_INTEN_RHIEN2_Pos)

#define GPIO_INTEN_RHIEN3_Pos            (19)

#define GPIO_INTEN_RHIEN3_Msk            (0x1ul << GPIO_INTEN_RHIEN3_Pos)

#define GPIO_INTEN_RHIEN4_Pos            (20)

#define GPIO_INTEN_RHIEN4_Msk            (0x1ul << GPIO_INTEN_RHIEN4_Pos)

#define GPIO_INTEN_RHIEN5_Pos            (21)

#define GPIO_INTEN_RHIEN5_Msk            (0x1ul << GPIO_INTEN_RHIEN5_Pos)

#define GPIO_INTEN_RHIEN6_Pos            (22)

#define GPIO_INTEN_RHIEN6_Msk            (0x1ul << GPIO_INTEN_RHIEN6_Pos)

#define GPIO_INTEN_RHIEN7_Pos            (23)

#define GPIO_INTEN_RHIEN7_Msk            (0x1ul << GPIO_INTEN_RHIEN7_Pos)

#define GPIO_INTEN_RHIEN8_Pos            (24)

#define GPIO_INTEN_RHIEN8_Msk            (0x1ul << GPIO_INTEN_RHIEN8_Pos)

#define GPIO_INTEN_RHIEN9_Pos            (25)

#define GPIO_INTEN_RHIEN9_Msk            (0x1ul << GPIO_INTEN_RHIEN9_Pos)

#define GPIO_INTEN_RHIEN10_Pos           (26)

#define GPIO_INTEN_RHIEN10_Msk           (0x1ul << GPIO_INTEN_RHIEN10_Pos)

#define GPIO_INTEN_RHIEN11_Pos           (27)

#define GPIO_INTEN_RHIEN11_Msk           (0x1ul << GPIO_INTEN_RHIEN11_Pos)

#define GPIO_INTEN_RHIEN12_Pos           (28)

#define GPIO_INTEN_RHIEN12_Msk           (0x1ul << GPIO_INTEN_RHIEN12_Pos)

#define GPIO_INTEN_RHIEN13_Pos           (29)

#define GPIO_INTEN_RHIEN13_Msk           (0x1ul << GPIO_INTEN_RHIEN13_Pos)

#define GPIO_INTEN_RHIEN14_Pos           (30)

#define GPIO_INTEN_RHIEN14_Msk           (0x1ul << GPIO_INTEN_RHIEN14_Pos)

#define GPIO_INTEN_RHIEN15_Pos           (31)

#define GPIO_INTEN_RHIEN15_Msk           (0x1ul << GPIO_INTEN_RHIEN15_Pos)

#define GPIO_INTSRC_INTSRC0_Pos          (0)

#define GPIO_INTSRC_INTSRC0_Msk          (0x1ul << GPIO_INTSRC_INTSRC0_Pos)

#define GPIO_INTSRC_INTSRC1_Pos          (1)

#define GPIO_INTSRC_INTSRC1_Msk          (0x1ul << GPIO_INTSRC_INTSRC1_Pos)

#define GPIO_INTSRC_INTSRC2_Pos          (2)

#define GPIO_INTSRC_INTSRC2_Msk          (0x1ul << GPIO_INTSRC_INTSRC2_Pos)

#define GPIO_INTSRC_INTSRC3_Pos          (3)

#define GPIO_INTSRC_INTSRC3_Msk          (0x1ul << GPIO_INTSRC_INTSRC3_Pos)

#define GPIO_INTSRC_INTSRC4_Pos          (4)

#define GPIO_INTSRC_INTSRC4_Msk          (0x1ul << GPIO_INTSRC_INTSRC4_Pos)

#define GPIO_INTSRC_INTSRC5_Pos          (5)

#define GPIO_INTSRC_INTSRC5_Msk          (0x1ul << GPIO_INTSRC_INTSRC5_Pos)

#define GPIO_INTSRC_INTSRC6_Pos          (6)

#define GPIO_INTSRC_INTSRC6_Msk          (0x1ul << GPIO_INTSRC_INTSRC6_Pos)

#define GPIO_INTSRC_INTSRC7_Pos          (7)

#define GPIO_INTSRC_INTSRC7_Msk          (0x1ul << GPIO_INTSRC_INTSRC7_Pos)

#define GPIO_INTSRC_INTSRC8_Pos          (8)

#define GPIO_INTSRC_INTSRC8_Msk          (0x1ul << GPIO_INTSRC_INTSRC8_Pos)

#define GPIO_INTSRC_INTSRC9_Pos          (9)

#define GPIO_INTSRC_INTSRC9_Msk          (0x1ul << GPIO_INTSRC_INTSRC9_Pos)

#define GPIO_INTSRC_INTSRC10_Pos         (10)

#define GPIO_INTSRC_INTSRC10_Msk         (0x1ul << GPIO_INTSRC_INTSRC10_Pos)

#define GPIO_INTSRC_INTSRC11_Pos         (11)

#define GPIO_INTSRC_INTSRC11_Msk         (0x1ul << GPIO_INTSRC_INTSRC11_Pos)

#define GPIO_INTSRC_INTSRC12_Pos         (12)

#define GPIO_INTSRC_INTSRC12_Msk         (0x1ul << GPIO_INTSRC_INTSRC12_Pos)

#define GPIO_INTSRC_INTSRC13_Pos         (13)

#define GPIO_INTSRC_INTSRC13_Msk         (0x1ul << GPIO_INTSRC_INTSRC13_Pos)

#define GPIO_INTSRC_INTSRC14_Pos         (14)

#define GPIO_INTSRC_INTSRC14_Msk         (0x1ul << GPIO_INTSRC_INTSRC14_Pos)

#define GPIO_INTSRC_INTSRC15_Pos         (15)

#define GPIO_INTSRC_INTSRC15_Msk         (0x1ul << GPIO_INTSRC_INTSRC15_Pos)

#define GPIO_SMTEN_SMTEN0_Pos            (0)

#define GPIO_SMTEN_SMTEN0_Msk            (0x1ul << GPIO_SMTEN_SMTEN0_Pos)

#define GPIO_SMTEN_SMTEN1_Pos            (1)

#define GPIO_SMTEN_SMTEN1_Msk            (0x1ul << GPIO_SMTEN_SMTEN1_Pos)

#define GPIO_SMTEN_SMTEN2_Pos            (2)

#define GPIO_SMTEN_SMTEN2_Msk            (0x1ul << GPIO_SMTEN_SMTEN2_Pos)

#define GPIO_SMTEN_SMTEN3_Pos            (3)

#define GPIO_SMTEN_SMTEN3_Msk            (0x1ul << GPIO_SMTEN_SMTEN3_Pos)

#define GPIO_SMTEN_SMTEN4_Pos            (4)

#define GPIO_SMTEN_SMTEN4_Msk            (0x1ul << GPIO_SMTEN_SMTEN4_Pos)

#define GPIO_SMTEN_SMTEN5_Pos            (5)

#define GPIO_SMTEN_SMTEN5_Msk            (0x1ul << GPIO_SMTEN_SMTEN5_Pos)

#define GPIO_SMTEN_SMTEN6_Pos            (6)

#define GPIO_SMTEN_SMTEN6_Msk            (0x1ul << GPIO_SMTEN_SMTEN6_Pos)

#define GPIO_SMTEN_SMTEN7_Pos            (7)

#define GPIO_SMTEN_SMTEN7_Msk            (0x1ul << GPIO_SMTEN_SMTEN7_Pos)

#define GPIO_SMTEN_SMTEN8_Pos            (8)

#define GPIO_SMTEN_SMTEN8_Msk            (0x1ul << GPIO_SMTEN_SMTEN8_Pos)

#define GPIO_SMTEN_SMTEN9_Pos            (9)

#define GPIO_SMTEN_SMTEN9_Msk            (0x1ul << GPIO_SMTEN_SMTEN9_Pos)

#define GPIO_SMTEN_SMTEN10_Pos           (10)

#define GPIO_SMTEN_SMTEN10_Msk           (0x1ul << GPIO_SMTEN_SMTEN10_Pos)

#define GPIO_SMTEN_SMTEN11_Pos           (11)

#define GPIO_SMTEN_SMTEN11_Msk           (0x1ul << GPIO_SMTEN_SMTEN11_Pos)

#define GPIO_SMTEN_SMTEN12_Pos           (12)

#define GPIO_SMTEN_SMTEN12_Msk           (0x1ul << GPIO_SMTEN_SMTEN12_Pos)

#define GPIO_SMTEN_SMTEN13_Pos           (13)

#define GPIO_SMTEN_SMTEN13_Msk           (0x1ul << GPIO_SMTEN_SMTEN13_Pos)

#define GPIO_SMTEN_SMTEN14_Pos           (14)

#define GPIO_SMTEN_SMTEN14_Msk           (0x1ul << GPIO_SMTEN_SMTEN14_Pos)

#define GPIO_SMTEN_SMTEN15_Pos           (15)

#define GPIO_SMTEN_SMTEN15_Msk           (0x1ul << GPIO_SMTEN_SMTEN15_Pos)

#define GPIO_SLEWCTL_HSREN0_Pos          (0)

#define GPIO_SLEWCTL_HSREN0_Msk          (0x1ul << GPIO_SLEWCTL_HSREN0_Pos)

#define GPIO_SLEWCTL_HSREN1_Pos          (1)

#define GPIO_SLEWCTL_HSREN1_Msk          (0x1ul << GPIO_SLEWCTL_HSREN1_Pos)

#define GPIO_SLEWCTL_HSREN2_Pos          (2)

#define GPIO_SLEWCTL_HSREN2_Msk          (0x1ul << GPIO_SLEWCTL_HSREN2_Pos)

#define GPIO_SLEWCTL_HSREN3_Pos          (3)

#define GPIO_SLEWCTL_HSREN3_Msk          (0x1ul << GPIO_SLEWCTL_HSREN3_Pos)

#define GPIO_SLEWCTL_HSREN4_Pos          (4)

#define GPIO_SLEWCTL_HSREN4_Msk          (0x1ul << GPIO_SLEWCTL_HSREN4_Pos)

#define GPIO_SLEWCTL_HSREN5_Pos          (5)

#define GPIO_SLEWCTL_HSREN5_Msk          (0x1ul << GPIO_SLEWCTL_HSREN5_Pos)

#define GPIO_SLEWCTL_HSREN6_Pos          (6)

#define GPIO_SLEWCTL_HSREN6_Msk          (0x1ul << GPIO_SLEWCTL_HSREN6_Pos)

#define GPIO_SLEWCTL_HSREN7_Pos          (7)

#define GPIO_SLEWCTL_HSREN7_Msk          (0x1ul << GPIO_SLEWCTL_HSREN7_Pos)

#define GPIO_SLEWCTL_HSREN8_Pos          (8)

#define GPIO_SLEWCTL_HSREN8_Msk          (0x1ul << GPIO_SLEWCTL_HSREN8_Pos)

#define GPIO_SLEWCTL_HSREN9_Pos          (9)

#define GPIO_SLEWCTL_HSREN9_Msk          (0x1ul << GPIO_SLEWCTL_HSREN9_Pos)

#define GPIO_SLEWCTL_HSREN10_Pos         (10)

#define GPIO_SLEWCTL_HSREN10_Msk         (0x1ul << GPIO_SLEWCTL_HSREN10_Pos)

#define GPIO_SLEWCTL_HSREN11_Pos         (11)

#define GPIO_SLEWCTL_HSREN11_Msk         (0x1ul << GPIO_SLEWCTL_HSREN11_Pos)

#define GPIO_SLEWCTL_HSREN12_Pos         (12)

#define GPIO_SLEWCTL_HSREN12_Msk         (0x1ul << GPIO_SLEWCTL_HSREN12_Pos)

#define GPIO_SLEWCTL_HSREN13_Pos         (13)

#define GPIO_SLEWCTL_HSREN13_Msk         (0x1ul << GPIO_SLEWCTL_HSREN13_Pos)

#define GPIO_SLEWCTL_HSREN14_Pos         (14)

#define GPIO_SLEWCTL_HSREN14_Msk         (0x1ul << GPIO_SLEWCTL_HSREN14_Pos)

#define GPIO_SLEWCTL_HSREN15_Pos         (15)

#define GPIO_SLEWCTL_HSREN15_Msk         (0x1ul << GPIO_SLEWCTL_HSREN15_Pos)

#define GPIO_DRVCTL_HDRVEN8_Pos          (8)

#define GPIO_DRVCTL_HDRVEN8_Msk          (0x1ul << GPIO_DRVCTL_HDRVEN8_Pos)

#define GPIO_DRVCTL_HDRVEN9_Pos          (9)

#define GPIO_DRVCTL_HDRVEN9_Msk          (0x1ul << GPIO_DRVCTL_HDRVEN9_Pos)

#define GPIO_DRVCTL_HDRVEN10_Pos         (10)

#define GPIO_DRVCTL_HDRVEN10_Msk         (0x1ul << GPIO_DRVCTL_HDRVEN10_Pos)

#define GPIO_DRVCTL_HDRVEN11_Pos         (11)

#define GPIO_DRVCTL_HDRVEN11_Msk         (0x1ul << GPIO_DRVCTL_HDRVEN11_Pos)

#define GPIO_DRVCTL_HDRVEN12_Pos         (12)

#define GPIO_DRVCTL_HDRVEN12_Msk         (0x1ul << GPIO_DRVCTL_HDRVEN12_Pos)

#define GPIO_DRVCTL_HDRVEN13_Pos         (13)

#define GPIO_DRVCTL_HDRVEN13_Msk         (0x1ul << GPIO_DRVCTL_HDRVEN13_Pos)

#define GPIO_DBCTL_DBCLKSEL_Pos          (0)

#define GPIO_DBCTL_DBCLKSEL_Msk          (0xFul << GPIO_DBCTL_DBCLKSEL_Pos)

#define GPIO_DBCTL_DBCLKSRC_Pos          (4)

#define GPIO_DBCTL_DBCLKSRC_Msk          (1ul << GPIO_DBCTL_DBCLKSRC_Pos)

#define GPIO_DBCTL_ICLKON_Pos            (5)

#define GPIO_DBCTL_ICLKON_Msk            (1ul << GPIO_DBCTL_ICLKON_Pos)                     /* GPIO_CONST */ /* end of GPIO register group */


/*---------------------- Inter-IC Bus Controller -------------------------*/

typedef struct

{


    __IO uint32_t CTL;           /* Offset: 0x00  I2C Control Register                                               */

    __IO uint32_t ADDR0;         /* Offset: 0x04  I2C Slave Address Register0                                        */

    __IO uint32_t DAT;           /* Offset: 0x08  I2C Data Register                                                  */

    __I  uint32_t STATUS;        /* Offset: 0x0C  I2C Status Register                                                */

    __IO uint32_t CLKDIV;        /* Offset: 0x10  I2C Clock Divided Register                                         */

    __IO uint32_t TOCTL;         /* Offset: 0x14  I2C Time-out Control Register                                      */

    __IO uint32_t ADDR1;         /* Offset: 0x18  I2C Slave Address Register1                                        */

    __IO uint32_t ADDR2;         /* Offset: 0x1C  I2C Slave Address Register2                                        */

    __IO uint32_t ADDR3;         /* Offset: 0x20  I2C Slave Address Register3                                        */

    __IO uint32_t ADDRMSK0;      /* Offset: 0x24  I2C Slave Address Mask Register0                                   */

    __IO uint32_t ADDRMSK1;      /* Offset: 0x28  I2C Slave Address Mask Register1                                   */

    __IO uint32_t ADDRMSK2;      /* Offset: 0x2C  I2C Slave Address Mask Register2                                   */

    __IO uint32_t ADDRMSK3;      /* Offset: 0x30  I2C Slave Address Mask Register3                                   */

    __I  uint32_t RESERVE0[2];

    __IO uint32_t WKCTL;         /* Offset: 0x3C  I2C Wake-up Control Register                                       */

    __IO uint32_t WKSTS;         /* Offset: 0x40  I2C Wake-up Status Register                                        */

    __IO uint32_t BUSCTL;        /* Offset: 0x44  I2C Bus Management Control Register                                */

    __IO uint32_t BUSTCTL;       /* Offset: 0x48  I2C Bus Management Timer Control Register                          */

    __IO uint32_t BUSSTS;        /* Offset: 0x4C  I2C Bus Management Status Register                                 */

    __IO uint32_t PKTSIZE;       /* Offset: 0x50  I2C Packet Error Checking Byte Number Register                     */

    __I  uint32_t PKTCRC;        /* Offset: 0x54  I2C Packet Error Checking Byte Value Register                      */

    __IO uint32_t BUSTOUT;       /* Offset: 0x58  I2C Bus Management Timer Register                                  */

    __IO uint32_t CLKTOUT;       /* Offset: 0x5C  I2C Bus Management Clock Low Timer Register                        */


} I2C_T;


#define I2C_CTL_AA_Pos                   (2)

#define I2C_CTL_AA_Msk                   (0x1ul << I2C_CTL_AA_Pos)

#define I2C_CTL_SI_Pos                   (3)

#define I2C_CTL_SI_Msk                   (0x1ul << I2C_CTL_SI_Pos)

#define I2C_CTL_STO_Pos                  (4)

#define I2C_CTL_STO_Msk                  (0x1ul << I2C_CTL_STO_Pos)

#define I2C_CTL_STA_Pos                  (5)

#define I2C_CTL_STA_Msk                  (0x1ul << I2C_CTL_STA_Pos)

#define I2C_CTL_I2CEN_Pos                (6)

#define I2C_CTL_I2CEN_Msk                (0x1ul << I2C_CTL_I2CEN_Pos)

#define I2C_CTL_INTEN_Pos                (7)

#define I2C_CTL_INTEN_Msk                (0x1ul << I2C_CTL_INTEN_Pos)

#define I2C_ADDR0_GC_Pos                 (0)

#define I2C_ADDR0_GC_Msk                 (0x1ul << I2C_ADDR0_GC_Pos)

#define I2C_ADDR0_ADDR_Pos               (1)

#define I2C_ADDR0_ADDR_Msk               (0x7ful << I2C_ADDR0_ADDR_Pos)

#define I2C_DAT_DAT_Pos                  (0)

#define I2C_DAT_DAT_Msk                  (0xfful << I2C_DAT_DAT_Pos)

#define I2C_STATUS_STATUS_Pos            (0)

#define I2C_STATUS_STATUS_Msk            (0xfful << I2C_STATUS_STATUS_Pos)

#define I2C_CLKDIV_DIVIDER_Pos           (0)

#define I2C_CLKDIV_DIVIDER_Msk           (0xfful << I2C_CLKDIV_DIVIDER_Pos)

#define I2C_TOCTL_TOIF_Pos               (0)

#define I2C_TOCTL_TOIF_Msk               (0x1ul << I2C_TOCTL_TOIF_Pos)

#define I2C_TOCTL_TOCDIV4_Pos            (1)

#define I2C_TOCTL_TOCDIV4_Msk            (0x1ul << I2C_TOCTL_TOCDIV4_Pos)

#define I2C_TOCTL_TOCEN_Pos              (2)

#define I2C_TOCTL_TOCEN_Msk              (0x1ul << I2C_TOCTL_TOCEN_Pos)

#define I2C_ADDR1_GC_Pos                 (0)

#define I2C_ADDR1_GC_Msk                 (0x1ul << I2C_ADDR1_GC_Pos)

#define I2C_ADDR1_ADDR_Pos               (1)

#define I2C_ADDR1_ADDR_Msk               (0x7ful << I2C_ADDR1_ADDR_Pos)

#define I2C_ADDR2_GC_Pos                 (0)

#define I2C_ADDR2_GC_Msk                 (0x1ul << I2C_ADDR2_GC_Pos)

#define I2C_ADDR2_ADDR_Pos               (1)

#define I2C_ADDR2_ADDR_Msk               (0x7ful << I2C_ADDR2_ADDR_Pos)

#define I2C_ADDR3_GC_Pos                 (0)

#define I2C_ADDR3_GC_Msk                 (0x1ul << I2C_ADDR3_GC_Pos)

#define I2C_ADDR3_ADDR_Pos               (1)

#define I2C_ADDR3_ADDR_Msk               (0x7ful << I2C_ADDR3_ADDR_Pos)

#define I2C_ADDRMSK0_ADDRMSK_Pos         (1)

#define I2C_ADDRMSK0_ADDRMSK_Msk         (0x7ful << I2C_ADDRMSK0_ADDRMSK_Pos)

#define I2C_ADDRMSK1_ADDRMSK_Pos         (1)

#define I2C_ADDRMSK1_ADDRMSK_Msk         (0x7ful << I2C_ADDRMSK1_ADDRMSK_Pos)

#define I2C_ADDRMSK2_ADDRMSK_Pos         (1)

#define I2C_ADDRMSK2_ADDRMSK_Msk         (0x7ful << I2C_ADDRMSK2_ADDRMSK_Pos)

#define I2C_ADDRMSK3_ADDRMSK_Pos         (1)

#define I2C_ADDRMSK3_ADDRMSK_Msk         (0x7ful << I2C_ADDRMSK3_ADDRMSK_Pos)

#define I2C_WKCTL_WKEN_Pos               (0)

#define I2C_WKCTL_WKEN_Msk               (0x1ul << I2C_WKCTL_WKEN_Pos)

#define I2C_WKSTS_WKIF_Pos               (0)

#define I2C_WKSTS_WKIF_Msk               (0x1ul << I2C_WKSTS_WKIF_Pos)

#define I2C_BUSCTL_ACKMEN_Pos            (0)

#define I2C_BUSCTL_ACKMEN_Msk            (0x1ul << I2C_BUSCTL_ACKMEN_Pos)

#define I2C_BUSCTL_PECEN_Pos             (1)

#define I2C_BUSCTL_PECEN_Msk             (0x1ul << I2C_BUSCTL_PECEN_Pos)

#define I2C_BUSCTL_BMDEN_Pos             (2)

#define I2C_BUSCTL_BMDEN_Msk             (0x1ul << I2C_BUSCTL_BMDEN_Pos)

#define I2C_BUSCTL_BMHEN_Pos             (3)

#define I2C_BUSCTL_BMHEN_Msk             (0x1ul << I2C_BUSCTL_BMHEN_Pos)

#define I2C_BUSCTL_ALERTEN_Pos           (4)

#define I2C_BUSCTL_ALERTEN_Msk           (0x1ul << I2C_BUSCTL_ALERTEN_Pos)

#define I2C_BUSCTL_SCTLOSTS_Pos          (5)

#define I2C_BUSCTL_SCTLOSTS_Msk          (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos)

#define I2C_BUSCTL_SCTLOEN_Pos           (6)

#define I2C_BUSCTL_SCTLOEN_Msk           (0x1ul << I2C_BUSCTL_SCTLOEN_Pos)

#define I2C_BUSCTL_BUSEN_Pos             (7)

#define I2C_BUSCTL_BUSEN_Msk             (0x1ul << I2C_BUSCTL_BUSEN_Pos)

#define I2C_BUSCTL_PECTXEN_Pos           (8)

#define I2C_BUSCTL_PECTXEN_Msk           (0x1ul << I2C_BUSCTL_PECTXEN_Pos)

#define I2C_BUSCTL_TIDLE_Pos             (9)

#define I2C_BUSCTL_TIDLE_Msk             (0x1ul << I2C_BUSCTL_TIDLE_Pos)

#define I2C_BUSCTL_PECCLR_Pos            (10)

#define I2C_BUSCTL_PECCLR_Msk            (0x1ul << I2C_BUSCTL_PECCLR_Pos)

#define I2C_BUSCTL_ACKM9SI_Pos           (11)

#define I2C_BUSCTL_ACKM9SI_Msk           (0x1ul << I2C_BUSCTL_ACKM9SI_Pos)

#define I2C_BUSTCTL_BUSTOEN_Pos          (0)

#define I2C_BUSTCTL_BUSTOEN_Msk          (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos)

#define I2C_BUSTCTL_CLKTOEN_Pos          (1)

#define I2C_BUSTCTL_CLKTOEN_Msk          (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos)

#define I2C_BUSTCTL_BUSTOIEN_Pos         (2)

#define I2C_BUSTCTL_BUSTOIEN_Msk         (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos)

#define I2C_BUSTCTL_CLKTOIEN_Pos         (3)

#define I2C_BUSTCTL_CLKTOIEN_Msk         (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos)

#define I2C_BUSTCTL_TORSTEN_Pos          (4)

#define I2C_BUSTCTL_TORSTEN_Msk          (0x1ul << I2C_BUSTCTL_TORSTEN_Pos)

#define I2C_BUSTCTL_PECIEN_Pos           (5)

#define I2C_BUSTCTL_PECIEN_Msk           (0x1ul << I2C_BUSTCTL_PECIEN_Pos)

#define I2C_BUSSTS_BUSY_Pos              (0)

#define I2C_BUSSTS_BUSY_Msk              (0x1ul << I2C_BUSSTS_BUSY_Pos)

#define I2C_BUSSTS_BCDONE_Pos            (1)

#define I2C_BUSSTS_BCDONE_Msk            (0x1ul << I2C_BUSSTS_BCDONE_Pos)

#define I2C_BUSSTS_PECERR_Pos            (2)

#define I2C_BUSSTS_PECERR_Msk            (0x1ul << I2C_BUSSTS_PECERR_Pos)

#define I2C_BUSSTS_ALERT_Pos             (3)

#define I2C_BUSSTS_ALERT_Msk             (0x1ul << I2C_BUSSTS_ALERT_Pos)

#define I2C_BUSSTS_SCTLDIN_Pos           (4)

#define I2C_BUSSTS_SCTLDIN_Msk           (0x1ul << I2C_BUSSTS_SCTLDIN_Pos)

#define I2C_BUSSTS_BUSTO_Pos             (5)

#define I2C_BUSSTS_BUSTO_Msk             (0x1ul << I2C_BUSSTS_BUSTO_Pos)

#define I2C_BUSSTS_CLKTO_Pos             (6)

#define I2C_BUSSTS_CLKTO_Msk             (0x1ul << I2C_BUSSTS_CLKTO_Pos)

#define I2C_PKTSIZE_PLDSIZE_Pos          (0)

#define I2C_PKTSIZE_PLDSIZE_Msk          (0xfful << I2C_PKTSIZE_PLDSIZE_Pos)

#define I2C_PKTCRC_PECCRC_Pos            (0)

#define I2C_PKTCRC_PECCRC_Msk            (0xfful << I2C_PKTCRC_PECCRC_Pos)

#define I2C_BUSTOUT_BUSTO_Pos            (0)

#define I2C_BUSTOUT_BUSTO_Msk            (0xfful << I2C_BUSTOUT_BUSTO_Pos)

#define I2C_CLKTOUT_CLKTO_Pos            (0)

#define I2C_CLKTOUT_CLKTO_Msk            (0xfful << I2C_CLKTOUT_CLKTO_Pos)                  /* I2C_CONST */ /* end of I2C register group */


/*---------------------- Peripheral Direct Memory Access Controller -------------------------*/

typedef struct

{


    __IO uint32_t CTL;           /* Offset: 0x00/0x10/0x20/0x30/0x40/0x50/0x60/0x70/0x80/0x90/0xA0/0xB0  Descriptor Table Control Register of PDMA Channel 0~11 */

    __IO uint32_t SA;            /* Offset: 0x04/0x14/0x24/0x34/0x44/0x54/0x64/0x74/0x84/0x94/0xA4/0xB4  Source Address Register of PDMA Channel 0~11 */

    __IO uint32_t DA;            /* Offset: 0x08/0x18/0x28/0x38/0x48/0x58/0x68/0x78/0x88/0x98/0xA8/0xB8  Destination Address Register of PDMA Channel 0~11 */

    __IO uint32_t NEXT;          /* Offset: 0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C/0x8C/0x9C/0xAC/0xBC  First Scatter-Gather Descriptor Table Offset Address of PDMA Channel 0~11 */


} DSCT_T;


typedef struct

{


    DSCT_T        DSCT[12];      /* Offset: 0x0000 ~ 0x00BC  DMA Embedded Description Table 0~11                     */

    __I  uint32_t CURSCAT[12];

    __I  uint32_t RESERVE0[196]; /* Offset: 0xC0 ~ 0xEC Current Scatter-Gather Descriptor Table Address of PDMA Channel 0~11 */

    __IO uint32_t CHCTL;         /* Offset: 0x400  PDMA Channel Control Register                                     */

    __O  uint32_t STOP;          /* Offset: 0x404  PDMA Transfer Stop Control Register                               */

    __O  uint32_t SWREQ;         /* Offset: 0x408  PDMA Software Request Register                                    */

    __I  uint32_t TRGSTS;        /* Offset: 0x40C  PDMA Channel Request Status Register                              */

    __IO uint32_t PRISET;        /* Offset: 0x410  PDMA Fixed Priority Setting Register                              */

    __O  uint32_t PRICLR;        /* Offset: 0x414  PDMA Fixed Priority Clear Register                                */

    __IO uint32_t INTEN;         /* Offset: 0x418  PDMA Interrupt Enable Register                                    */

    __IO uint32_t INTSTS;        /* Offset: 0x41C  PDMA Interrupt Status Register                                    */

    __IO uint32_t ABTSTS;        /* Offset: 0x420  PDMA Channel Read/Write Target Abort Flag Register                */

    __IO uint32_t TDSTS;         /* Offset: 0x424  PDMA Channel Transfer Done Flag Register                          */

    __IO uint32_t SCATSTS;       /* Offset: 0x428  PDMA Scatter-Gather Table Empty Status Register                   */

    __I  uint32_t TACTSTS;

    __I  uint32_t RESERVE1[1];   /* Offset: 0x42C  PDMA Transfer Active Flag Register                                */

    __IO uint32_t TOUTEN;        /* Offset: 0x434  PDMA Time-out Enable register                                     */

    __IO uint32_t TOUTIEN;       /* Offset: 0x438  PDMA Time-out Interrupt Enable register                           */

    __IO uint32_t SCATBA;        /* Offset: 0x43C  PDMA Scatter-Gather Descriptor Table Base Address Register        */

    __IO uint32_t TOC0_1;        /* Offset: 0x440  PDMA Time-out Counter Ch1 and Ch0 Register                        */

    __IO uint32_t TOC2_3;        /* Offset: 0x444  PDMA Time-out Counter Ch3 and Ch2 Register                        */

    __IO uint32_t TOC4_5;        /* Offset: 0x448  PDMA Time-out Counter Ch5 and Ch4 Register                        */

    __IO uint32_t TOC6_7;

    __I  uint32_t RESERVE2[12];  /* Offset: 0x44C  PDMA Time-out Counter Ch7 and Ch6 Register                        */

    __IO uint32_t REQSEL0_3;     /* Offset: 0x480  PDMA Request Source Select Register 0                             */

    __IO uint32_t REQSEL4_7;     /* Offset: 0x484  PDMA Request Source Select Register 1                             */

    __IO uint32_t REQSEL8_11;    /* Offset: 0x484  PDMA Request Source Select Register 2                             */


} PDMA_T;


#define PDMA_DSCT_CTL_OPMODE_Pos         (0)

#define PDMA_DSCT_CTL_OPMODE_Msk         (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos)

#define PDMA_DSCT_CTL_TXTYPE_Pos         (2)

#define PDMA_DSCT_CTL_TXTYPE_Msk         (1ul << PDMA_DSCT_CTL_TXTYPE_Pos)

#define PDMA_DSCT_CTL_BURSIZE_Pos        (4)

#define PDMA_DSCT_CTL_BURSIZE_Msk        (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos)

#define PDMA_DSCT_CTL_TBINTDIS_Pos       (7)

#define PDMA_DSCT_CTL_TBINTDIS_Msk       (1ul << PDMA_DSCT_CTL_TBINTDIS_Pos)

#define PDMA_DSCT_CTL_SAINC_Pos          (8)

#define PDMA_DSCT_CTL_SAINC_Msk          (0x3ul << PDMA_DSCT_CTL_SAINC_Pos)

#define PDMA_DSCT_CTL_DAINC_Pos          (10)

#define PDMA_DSCT_CTL_DAINC_Msk          (0x3ul << PDMA_DSCT_CTL_DAINC_Pos)

#define PDMA_DSCT_CTL_TXWIDTH_Pos        (12)

#define PDMA_DSCT_CTL_TXWIDTH_Msk        (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos)

#define PDMA_DSCT_CTL_TXCNT_Pos          (16)

#define PDMA_DSCT_CTL_TXCNT_Msk          (0x3FFFul << PDMA_DSCT_CTL_TXCNT_Pos)

#define PDMA_DSCT_SA_SA_Pos              (0)

#define PDMA_DSCT_SA_SA_Msk              (0xFFFFFFFFul << PDMA_DSCT_SA_SA_Pos)

#define PDMA_DSCT_DA_DA_Pos              (0)

#define PDMA_DSCT_DA_DA_Msk              (0xFFFFFFFFul << PDMA_DSCT_DA_DA_Pos)

#define PDMA_DSCT_NEXT_NEXT_Pos          (0)

#define PDMA_DSCT_NEXT_NEXT_Msk          (0xFFFFul << PDMA_DSCT_NEXT_NEXT_Pos)

#define PDMA_CURSCAT_CURADDR_Pos         (0)

#define PDMA_CURSCAT_CURADDR_Msk         (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos)

#define PDMA_CHCTL_CHENn_Pos             (0)

#define PDMA_CHCTL_CHENn_Msk             (0xffful << PDMA_CHCTL_CHENn_Pos)

#define PDMA_STOP_STOPn_Pos              (0)

#define PDMA_STOP_STOPn_Msk              (0xffful << PDMA_STOP_STOPn_Pos)

#define PDMA_SWREQ_SWREQn_Pos            (0)

#define PDMA_SWREQ_SWREQn_Msk            (0xffful << PDMA_SWREQ_SWREQn_Pos)

#define PDMA_TRGSTS_REQSTSn_Pos          (0)

#define PDMA_TRGSTS_REQSTSn_Msk          (0xffful << PDMA_TRGSTS_REQSTSn_Pos)

#define PDMA_PRISET_FPRISETn_Pos         (0)

#define PDMA_PRISET_FPRISETn_Msk         (0xffful << PDMA_PRISET_FPRISETn_Pos)

#define PDMA_PRICLR_FPRICLRn_Pos         (0)

#define PDMA_PRICLR_FPRICLRn_Msk         (0xffful << PDMA_PRICLR_FPRICLRn_Pos)

#define PDMA_INTEN_INTENn_Pos            (0)

#define PDMA_INTEN_INTENn_Msk            (0xffful << PDMA_INTEN_INTENn_Pos)

#define PDMA_INTSTS_ABTIF_Pos            (0)

#define PDMA_INTSTS_ABTIF_Msk            (0x1ul << PDMA_INTSTS_ABTIF_Pos)

#define PDMA_INTSTS_TDIF_Pos             (1)

#define PDMA_INTSTS_TDIF_Msk             (0x1ul << PDMA_INTSTS_TDIF_Pos)

#define PDMA_INTSTS_TEIF_Pos             (2)

#define PDMA_INTSTS_TEIF_Msk             (0x1ul << PDMA_INTSTS_TEIF_Pos)

#define PDMA_INTSTS_REQTOFn_Pos          (8)

#define PDMA_INTSTS_REQTOFn_Msk          (0xfful << PDMA_INTSTS_REQTOFn_Pos)

#define PDMA_ABTSTS_ABTIFn_Pos           (0)

#define PDMA_ABTSTS_ABTIFn_Msk           (0xffful << PDMA_ABTSTS_ABTIFn_Pos)

#define PDMA_TDSTS_TDIFn_Pos             (0)

#define PDMA_TDSTS_TDIFn_Msk             (0xffful << PDMA_TDSTS_TDIFn_Pos)

#define PDMA_SCATSTS_TEMPTYFn_Pos        (0)

#define PDMA_SCATSTS_TEMPTYFn_Msk        (0xffful << PDMA_SCATSTS_TEMPTYFn_Pos)

#define PDMA_TACTSTS_TXACTFn_Pos         (0)

#define PDMA_TACTSTS_TXACTFn_Msk         (0xffful << PDMA_TACTSTS_TXACTFn_Pos)

#define PDMA_TOUTEN_TOUTENn_Pos          (0)

#define PDMA_TOUTEN_TOUTENn_Msk          (0xfful << PDMA_TOUTEN_TOUTENn_Pos)

#define PDMA_TOUTIEN_TOUTIENn_Pos        (0)

#define PDMA_TOUTIEN_TOUTIENn_Msk        (0xfful << PDMA_TOUTIEN_TOUTIENn_Pos)

#define PDMA_SCATBA_SCATBA_Pos           (16)

#define PDMA_SCATBA_SCATBA_Msk           (0xfffful << PDMA_SCATBA_SCATBA_Pos)

#define PDMA_TOC0_1_TOC0_Pos             (0)

#define PDMA_TOC0_1_TOC0_Msk             (0xfffful << PDMA_TOC0_1_TOC0_Pos)

#define PDMA_TOC0_1_TOC1_Pos             (16)

#define PDMA_TOC0_1_TOC1_Msk             (0xfffful << PDMA_TOC0_1_TOC1_Pos)

#define PDMA_TOC2_3_TOC2_Pos             (0)

#define PDMA_TOC2_3_TOC2_Msk             (0xfffful << PDMA_TOC2_3_TOC2_Pos)

#define PDMA_TOC2_3_TOC3_Pos             (16)

#define PDMA_TOC2_3_TOC3_Msk             (0xfffful << PDMA_TOC2_3_TOC3_Pos)

#define PDMA_TOC4_5_TOC4_Pos             (0)

#define PDMA_TOC4_5_TOC4_Msk             (0xfffful << PDMA_TOC4_5_TOC4_Pos)

#define PDMA_TOC4_5_TOC5_Pos             (16)

#define PDMA_TOC4_5_TOC5_Msk             (0xfffful << PDMA_TOC4_5_TOC5_Pos)

#define PDMA_TOC6_7_TOC6_Pos             (0)

#define PDMA_TOC6_7_TOC6_Msk             (0xfffful << PDMA_TOC6_7_TOC6_Pos)

#define PDMA_TOC6_7_TOC7_Pos             (16)

#define PDMA_TOC6_7_TOC7_Msk             (0xfffful << PDMA_TOC6_7_TOC7_Pos)

#define PDMA_REQSEL0_3_REQSRC0_Pos       (0)

#define PDMA_REQSEL0_3_REQSRC0_Msk       (0x1ful << PDMA_REQSEL0_3_REQSRC0_Pos)

#define PDMA_REQSEL0_3_REQSRC1_Pos       (8)

#define PDMA_REQSEL0_3_REQSRC1_Msk       (0x1ful << PDMA_REQSEL0_3_REQSRC1_Pos)

#define PDMA_REQSEL0_3_REQSRC2_Pos       (16)

#define PDMA_REQSEL0_3_REQSRC2_Msk       (0x1ful << PDMA_REQSEL0_3_REQSRC2_Pos)

#define PDMA_REQSEL0_3_REQSRC3_Pos       (24)

#define PDMA_REQSEL0_3_REQSRC3_Msk       (0x1ful << PDMA_REQSEL0_3_REQSRC3_Pos)

#define PDMA_REQSEL4_7_REQSRC4_Pos       (0)

#define PDMA_REQSEL4_7_REQSRC4_Msk       (0x1ful << PDMA_REQSEL4_7_REQSRC4_Pos)

#define PDMA_REQSEL4_7_REQSRC5_Pos       (8)

#define PDMA_REQSEL4_7_REQSRC5_Msk       (0x1ful << PDMA_REQSEL4_7_REQSRC5_Pos)

#define PDMA_REQSEL4_7_REQSRC6_Pos       (16)

#define PDMA_REQSEL4_7_REQSRC6_Msk       (0x1ful << PDMA_REQSEL4_7_REQSRC6_Pos)

#define PDMA_REQSEL4_7_REQSRC7_Pos       (24)

#define PDMA_REQSEL4_7_REQSRC7_Msk       (0x1ful << PDMA_REQSEL4_7_REQSRC7_Pos)

#define PDMA_REQSEL8_11_REQSRC8_Pos      (0)

#define PDMA_REQSEL8_11_REQSRC8_Msk      (0x1ful << PDMA_REQSEL8_11_REQSRC8_Pos)

#define PDMA_REQSEL8_11_REQSRC9_Pos      (8)

#define PDMA_REQSEL8_11_REQSRC9_Msk      (0x1ful << PDMA_REQSEL8_11_REQSRC9_Pos)

#define PDMA_REQSEL8_11_REQSRC10_Pos     (16)

#define PDMA_REQSEL8_11_REQSRC10_Msk     (0x1ful << PDMA_REQSEL8_11_REQSRC10_Pos)

#define PDMA_REQSEL8_11_REQSRC11_Pos     (24)

#define PDMA_REQSEL8_11_REQSRC11_Msk     (0x1ful << PDMA_REQSEL8_11_REQSRC11_Pos)           /* PDMA_CONST */ /* end of PDMA register group */


/*---------------------- Pulse Width Modulation Controller -------------------------*/

typedef struct

{


    __IO uint32_t CTL0;          /* Offset: 0x00  PWM Control Register 0                                             */

    __IO uint32_t CTL1;          /* Offset: 0x04  PWM Control Register 1                                             */

    __IO uint32_t SYNC;          /* Offset: 0x08  PWM Synchronization Register                                       */

    __IO uint32_t SWSYNC;        /* Offset: 0x0C  PWM Software Control Synchronization Register                      */

    __IO uint32_t CLKSRC;        /* Offset: 0x10  PWM Clock Source Register                                          */

    __IO uint32_t CLKPSC0_1;     /* Offset: 0x14  PWM Clock Pre-scale Register 0                                     */

    __IO uint32_t CLKPSC2_3;     /* Offset: 0x18  PWM Clock Pre-scale Register 2                                     */

    __IO uint32_t CLKPSC4_5;     /* Offset: 0x1C  PWM Clock Pre-scale Register 4                                     */

    __IO uint32_t CNTEN;         /* Offset: 0x20  PWM Counter Enable Register                                        */

    __IO uint32_t CNTCLR;        /* Offset: 0x24  PWM Clear Counter Register                                         */

    __IO uint32_t LOAD;          /* Offset: 0x28  PWM Load Register                                                  */

    __I  uint32_t RESERVE0[1];

    __IO uint32_t PERIOD[6];     /* Offset: 0x30~0x44  PWM Period Register 0~5                                       */

    __I  uint32_t RESERVE1[2];

    __IO uint32_t CMPDAT[6];     /* Offset: 0x50~0x64  PWM Comparator Register 0~5                                   */

    __I  uint32_t RESERVE2[2];

    __IO uint32_t DTCTL0_1;      /* Offset: 0x70  PWM Dead-Time Control Register 0                                   */

    __IO uint32_t DTCTL2_3;      /* Offset: 0x74  PWM Dead-Time Control Register 2                                   */

    __IO uint32_t DTCTL4_5;      /* Offset: 0x78  PWM Dead-Time Control Register 4                                   */

    __I  uint32_t RESERVE3[1];

    __IO uint32_t PHS0_1;        /* Offset: 0x80  PWM Counter Phase Register 0                                       */

    __IO uint32_t PHS2_3;        /* Offset: 0x84  PWM Counter Phase Register 2                                       */

    __IO uint32_t PHS4_5;        /* Offset: 0x88  PWM Counter Phase Register 4                                       */

    __I  uint32_t RESERVE4[1];

    __I  uint32_t CNT[6];        /* Offset: 0x90~0xA4  PWM Counter Register 0~5                                      */

    __I  uint32_t RESERVE5[2];

    __IO uint32_t WGCTL0;        /* Offset: 0xB0  PWM Generation Register 0                                          */

    __IO uint32_t WGCTL1;        /* Offset: 0xB4  PWM Generation Register 1                                          */

    __IO uint32_t MSKEN;         /* Offset: 0xB8  PWM Mask Enable Register                                           */

    __IO uint32_t MSK;           /* Offset: 0xBC  PWM Mask Data Register                                             */

    __IO uint32_t BNF;           /* Offset: 0xC0  PWM Brake Noise Filter Register                                    */

    __IO uint32_t FAILBRK;       /* Offset: 0xC4  PWM System Fail Brake Control Register                             */

    __IO uint32_t BRKCTL0_1;     /* Offset: 0xC8  PWM Brake Edge Detect Control Register 0                           */

    __IO uint32_t BRKCTL2_3;     /* Offset: 0xCC  PWM Brake Edge Detect Control Register 2                           */

    __IO uint32_t BRKCTL4_5;     /* Offset: 0xD0  PWM Brake Edge Detect Control Register 4                           */

    __IO uint32_t POLCTL;        /* Offset: 0xD4  PWM Pin Polar Inverse Register                                     */

    __IO uint32_t POEN;          /* Offset: 0xD8  PWM Output Enable Register                                         */

    __O  uint32_t SWBRK;         /* Offset: 0xDC  PWM Software Brake Control Register                                */

    __IO uint32_t INTEN0;        /* Offset: 0xE0  PWM Interrupt Enable Register 0                                    */

    __IO uint32_t INTEN1;        /* Offset: 0xE4  PWM Interrupt Enable Register 1                                    */

    __IO uint32_t INTSTS0;       /* Offset: 0xE8  PWM Interrupt Flag Register 0                                      */

    __IO uint32_t INTSTS1;       /* Offset: 0xEC  PWM Interrupt Flag Register 1                                      */

    __IO uint32_t IFA;           /* Offset: 0xF0  PWM Interrupt Flag Accumulator Register                            */

    __IO uint32_t RESERVE6[1];

    __IO uint32_t EADCTS0;       /* Offset: 0xF8  PWM Trigger EADC Source Select Register 0                          */

    __IO uint32_t EADCTS1;       /* Offset: 0xFC  PWM Trigger EADC Source Select Register 1                          */

    __IO uint32_t FTCMPDAT0_1;   /* Offset: 0x100  PWM Free Trigger Compare Register 0                               */

    __IO uint32_t FTCMPDAT2_3;   /* Offset: 0x104  PWM Free Trigger Compare Register 2                               */

    __IO uint32_t FTCMPDAT4_5;   /* Offset: 0x108  PWM Free Trigger Compare Register 4                               */

    __I  uint32_t RESERVE7[1];

    __IO uint32_t SSCTL;         /* Offset: 0x110  PWM Synchronous Start Control Register                            */

    __O  uint32_t SSTRG;         /* Offset: 0x114  PWM Synchronous Start Trigger Register                            */

    __I  uint32_t RESERVE8[2];

    __IO uint32_t STATUS;        /* Offset: 0x120  PWM Status Register                                               */

    __I  uint32_t RESERVE9[55];

    __IO uint32_t CAPINEN;       /* Offset: 0x200  PWM Capture Input Enable Register                                 */

    __IO uint32_t CAPCTL;        /* Offset: 0x204  PWM Capture Control Register                                      */

    __I  uint32_t CAPSTS;        /* Offset: 0x208  PWM Capture Status Register                                       */

    __I  uint32_t RCAPDAT0;      /* Offset: 0x20C  PWM Rising Capture Data Register 0                                */

    __I  uint32_t FCAPDAT0;      /* Offset: 0x210  PWM Falling Capture Data Register 0                               */

    __I  uint32_t RCAPDAT1;      /* Offset: 0x214  PWM Rising Capture Data Register 1                                */

    __I  uint32_t FCAPDAT1;      /* Offset: 0x218  PWM Falling Capture Data Register 1                               */

    __I  uint32_t RCAPDAT2;      /* Offset: 0x21C  PWM Rising Capture Data Register 2                                */

    __I  uint32_t FCAPDAT2;      /* Offset: 0x220  PWM Falling Capture Data Register 2                               */

    __I  uint32_t RCAPDAT3;      /* Offset: 0x224  PWM Rising Capture Data Register 3                                */

    __I  uint32_t FCAPDAT3;      /* Offset: 0x228  PWM Falling Capture Data Register 3                               */

    __I  uint32_t RCAPDAT4;      /* Offset: 0x22C  PWM Rising Capture Data Register 4                                */

    __I  uint32_t FCAPDAT4;      /* Offset: 0x230  PWM Falling Capture Data Register 4                               */

    __I  uint32_t RCAPDAT5;      /* Offset: 0x234  PWM Rising Capture Data Register 5                                */

    __I  uint32_t FCAPDAT5;      /* Offset: 0x238  PWM Falling Capture Data Register 5                               */

    __IO uint32_t PDMACTL;       /* Offset: 0x23C  PWM PDMA Control Register                                         */

    __I  uint32_t PDMACAP0_1;    /* Offset: 0x240  PWM Capture Channel 01 PDMA Register                              */

    __I  uint32_t PDMACAP2_3;    /* Offset: 0x244  PWM Capture Channel 23 PDMA Register                              */

    __I  uint32_t PDMACAP4_5;    /* Offset: 0x248  PWM Capture Channel 45 PDMA Register                              */

    __I  uint32_t RESERVE10[1];

    __IO uint32_t CAPIEN;        /* Offset: 0x250  PWM Capture Interrupt Enable Register                             */

    __IO uint32_t CAPIF;         /* Offset: 0x254  PWM Capture Interrupt Flag Register                               */

    __I  uint32_t RESERVE11[43];

    __I  uint32_t PBUF[6];       /* Offset: 0x304~0x318  PWM PERIOD0~5 Buffer                                        */

    __I  uint32_t CMPBUF[6];     /* Offset: 0x31C~0x330  PWM CMPDAT0~5 Buffer                                        */

    __I  uint32_t RESERVE12[3];

    __I  uint32_t FTCBUF0_1;     /* Offset: 0x340  PWM FTCMPDAT0_1 Buffer                                            */

    __I  uint32_t FTCBUF2_3;     /* Offset: 0x344  PWM FTCMPDAT2_3 Buffer                                            */

    __I  uint32_t FTCBUF4_5;     /* Offset: 0x348  PWM FTCMPDAT4_5 Buffer                                            */

    __IO uint32_t FTCI;          /* Offset: 0x34C  PWM FTCMPDAT Indicator Register                                   */


} PWM_T;


#define PWM_CTL0_CTRLDn_Pos              (0)

#define PWM_CTL0_CTRLDn_Msk              (0x3ful << PWM_CTL0_CTRLDn_Pos)

#define PWM_CTL0_CTRLD0_Pos              (0)

#define PWM_CTL0_CTRLD0_Msk              (0x1ul << PWM_CTL0_CTRLD0_Pos)

#define PWM_CTL0_CTRLD1_Pos              (1)

#define PWM_CTL0_CTRLD1_Msk              (0x1ul << PWM_CTL0_CTRLD1_Pos)

#define PWM_CTL0_CTRLD2_Pos              (2)

#define PWM_CTL0_CTRLD2_Msk              (0x1ul << PWM_CTL0_CTRLD2_Pos)

#define PWM_CTL0_CTRLD3_Pos              (3)

#define PWM_CTL0_CTRLD3_Msk              (0x1ul << PWM_CTL0_CTRLD3_Pos)

#define PWM_CTL0_CTRLD4_Pos              (4)

#define PWM_CTL0_CTRLD4_Msk              (0x1ul << PWM_CTL0_CTRLD4_Pos)

#define PWM_CTL0_CTRLD5_Pos              (5)

#define PWM_CTL0_CTRLD5_Msk              (0x1ul << PWM_CTL0_CTRLD5_Pos)

#define PWM_CTL0_WINLDENn_Pos            (8)

#define PWM_CTL0_WINLDENn_Msk            (0x3ful << PWM_CTL0_WINLDENn_Pos)

#define PWM_CTL0_WINLDEN0_Pos            (8)

#define PWM_CTL0_WINLDEN0_Msk            (0x1ul << PWM_CTL0_WINLDEN0_Pos)

#define PWM_CTL0_WINLDEN1_Pos            (9)

#define PWM_CTL0_WINLDEN1_Msk            (0x1ul << PWM_CTL0_WINLDEN1_Pos)

#define PWM_CTL0_WINLDEN2_Pos            (10)

#define PWM_CTL0_WINLDEN2_Msk            (0x1ul << PWM_CTL0_WINLDEN2_Pos)

#define PWM_CTL0_WINLDEN3_Pos            (11)

#define PWM_CTL0_WINLDEN3_Msk            (0x1ul << PWM_CTL0_WINLDEN3_Pos)

#define PWM_CTL0_WINLDEN4_Pos            (12)

#define PWM_CTL0_WINLDEN4_Msk            (0x1ul << PWM_CTL0_WINLDEN4_Pos)

#define PWM_CTL0_WINLDEN5_Pos            (13)

#define PWM_CTL0_WINLDEN5_Msk            (0x1ul << PWM_CTL0_WINLDEN5_Pos)

#define PWM_CTL0_IMMLDENn_Pos            (16)

#define PWM_CTL0_IMMLDENn_Msk            (0x3ful << PWM_CTL0_IMMLDENn_Pos)

#define PWM_CTL0_IMMLDEN0_Pos            (16)

#define PWM_CTL0_IMMLDEN0_Msk            (0x1ul << PWM_CTL0_IMMLDEN0_Pos)

#define PWM_CTL0_IMMLDEN1_Pos            (17)

#define PWM_CTL0_IMMLDEN1_Msk            (0x1ul << PWM_CTL0_IMMLDEN1_Pos)

#define PWM_CTL0_IMMLDEN2_Pos            (18)

#define PWM_CTL0_IMMLDEN2_Msk            (0x1ul << PWM_CTL0_IMMLDEN2_Pos)

#define PWM_CTL0_IMMLDEN3_Pos            (19)

#define PWM_CTL0_IMMLDEN3_Msk            (0x1ul << PWM_CTL0_IMMLDEN3_Pos)

#define PWM_CTL0_IMMLDEN4_Pos            (20)

#define PWM_CTL0_IMMLDEN4_Msk            (0x1ul << PWM_CTL0_IMMLDEN4_Pos)

#define PWM_CTL0_IMMLDEN5_Pos            (21)

#define PWM_CTL0_IMMLDEN5_Msk            (0x1ul << PWM_CTL0_IMMLDEN5_Pos)

#define PWM_CTL0_GROUPEN_Pos             (24)

#define PWM_CTL0_GROUPEN_Msk             (0x1ul << PWM_CTL0_GROUPEN_Pos)

#define PWM_CTL0_DBGHALT_Pos             (30)

#define PWM_CTL0_DBGHALT_Msk             (0x1ul << PWM_CTL0_DBGHALT_Pos)

#define PWM_CTL0_DBGTRIOFF_Pos           (31)

#define PWM_CTL0_DBGTRIOFF_Msk           (0x1ul << PWM_CTL0_DBGTRIOFF_Pos)

#define PWM_CTL1_CNTTYPEn_Pos            (0)

#define PWM_CTL1_CNTTYPEn_Msk            (0xffful << PWM_CTL1_CNTTYPEn_Pos)

#define PWM_CTL1_CNTTYPE0_Pos            (0)

#define PWM_CTL1_CNTTYPE0_Msk            (0x3ul << PWM_CTL1_CNTTYPE0_Pos)

#define PWM_CTL1_CNTTYPE1_Pos            (2)

#define PWM_CTL1_CNTTYPE1_Msk            (0x3ul << PWM_CTL1_CNTTYPE1_Pos)

#define PWM_CTL1_CNTTYPE2_Pos            (4)

#define PWM_CTL1_CNTTYPE2_Msk            (0x3ul << PWM_CTL1_CNTTYPE2_Pos)

#define PWM_CTL1_CNTTYPE3_Pos            (6)

#define PWM_CTL1_CNTTYPE3_Msk            (0x3ul << PWM_CTL1_CNTTYPE3_Pos)

#define PWM_CTL1_CNTTYPE4_Pos            (8)

#define PWM_CTL1_CNTTYPE4_Msk            (0x3ul << PWM_CTL1_CNTTYPE4_Pos)

#define PWM_CTL1_CNTTYPE5_Pos            (10)

#define PWM_CTL1_CNTTYPE5_Msk            (0x3ul << PWM_CTL1_CNTTYPE5_Pos)

#define PWM_CTL1_CNTMODEn_Pos            (16)

#define PWM_CTL1_CNTMODEn_Msk            (0x3ful << PWM_CTL1_CNTMODEn_Pos)

#define PWM_CTL1_CNTMODE0_Pos            (16)

#define PWM_CTL1_CNTMODE0_Msk            (0x1ul << PWM_CTL1_CNTMODE0_Pos)

#define PWM_CTL1_CNTMODE1_Pos            (17)

#define PWM_CTL1_CNTMODE1_Msk            (0x1ul << PWM_CTL1_CNTMODE1_Pos)

#define PWM_CTL1_CNTMODE2_Pos            (18)

#define PWM_CTL1_CNTMODE2_Msk            (0x1ul << PWM_CTL1_CNTMODE2_Pos)

#define PWM_CTL1_CNTMODE3_Pos            (19)

#define PWM_CTL1_CNTMODE3_Msk            (0x1ul << PWM_CTL1_CNTMODE3_Pos)

#define PWM_CTL1_CNTMODE4_Pos            (20)

#define PWM_CTL1_CNTMODE4_Msk            (0x1ul << PWM_CTL1_CNTMODE4_Pos)

#define PWM_CTL1_CNTMODE5_Pos            (21)

#define PWM_CTL1_CNTMODE5_Msk            (0x1ul << PWM_CTL1_CNTMODE5_Pos)

#define PWM_CTL1_OUTMODEn_Pos            (24)

#define PWM_CTL1_OUTMODEn_Msk            (0x7ul << PWM_CTL1_OUTMODEn_Pos)

#define PWM_CTL1_OUTMODE0_Pos            (24)

#define PWM_CTL1_OUTMODE0_Msk            (0x1ul << PWM_CTL1_OUTMODE0_Pos)

#define PWM_CTL1_OUTMODE2_Pos            (25)

#define PWM_CTL1_OUTMODE2_Msk            (0x1ul << PWM_CTL1_OUTMODE2_Pos)

#define PWM_CTL1_OUTMODE4_Pos            (26)

#define PWM_CTL1_OUTMODE4_Msk            (0x1ul << PWM_CTL1_OUTMODE4_Pos)

#define PWM_SYNC_PHSENn_Pos              (0)

#define PWM_SYNC_PHSENn_Msk              (0x7ul << PWM_SYNC_PHSENn_Pos)

#define PWM_SYNC_PHSEN0_Pos              (0)

#define PWM_SYNC_PHSEN0_Msk              (0x1ul << PWM_SYNC_PHSEN0_Pos)

#define PWM_SYNC_PHSEN2_Pos              (1)

#define PWM_SYNC_PHSEN2_Msk              (0x1ul << PWM_SYNC_PHSEN2_Pos)

#define PWM_SYNC_PHSEN4_Pos              (2)

#define PWM_SYNC_PHSEN4_Msk              (0x1ul << PWM_SYNC_PHSEN4_Pos)

#define PWM_SYNC_SINSRCn_Pos             (8)

#define PWM_SYNC_SINSRCn_Msk             (0x3ful << PWM_SYNC_SINSRCn_Pos)

#define PWM_SYNC_SINSRC0_Pos             (8)

#define PWM_SYNC_SINSRC0_Msk             (0x3ul << PWM_SYNC_SINSRC0_Pos)

#define PWM_SYNC_SINSRC2_Pos             (10)

#define PWM_SYNC_SINSRC2_Msk             (0x3ul << PWM_SYNC_SINSRC2_Pos)

#define PWM_SYNC_SINSRC4_Pos             (12)

#define PWM_SYNC_SINSRC4_Msk             (0x3ul << PWM_SYNC_SINSRC4_Pos)

#define PWM_SYNC_SNFLTEN_Pos             (16)

#define PWM_SYNC_SNFLTEN_Msk             (0x1ul << PWM_SYNC_SNFLTEN_Pos)

#define PWM_SYNC_SFLTCSEL_Pos            (17)

#define PWM_SYNC_SFLTCSEL_Msk            (0x7ul << PWM_SYNC_SFLTCSEL_Pos)

#define PWM_SYNC_SFLTCNT_Pos             (20)

#define PWM_SYNC_SFLTCNT_Msk             (0x7ul << PWM_SYNC_SFLTCNT_Pos)

#define PWM_SYNC_SINPINV_Pos             (23)

#define PWM_SYNC_SINPINV_Msk             (0x1ul << PWM_SYNC_SINPINV_Pos)

#define PWM_SYNC_PHSDIRn_Pos             (24)

#define PWM_SYNC_PHSDIRn_Msk             (0x7ul << PWM_SYNC_PHSDIRn_Pos)

#define PWM_SYNC_PHSDIR0_Pos             (24)

#define PWM_SYNC_PHSDIR0_Msk             (0x1ul << PWM_SYNC_PHSDIR0_Pos)

#define PWM_SYNC_PHSDIR2_Pos             (25)

#define PWM_SYNC_PHSDIR2_Msk             (0x1ul << PWM_SYNC_PHSDIR2_Pos)

#define PWM_SYNC_PHSDIR4_Pos             (26)

#define PWM_SYNC_PHSDIR4_Msk             (0x1ul << PWM_SYNC_PHSDIR4_Pos)

#define PWM_SWSYNC_SWSYNCn_Pos           (0)

#define PWM_SWSYNC_SWSYNCn_Msk           (0x7ul << PWM_SWSYNC_SWSYNCn_Pos)

#define PWM_SWSYNC_SWSYNC0_Pos           (0)

#define PWM_SWSYNC_SWSYNC0_Msk           (0x1ul << PWM_SWSYNC_SWSYNC0_Pos)

#define PWM_SWSYNC_SWSYNC2_Pos           (1)

#define PWM_SWSYNC_SWSYNC2_Msk           (0x1ul << PWM_SWSYNC_SWSYNC2_Pos)

#define PWM_SWSYNC_SWSYNC4_Pos           (2)

#define PWM_SWSYNC_SWSYNC4_Msk           (0x1ul << PWM_SWSYNC_SWSYNC4_Pos)

#define PWM_CLKSRC_ECLKSRC0_Pos          (0)

#define PWM_CLKSRC_ECLKSRC0_Msk          (0x7ul << PWM_CLKSRC_ECLKSRC0_Pos)

#define PWM_CLKSRC_ECLKSRC2_Pos          (8)

#define PWM_CLKSRC_ECLKSRC2_Msk          (0x7ul << PWM_CLKSRC_ECLKSRC2_Pos)

#define PWM_CLKSRC_ECLKSRC4_Pos          (16)

#define PWM_CLKSRC_ECLKSRC4_Msk          (0x7ul << PWM_CLKSRC_ECLKSRC4_Pos)

#define PWM_CLKPSC0_1_CLKPSC_Pos         (0)

#define PWM_CLKPSC0_1_CLKPSC_Msk         (0xffful << PWM_CLKPSC0_1_CLKPSC_Pos)

#define PWM_CLKPSC2_3_CLKPSC_Pos         (0)

#define PWM_CLKPSC2_3_CLKPSC_Msk         (0xffful << PWM_CLKPSC2_3_CLKPSC_Pos)

#define PWM_CLKPSC4_5_CLKPSC_Pos         (0)

#define PWM_CLKPSC4_5_CLKPSC_Msk         (0xffful << PWM_CLKPSC4_5_CLKPSC_Pos)

#define PWM_CNTEN_CNTENn_Pos             (0)

#define PWM_CNTEN_CNTENn_Msk             (0x3ful << PWM_CNTEN_CNTENn_Pos)

#define PWM_CNTEN_CNTEN0_Pos             (0)

#define PWM_CNTEN_CNTEN0_Msk             (0x1ul << PWM_CNTEN_CNTEN0_Pos)

#define PWM_CNTEN_CNTEN1_Pos             (1)

#define PWM_CNTEN_CNTEN1_Msk             (0x1ul << PWM_CNTEN_CNTEN1_Pos)

#define PWM_CNTEN_CNTEN2_Pos             (2)

#define PWM_CNTEN_CNTEN2_Msk             (0x1ul << PWM_CNTEN_CNTEN2_Pos)

#define PWM_CNTEN_CNTEN3_Pos             (3)

#define PWM_CNTEN_CNTEN3_Msk             (0x1ul << PWM_CNTEN_CNTEN3_Pos)

#define PWM_CNTEN_CNTEN4_Pos             (4)

#define PWM_CNTEN_CNTEN4_Msk             (0x1ul << PWM_CNTEN_CNTEN4_Pos)

#define PWM_CNTEN_CNTEN5_Pos             (5)

#define PWM_CNTEN_CNTEN5_Msk             (0x1ul << PWM_CNTEN_CNTEN5_Pos)

#define PWM_CNTCLR_CNTCLRn_Pos           (0)

#define PWM_CNTCLR_CNTCLRn_Msk           (0x3ful << PWM_CNTCLR_CNTCLRn_Pos)

#define PWM_CNTCLR_CNTCLR0_Pos           (0)

#define PWM_CNTCLR_CNTCLR0_Msk           (0x1ul << PWM_CNTCLR_CNTCLR0_Pos)

#define PWM_CNTCLR_CNTCLR1_Pos           (1)

#define PWM_CNTCLR_CNTCLR1_Msk           (0x1ul << PWM_CNTCLR_CNTCLR1_Pos)

#define PWM_CNTCLR_CNTCLR2_Pos           (2)

#define PWM_CNTCLR_CNTCLR2_Msk           (0x1ul << PWM_CNTCLR_CNTCLR2_Pos)

#define PWM_CNTCLR_CNTCLR3_Pos           (3)

#define PWM_CNTCLR_CNTCLR3_Msk           (0x1ul << PWM_CNTCLR_CNTCLR3_Pos)

#define PWM_CNTCLR_CNTCLR4_Pos           (4)

#define PWM_CNTCLR_CNTCLR4_Msk           (0x1ul << PWM_CNTCLR_CNTCLR4_Pos)

#define PWM_CNTCLR_CNTCLR5_Pos           (5)

#define PWM_CNTCLR_CNTCLR5_Msk           (0x1ul << PWM_CNTCLR_CNTCLR5_Pos)

#define PWM_LOAD_LOADn_Pos               (0)

#define PWM_LOAD_LOADn_Msk               (0x3ful << PWM_LOAD_LOADn_Pos)

#define PWM_LOAD_LOAD0_Pos               (0)

#define PWM_LOAD_LOAD0_Msk               (0x1ul << PWM_LOAD_LOAD0_Pos)

#define PWM_LOAD_LOAD1_Pos               (1)

#define PWM_LOAD_LOAD1_Msk               (0x1ul << PWM_LOAD_LOAD1_Pos)

#define PWM_LOAD_LOAD2_Pos               (2)

#define PWM_LOAD_LOAD2_Msk               (0x1ul << PWM_LOAD_LOAD2_Pos)

#define PWM_LOAD_LOAD3_Pos               (3)

#define PWM_LOAD_LOAD3_Msk               (0x1ul << PWM_LOAD_LOAD3_Pos)

#define PWM_LOAD_LOAD4_Pos               (4)

#define PWM_LOAD_LOAD4_Msk               (0x1ul << PWM_LOAD_LOAD4_Pos)

#define PWM_LOAD_LOAD5_Pos               (5)

#define PWM_LOAD_LOAD5_Msk               (0x1ul << PWM_LOAD_LOAD5_Pos)

#define PWM_PERIOD_PERIOD_Pos            (0)

#define PWM_PERIOD_PERIOD_Msk            (0xfffful << PWM_PERIOD_PERIOD_Pos)

#define PWM_CMPDAT_CMP_Pos               (0)

#define PWM_CMPDAT_CMP_Msk               (0xfffful << PWM_CMPDAT_CMP_Pos)

#define PWM_DTCTL0_1_DTCNT_Pos           (0)

#define PWM_DTCTL0_1_DTCNT_Msk           (0xffful << PWM_DTCTL0_1_DTCNT_Pos)

#define PWM_DTCTL0_1_DTEN_Pos            (16)

#define PWM_DTCTL0_1_DTEN_Msk            (0x1ul << PWM_DTCTL0_1_DTEN_Pos)

#define PWM_DTCTL0_1_DTCKSEL_Pos         (24)

#define PWM_DTCTL0_1_DTCKSEL_Msk         (0x1ul << PWM_DTCTL0_1_DTCKSEL_Pos)

#define PWM_DTCTL2_3_DTCNT_Pos           (0)

#define PWM_DTCTL2_3_DTCNT_Msk           (0xffful << PWM_DTCTL2_3_DTCNT_Pos)

#define PWM_DTCTL2_3_DTEN_Pos            (16)

#define PWM_DTCTL2_3_DTEN_Msk            (0x1ul << PWM_DTCTL2_3_DTEN_Pos)

#define PWM_DTCTL2_3_DTCKSEL_Pos         (24)

#define PWM_DTCTL2_3_DTCKSEL_Msk         (0x1ul << PWM_DTCTL2_3_DTCKSEL_Pos)

#define PWM_DTCTL4_5_DTCNT_Pos           (0)

#define PWM_DTCTL4_5_DTCNT_Msk           (0xffful << PWM_DTCTL4_5_DTCNT_Pos)

#define PWM_DTCTL4_5_DTEN_Pos            (16)

#define PWM_DTCTL4_5_DTEN_Msk            (0x1ul << PWM_DTCTL4_5_DTEN_Pos)

#define PWM_DTCTL4_5_DTCKSEL_Pos         (24)

#define PWM_DTCTL4_5_DTCKSEL_Msk         (0x1ul << PWM_DTCTL4_5_DTCKSEL_Pos)

#define PWM_PHS0_1_PHS_Pos               (0)

#define PWM_PHS0_1_PHS_Msk               (0xfffful << PWM_PHS0_1_PHS_Pos)

#define PWM_PHS2_3_PHS_Pos               (0)

#define PWM_PHS2_3_PHS_Msk               (0xfffful << PWM_PHS2_3_PHS_Pos)

#define PWM_PHS4_5_PHS_Pos               (0)

#define PWM_PHS4_5_PHS_Msk               (0xfffful << PWM_PHS4_5_PHS_Pos)

#define PWM_CNT_CNT_Pos                  (0)

#define PWM_CNT_CNT_Msk                  (0xfffful << PWM_CNT_CNT_Pos)

#define PWM_CNT_DIRF_Pos                 (16)

#define PWM_CNT_DIRF_Msk                 (0x1ul << PWM_CNT_DIRF_Pos)

#define PWM_WGCTL0_ZPCTLn_Pos            (0)

#define PWM_WGCTL0_ZPCTLn_Msk            (0xffful << PWM_WGCTL0_ZPCTLn_Pos)

#define PWM_WGCTL0_ZPCTL0_Pos            (0)

#define PWM_WGCTL0_ZPCTL0_Msk            (0x3ul << PWM_WGCTL0_ZPCTL0_Pos)

#define PWM_WGCTL0_ZPCTL1_Pos            (2)

#define PWM_WGCTL0_ZPCTL1_Msk            (0x3ul << PWM_WGCTL0_ZPCTL1_Pos)

#define PWM_WGCTL0_ZPCTL2_Pos            (4)

#define PWM_WGCTL0_ZPCTL2_Msk            (0x3ul << PWM_WGCTL0_ZPCTL2_Pos)

#define PWM_WGCTL0_ZPCTL3_Pos            (6)

#define PWM_WGCTL0_ZPCTL3_Msk            (0x3ul << PWM_WGCTL0_ZPCTL3_Pos)

#define PWM_WGCTL0_ZPCTL4_Pos            (8)

#define PWM_WGCTL0_ZPCTL4_Msk            (0x3ul << PWM_WGCTL0_ZPCTL4_Pos)

#define PWM_WGCTL0_ZPCTL5_Pos            (10)

#define PWM_WGCTL0_ZPCTL5_Msk            (0x3ul << PWM_WGCTL0_ZPCTL5_Pos)

#define PWM_WGCTL0_PRDPCTLn_Pos          (16)

#define PWM_WGCTL0_PRDPCTLn_Msk          (0xffful << PWM_WGCTL0_PRDPCTLn_Pos)

#define PWM_WGCTL0_PRDPCTL0_Pos          (16)

#define PWM_WGCTL0_PRDPCTL0_Msk          (0x3ul << PWM_WGCTL0_PRDPCTL0_Pos)

#define PWM_WGCTL0_PRDPCTL1_Pos          (18)

#define PWM_WGCTL0_PRDPCTL1_Msk          (0x3ul << PWM_WGCTL0_PRDPCTL1_Pos)

#define PWM_WGCTL0_PRDPCTL2_Pos          (20)

#define PWM_WGCTL0_PRDPCTL2_Msk          (0x3ul << PWM_WGCTL0_PRDPCTL2_Pos)

#define PWM_WGCTL0_PRDPCTL3_Pos          (22)

#define PWM_WGCTL0_PRDPCTL3_Msk          (0x3ul << PWM_WGCTL0_PRDPCTL3_Pos)

#define PWM_WGCTL0_PRDPCTL4_Pos          (24)

#define PWM_WGCTL0_PRDPCTL4_Msk          (0x3ul << PWM_WGCTL0_PRDPCTL4_Pos)

#define PWM_WGCTL0_PRDPCTL5_Pos          (26)

#define PWM_WGCTL0_PRDPCTL5_Msk          (0x3ul << PWM_WGCTL0_PRDPCTL5_Pos)

#define PWM_WGCTL1_CMPUCTLn_Pos          (0)

#define PWM_WGCTL1_CMPUCTLn_Msk          (0xffful << PWM_WGCTL1_CMPUCTLn_Pos)

#define PWM_WGCTL1_CMPUCTL0_Pos          (0)

#define PWM_WGCTL1_CMPUCTL0_Msk          (0x3ul << PWM_WGCTL1_CMPUCTL0_Pos)

#define PWM_WGCTL1_CMPUCTL1_Pos          (2)

#define PWM_WGCTL1_CMPUCTL1_Msk          (0x3ul << PWM_WGCTL1_CMPUCTL1_Pos)

#define PWM_WGCTL1_CMPUCTL2_Pos          (4)

#define PWM_WGCTL1_CMPUCTL2_Msk          (0x3ul << PWM_WGCTL1_CMPUCTL2_Pos)

#define PWM_WGCTL1_CMPUCTL3_Pos          (6)

#define PWM_WGCTL1_CMPUCTL3_Msk          (0x3ul << PWM_WGCTL1_CMPUCTL3_Pos)

#define PWM_WGCTL1_CMPUCTL4_Pos          (8)

#define PWM_WGCTL1_CMPUCTL4_Msk          (0x3ul << PWM_WGCTL1_CMPUCTL4_Pos)

#define PWM_WGCTL1_CMPUCTL5_Pos          (10)

#define PWM_WGCTL1_CMPUCTL5_Msk          (0x3ul << PWM_WGCTL1_CMPUCTL5_Pos)

#define PWM_WGCTL1_CMPDCTLn_Pos          (16)

#define PWM_WGCTL1_CMPDCTLn_Msk          (0xffful << PWM_WGCTL1_CMPDCTLn_Pos)

#define PWM_WGCTL1_CMPDCTL0_Pos          (16)

#define PWM_WGCTL1_CMPDCTL0_Msk          (0x3ul << PWM_WGCTL1_CMPDCTL0_Pos)

#define PWM_WGCTL1_CMPDCTL1_Pos          (18)

#define PWM_WGCTL1_CMPDCTL1_Msk          (0x3ul << PWM_WGCTL1_CMPDCTL1_Pos)

#define PWM_WGCTL1_CMPDCTL2_Pos          (20)

#define PWM_WGCTL1_CMPDCTL2_Msk          (0x3ul << PWM_WGCTL1_CMPDCTL2_Pos)

#define PWM_WGCTL1_CMPDCTL3_Pos          (22)

#define PWM_WGCTL1_CMPDCTL3_Msk          (0x3ul << PWM_WGCTL1_CMPDCTL3_Pos)

#define PWM_WGCTL1_CMPDCTL4_Pos          (24)

#define PWM_WGCTL1_CMPDCTL4_Msk          (0x3ul << PWM_WGCTL1_CMPDCTL4_Pos)

#define PWM_WGCTL1_CMPDCTL5_Pos          (26)

#define PWM_WGCTL1_CMPDCTL5_Msk          (0x3ul << PWM_WGCTL1_CMPDCTL5_Pos)

#define PWM_MSKEN_MSKENn_Pos             (0)

#define PWM_MSKEN_MSKENn_Msk             (0x3ful << PWM_MSKEN_MSKENn_Pos)

#define PWM_MSKEN_MSKEN0_Pos             (0)

#define PWM_MSKEN_MSKEN0_Msk             (0x1ul << PWM_MSKEN_MSKEN0_Pos)

#define PWM_MSKEN_MSKEN1_Pos             (1)

#define PWM_MSKEN_MSKEN1_Msk             (0x1ul << PWM_MSKEN_MSKEN1_Pos)

#define PWM_MSKEN_MSKEN2_Pos             (2)

#define PWM_MSKEN_MSKEN2_Msk             (0x1ul << PWM_MSKEN_MSKEN2_Pos)

#define PWM_MSKEN_MSKEN3_Pos             (3)

#define PWM_MSKEN_MSKEN3_Msk             (0x1ul << PWM_MSKEN_MSKEN3_Pos)

#define PWM_MSKEN_MSKEN4_Pos             (4)

#define PWM_MSKEN_MSKEN4_Msk             (0x1ul << PWM_MSKEN_MSKEN4_Pos)

#define PWM_MSKEN_MSKEN5_Pos             (5)

#define PWM_MSKEN_MSKEN5_Msk             (0x1ul << PWM_MSKEN_MSKEN5_Pos)

#define PWM_MSK_MSKDATn_Pos              (0)

#define PWM_MSK_MSKDATn_Msk              (0x3ful << PWM_MSK_MSKDATn_Pos)

#define PWM_MSK_MSKDAT0_Pos              (0)

#define PWM_MSK_MSKDAT0_Msk              (0x1ul << PWM_MSK_MSKDAT0_Pos)

#define PWM_MSK_MSKDAT1_Pos              (1)

#define PWM_MSK_MSKDAT1_Msk              (0x1ul << PWM_MSK_MSKDAT1_Pos)

#define PWM_MSK_MSKDAT2_Pos              (2)

#define PWM_MSK_MSKDAT2_Msk              (0x1ul << PWM_MSK_MSKDAT2_Pos)

#define PWM_MSK_MSKDAT3_Pos              (3)

#define PWM_MSK_MSKDAT3_Msk              (0x1ul << PWM_MSK_MSKDAT3_Pos)

#define PWM_MSK_MSKDAT4_Pos              (4)

#define PWM_MSK_MSKDAT4_Msk              (0x1ul << PWM_MSK_MSKDAT4_Pos)

#define PWM_MSK_MSKDAT5_Pos              (5)

#define PWM_MSK_MSKDAT5_Msk              (0x1ul << PWM_MSK_MSKDAT5_Pos)

#define PWM_BNF_BRK0NFEN_Pos             (0)

#define PWM_BNF_BRK0NFEN_Msk             (0x1ul << PWM_BNF_BRK0NFEN_Pos)

#define PWM_BNF_BRK0NFSEL_Pos            (1)

#define PWM_BNF_BRK0NFSEL_Msk            (0x7ul << PWM_BNF_BRK0NFSEL_Pos)

#define PWM_BNF_BRK0FCNT_Pos             (4)

#define PWM_BNF_BRK0FCNT_Msk             (0x7ul << PWM_BNF_BRK0FCNT_Pos)

#define PWM_BNF_BRK0PINV_Pos             (7)

#define PWM_BNF_BRK0PINV_Msk             (0x1ul << PWM_BNF_BRK0PINV_Pos)

#define PWM_BNF_BRK1NFEN_Pos             (8)

#define PWM_BNF_BRK1NFEN_Msk             (0x1ul << PWM_BNF_BRK1NFEN_Pos)

#define PWM_BNF_BRK1NFSEL_Pos            (9)

#define PWM_BNF_BRK1NFSEL_Msk            (0x7ul << PWM_BNF_BRK1NFSEL_Pos)

#define PWM_BNF_BRK1FCNT_Pos             (12)

#define PWM_BNF_BRK1FCNT_Msk             (0x7ul << PWM_BNF_BRK1FCNT_Pos)

#define PWM_BNF_BRK1PINV_Pos             (15)

#define PWM_BNF_BRK1PINV_Msk             (0x1ul << PWM_BNF_BRK1PINV_Pos)

#define PWM_BNF_BK0SRC_Pos               (16)

#define PWM_BNF_BK0SRC_Msk               (0x1ul << PWM_BNF_BK0SRC_Pos)

#define PWM_BNF_BK1SRC_Pos               (24)

#define PWM_BNF_BK1SRC_Msk               (0x1ul << PWM_BNF_BK1SRC_Pos)

#define PWM_FAILBRK_CSSBRKEN_Pos         (0)

#define PWM_FAILBRK_CSSBRKEN_Msk         (0x1ul << PWM_FAILBRK_CSSBRKEN_Pos)

#define PWM_FAILBRK_BODBRKEN_Pos         (1)

#define PWM_FAILBRK_BODBRKEN_Msk         (0x1ul << PWM_FAILBRK_BODBRKEN_Pos)

#define PWM_FAILBRK_CORBRKEN_Pos         (3)

#define PWM_FAILBRK_CORBRKEN_Msk         (0x1ul << PWM_FAILBRK_CORBRKEN_Pos)

#define PWM_BRKCTL0_1_BRKP0EEN_Pos       (4)

#define PWM_BRKCTL0_1_BRKP0EEN_Msk       (0x1ul << PWM_BRKCTL0_1_BRKP0EEN_Pos)

#define PWM_BRKCTL0_1_BRKP1EEN_Pos       (5)

#define PWM_BRKCTL0_1_BRKP1EEN_Msk       (0x1ul << PWM_BRKCTL0_1_BRKP1EEN_Pos)

#define PWM_BRKCTL0_1_SYSEBEN_Pos        (7)

#define PWM_BRKCTL0_1_SYSEBEN_Msk        (0x1ul << PWM_BRKCTL0_1_SYSEBEN_Pos)

#define PWM_BRKCTL0_1_BRKP0LEN_Pos       (12)

#define PWM_BRKCTL0_1_BRKP0LEN_Msk       (0x1ul << PWM_BRKCTL0_1_BRKP0LEN_Pos)

#define PWM_BRKCTL0_1_BRKP1LEN_Pos       (13)

#define PWM_BRKCTL0_1_BRKP1LEN_Msk       (0x1ul << PWM_BRKCTL0_1_BRKP1LEN_Pos)

#define PWM_BRKCTL0_1_SYSLBEN_Pos        (15)

#define PWM_BRKCTL0_1_SYSLBEN_Msk        (0x1ul << PWM_BRKCTL0_1_SYSLBEN_Pos)

#define PWM_BRKCTL0_1_BRKAEVEN_Pos       (16)

#define PWM_BRKCTL0_1_BRKAEVEN_Msk       (0x3ul << PWM_BRKCTL0_1_BRKAEVEN_Pos)

#define PWM_BRKCTL0_1_BRKAODD_Pos        (18)

#define PWM_BRKCTL0_1_BRKAODD_Msk        (0x3ul << PWM_BRKCTL0_1_BRKAODD_Pos)

#define PWM_BRKCTL2_3_BRKP0EEN_Pos       (4)

#define PWM_BRKCTL2_3_BRKP0EEN_Msk       (0x1ul << PWM_BRKCTL2_3_BRKP0EEN_Pos)

#define PWM_BRKCTL2_3_BRKP1EEN_Pos       (5)

#define PWM_BRKCTL2_3_BRKP1EEN_Msk       (0x1ul << PWM_BRKCTL2_3_BRKP1EEN_Pos)

#define PWM_BRKCTL2_3_SYSEBEN_Pos        (7)

#define PWM_BRKCTL2_3_SYSEBEN_Msk        (0x1ul << PWM_BRKCTL2_3_SYSEBEN_Pos)

#define PWM_BRKCTL2_3_BRKP0LEN_Pos       (12)

#define PWM_BRKCTL2_3_BRKP0LEN_Msk       (0x1ul << PWM_BRKCTL2_3_BRKP0LEN_Pos)

#define PWM_BRKCTL2_3_BRKP1LEN_Pos       (13)

#define PWM_BRKCTL2_3_BRKP1LEN_Msk       (0x1ul << PWM_BRKCTL2_3_BRKP1LEN_Pos)

#define PWM_BRKCTL2_3_SYSLBEN_Pos        (15)

#define PWM_BRKCTL2_3_SYSLBEN_Msk        (0x1ul << PWM_BRKCTL2_3_SYSLBEN_Pos)

#define PWM_BRKCTL2_3_BRKAEVEN_Pos       (16)

#define PWM_BRKCTL2_3_BRKAEVEN_Msk       (0x3ul << PWM_BRKCTL2_3_BRKAEVEN_Pos)

#define PWM_BRKCTL2_3_BRKAODD_Pos        (18)

#define PWM_BRKCTL2_3_BRKAODD_Msk        (0x3ul << PWM_BRKCTL2_3_BRKAODD_Pos)

#define PWM_BRKCTL4_5_BRKP0EEN_Pos       (4)

#define PWM_BRKCTL4_5_BRKP0EEN_Msk       (0x1ul << PWM_BRKCTL4_5_BRKP0EEN_Pos)

#define PWM_BRKCTL4_5_BRKP1EEN_Pos       (5)

#define PWM_BRKCTL4_5_BRKP1EEN_Msk       (0x1ul << PWM_BRKCTL4_5_BRKP1EEN_Pos)

#define PWM_BRKCTL4_5_SYSEBEN_Pos        (7)

#define PWM_BRKCTL4_5_SYSEBEN_Msk        (0x1ul << PWM_BRKCTL4_5_SYSEBEN_Pos)

#define PWM_BRKCTL4_5_BRKP0LEN_Pos       (12)

#define PWM_BRKCTL4_5_BRKP0LEN_Msk       (0x1ul << PWM_BRKCTL4_5_BRKP0LEN_Pos)

#define PWM_BRKCTL4_5_BRKP1LEN_Pos       (13)

#define PWM_BRKCTL4_5_BRKP1LEN_Msk       (0x1ul << PWM_BRKCTL4_5_BRKP1LEN_Pos)

#define PWM_BRKCTL4_5_SYSLBEN_Pos        (15)

#define PWM_BRKCTL4_5_SYSLBEN_Msk        (0x1ul << PWM_BRKCTL4_5_SYSLBEN_Pos)

#define PWM_BRKCTL4_5_BRKAEVEN_Pos       (16)

#define PWM_BRKCTL4_5_BRKAEVEN_Msk       (0x3ul << PWM_BRKCTL4_5_BRKAEVEN_Pos)

#define PWM_BRKCTL4_5_BRKAODD_Pos        (18)

#define PWM_BRKCTL4_5_BRKAODD_Msk        (0x3ul << PWM_BRKCTL4_5_BRKAODD_Pos)

#define PWM_POLCTL_PINVn_Pos             (0)

#define PWM_POLCTL_PINVn_Msk             (0x3ful << PWM_POLCTL_PINVn_Pos)

#define PWM_POLCTL_PINV0_Pos             (0)

#define PWM_POLCTL_PINV0_Msk             (0x1ul << PWM_POLCTL_PINV0_Pos)

#define PWM_POLCTL_PINV1_Pos             (1)

#define PWM_POLCTL_PINV1_Msk             (0x1ul << PWM_POLCTL_PINV1_Pos)

#define PWM_POLCTL_PINV2_Pos             (2)

#define PWM_POLCTL_PINV2_Msk             (0x1ul << PWM_POLCTL_PINV2_Pos)

#define PWM_POLCTL_PINV3_Pos             (3)

#define PWM_POLCTL_PINV3_Msk             (0x1ul << PWM_POLCTL_PINV3_Pos)

#define PWM_POLCTL_PINV4_Pos             (4)

#define PWM_POLCTL_PINV4_Msk             (0x1ul << PWM_POLCTL_PINV4_Pos)

#define PWM_POLCTL_PINV5_Pos             (5)

#define PWM_POLCTL_PINV5_Msk             (0x1ul << PWM_POLCTL_PINV5_Pos)

#define PWM_POEN_POENn_Pos               (0)

#define PWM_POEN_POENn_Msk               (0x3ful << PWM_POEN_POENn_Pos)

#define PWM_POEN_POEN0_Pos               (0)

#define PWM_POEN_POEN0_Msk               (0x1ul << PWM_POEN_POEN0_Pos)

#define PWM_POEN_POEN1_Pos               (1)

#define PWM_POEN_POEN1_Msk               (0x1ul << PWM_POEN_POEN1_Pos)

#define PWM_POEN_POEN2_Pos               (2)

#define PWM_POEN_POEN2_Msk               (0x1ul << PWM_POEN_POEN2_Pos)

#define PWM_POEN_POEN3_Pos               (3)

#define PWM_POEN_POEN3_Msk               (0x1ul << PWM_POEN_POEN3_Pos)

#define PWM_POEN_POEN4_Pos               (4)

#define PWM_POEN_POEN4_Msk               (0x1ul << PWM_POEN_POEN4_Pos)

#define PWM_POEN_POEN5_Pos               (5)

#define PWM_POEN_POEN5_Msk               (0x1ul << PWM_POEN_POEN5_Pos)

#define PWM_SWBRK_BRKETRGn_Pos           (0)

#define PWM_SWBRK_BRKETRGn_Msk           (0x7ul << PWM_SWBRK_BRKETRGn_Pos)

#define PWM_SWBRK_BRKETRG0_Pos           (0)

#define PWM_SWBRK_BRKETRG0_Msk           (0x1ul << PWM_SWBRK_BRKETRG0_Pos)

#define PWM_SWBRK_BRKETRG2_Pos           (1)

#define PWM_SWBRK_BRKETRG2_Msk           (0x1ul << PWM_SWBRK_BRKETRG2_Pos)

#define PWM_SWBRK_BRKETRG4_Pos           (2)

#define PWM_SWBRK_BRKETRG4_Msk           (0x1ul << PWM_SWBRK_BRKETRG4_Pos)

#define PWM_SWBRK_BRKLTRGn_Pos           (8)

#define PWM_SWBRK_BRKLTRGn_Msk           (0x7ul << PWM_SWBRK_BRKLTRGn_Pos)

#define PWM_SWBRK_BRKLTRG0_Pos           (8)

#define PWM_SWBRK_BRKLTRG0_Msk           (0x1ul << PWM_SWBRK_BRKLTRG0_Pos)

#define PWM_SWBRK_BRKLTRG2_Pos           (9)

#define PWM_SWBRK_BRKLTRG2_Msk           (0x1ul << PWM_SWBRK_BRKLTRG2_Pos)

#define PWM_SWBRK_BRKLTRG4_Pos           (10)

#define PWM_SWBRK_BRKLTRG4_Msk           (0x1ul << PWM_SWBRK_BRKLTRG4_Pos)

#define PWM_INTEN0_ZIENn_Pos             (0)

#define PWM_INTEN0_ZIENn_Msk             (0x3ful << PWM_INTEN0_ZIENn_Pos)

#define PWM_INTEN0_ZIEN0_Pos             (0)

#define PWM_INTEN0_ZIEN0_Msk             (0x1ul << PWM_INTEN0_ZIEN0_Pos)

#define PWM_INTEN0_ZIEN1_Pos             (1)

#define PWM_INTEN0_ZIEN1_Msk             (0x1ul << PWM_INTEN0_ZIEN1_Pos)

#define PWM_INTEN0_ZIEN2_Pos             (2)

#define PWM_INTEN0_ZIEN2_Msk             (0x1ul << PWM_INTEN0_ZIEN2_Pos)

#define PWM_INTEN0_ZIEN3_Pos             (3)

#define PWM_INTEN0_ZIEN3_Msk             (0x1ul << PWM_INTEN0_ZIEN3_Pos)

#define PWM_INTEN0_ZIEN4_Pos             (4)

#define PWM_INTEN0_ZIEN4_Msk             (0x1ul << PWM_INTEN0_ZIEN4_Pos)

#define PWM_INTEN0_ZIEN5_Pos             (5)

#define PWM_INTEN0_ZIEN5_Msk             (0x1ul << PWM_INTEN0_ZIEN5_Pos)

#define PWM_INTEN0_IFAIEN0_1_Pos         (7)

#define PWM_INTEN0_IFAIEN0_1_Msk         (0x1ul << PWM_INTEN0_IFAIEN0_1_Pos)

#define PWM_INTEN0_PIENn_Pos             (8)

#define PWM_INTEN0_PIENn_Msk             (0x3ful << PWM_INTEN0_PIENn_Pos)

#define PWM_INTEN0_PIEN0_Pos             (8)

#define PWM_INTEN0_PIEN0_Msk             (0x1ul << PWM_INTEN0_PIEN0_Pos)

#define PWM_INTEN0_PIEN1_Pos             (9)

#define PWM_INTEN0_PIEN1_Msk             (0x1ul << PWM_INTEN0_PIEN1_Pos)

#define PWM_INTEN0_PIEN2_Pos             (10)

#define PWM_INTEN0_PIEN2_Msk             (0x1ul << PWM_INTEN0_PIEN2_Pos)

#define PWM_INTEN0_PIEN3_Pos             (11)

#define PWM_INTEN0_PIEN3_Msk             (0x1ul << PWM_INTEN0_PIEN3_Pos)

#define PWM_INTEN0_PIEN4_Pos             (12)

#define PWM_INTEN0_PIEN4_Msk             (0x1ul << PWM_INTEN0_PIEN4_Pos)

#define PWM_INTEN0_PIEN5_Pos             (13)

#define PWM_INTEN0_PIEN5_Msk             (0x1ul << PWM_INTEN0_PIEN5_Pos)

#define PWM_INTEN0_IFAIEN2_3_Pos         (15)

#define PWM_INTEN0_IFAIEN2_3_Msk         (0x1ul << PWM_INTEN0_IFAIEN2_3_Pos)

#define PWM_INTEN0_CMPUIENn_Pos          (16)

#define PWM_INTEN0_CMPUIENn_Msk          (0x3ful << PWM_INTEN0_CMPUIENn_Pos)

#define PWM_INTEN0_CMPUIEN0_Pos          (16)

#define PWM_INTEN0_CMPUIEN0_Msk          (0x1ul << PWM_INTEN0_CMPUIEN0_Pos)

#define PWM_INTEN0_CMPUIEN1_Pos          (17)

#define PWM_INTEN0_CMPUIEN1_Msk          (0x1ul << PWM_INTEN0_CMPUIEN1_Pos)

#define PWM_INTEN0_CMPUIEN2_Pos          (18)

#define PWM_INTEN0_CMPUIEN2_Msk          (0x1ul << PWM_INTEN0_CMPUIEN2_Pos)

#define PWM_INTEN0_CMPUIEN3_Pos          (19)

#define PWM_INTEN0_CMPUIEN3_Msk          (0x1ul << PWM_INTEN0_CMPUIEN3_Pos)

#define PWM_INTEN0_CMPUIEN4_Pos          (20)

#define PWM_INTEN0_CMPUIEN4_Msk          (0x1ul << PWM_INTEN0_CMPUIEN4_Pos)

#define PWM_INTEN0_CMPUIEN5_Pos          (21)

#define PWM_INTEN0_CMPUIEN5_Msk          (0x1ul << PWM_INTEN0_CMPUIEN5_Pos)

#define PWM_INTEN0_IFAIEN4_5_Pos         (23)

#define PWM_INTEN0_IFAIEN4_5_Msk         (0x1ul << PWM_INTEN0_IFAIEN4_5_Pos)

#define PWM_INTEN0_CMPDIENn_Pos          (24)

#define PWM_INTEN0_CMPDIENn_Msk          (0x3ful << PWM_INTEN0_CMPDIENn_Pos)

#define PWM_INTEN0_CMPDIEN0_Pos          (24)

#define PWM_INTEN0_CMPDIEN0_Msk          (0x1ul << PWM_INTEN0_CMPDIEN0_Pos)

#define PWM_INTEN0_CMPDIEN1_Pos          (25)

#define PWM_INTEN0_CMPDIEN1_Msk          (0x1ul << PWM_INTEN0_CMPDIEN1_Pos)

#define PWM_INTEN0_CMPDIEN2_Pos          (26)

#define PWM_INTEN0_CMPDIEN2_Msk          (0x1ul << PWM_INTEN0_CMPDIEN2_Pos)

#define PWM_INTEN0_CMPDIEN3_Pos          (27)

#define PWM_INTEN0_CMPDIEN3_Msk          (0x1ul << PWM_INTEN0_CMPDIEN3_Pos)

#define PWM_INTEN0_CMPDIEN4_Pos          (28)

#define PWM_INTEN0_CMPDIEN4_Msk          (0x1ul << PWM_INTEN0_CMPDIEN4_Pos)

#define PWM_INTEN0_CMPDIEN5_Pos          (29)

#define PWM_INTEN0_CMPDIEN5_Msk          (0x1ul << PWM_INTEN0_CMPDIEN5_Pos)

#define PWM_INTEN1_BRKEIEN0_1_Pos        (0)

#define PWM_INTEN1_BRKEIEN0_1_Msk        (0x1ul << PWM_INTEN1_BRKEIEN0_1_Pos)

#define PWM_INTEN1_BRKEIEN2_3_Pos        (1)

#define PWM_INTEN1_BRKEIEN2_3_Msk        (0x1ul << PWM_INTEN1_BRKEIEN2_3_Pos)

#define PWM_INTEN1_BRKEIEN4_5_Pos        (2)

#define PWM_INTEN1_BRKEIEN4_5_Msk        (0x1ul << PWM_INTEN1_BRKEIEN4_5_Pos)

#define PWM_INTEN1_BRKLIEN0_1_Pos        (8)

#define PWM_INTEN1_BRKLIEN0_1_Msk        (0x1ul << PWM_INTEN1_BRKLIEN0_1_Pos)

#define PWM_INTEN1_BRKLIEN2_3_Pos        (9)

#define PWM_INTEN1_BRKLIEN2_3_Msk        (0x1ul << PWM_INTEN1_BRKLIEN2_3_Pos)

#define PWM_INTEN1_BRKLIEN4_5_Pos        (10)

#define PWM_INTEN1_BRKLIEN4_5_Msk        (0x1ul << PWM_INTEN1_BRKLIEN4_5_Pos)

#define PWM_INTSTS0_ZIFn_Pos             (0)

#define PWM_INTSTS0_ZIFn_Msk             (0x3ful << PWM_INTSTS0_ZIFn_Pos)

#define PWM_INTSTS0_ZIF0_Pos             (0)

#define PWM_INTSTS0_ZIF0_Msk             (0x1ul << PWM_INTSTS0_ZIF0_Pos)

#define PWM_INTSTS0_ZIF1_Pos             (1)

#define PWM_INTSTS0_ZIF1_Msk             (0x1ul << PWM_INTSTS0_ZIF1_Pos)

#define PWM_INTSTS0_ZIF2_Pos             (2)

#define PWM_INTSTS0_ZIF2_Msk             (0x1ul << PWM_INTSTS0_ZIF2_Pos)

#define PWM_INTSTS0_ZIF3_Pos             (3)

#define PWM_INTSTS0_ZIF3_Msk             (0x1ul << PWM_INTSTS0_ZIF3_Pos)

#define PWM_INTSTS0_ZIF4_Pos             (4)

#define PWM_INTSTS0_ZIF4_Msk             (0x1ul << PWM_INTSTS0_ZIF4_Pos)

#define PWM_INTSTS0_ZIF5_Pos             (5)

#define PWM_INTSTS0_ZIF5_Msk             (0x1ul << PWM_INTSTS0_ZIF5_Pos)

#define PWM_INTSTS0_IFAIF0_1_Pos         (7)

#define PWM_INTSTS0_IFAIF0_1_Msk         (0x1ul << PWM_INTSTS0_IFAIF0_1_Pos)

#define PWM_INTSTS0_PIFn_Pos             (8)

#define PWM_INTSTS0_PIFn_Msk             (0x3ful << PWM_INTSTS0_PIFn_Pos)

#define PWM_INTSTS0_PIF0_Pos             (8)

#define PWM_INTSTS0_PIF0_Msk             (0x1ul << PWM_INTSTS0_PIF0_Pos)

#define PWM_INTSTS0_PIF1_Pos             (9)

#define PWM_INTSTS0_PIF1_Msk             (0x1ul << PWM_INTSTS0_PIF1_Pos)

#define PWM_INTSTS0_PIF2_Pos             (10)

#define PWM_INTSTS0_PIF2_Msk             (0x1ul << PWM_INTSTS0_PIF2_Pos)

#define PWM_INTSTS0_PIF3_Pos             (11)

#define PWM_INTSTS0_PIF3_Msk             (0x1ul << PWM_INTSTS0_PIF3_Pos)

#define PWM_INTSTS0_PIF4_Pos             (12)

#define PWM_INTSTS0_PIF4_Msk             (0x1ul << PWM_INTSTS0_PIF4_Pos)

#define PWM_INTSTS0_PIF5_Pos             (13)

#define PWM_INTSTS0_PIF5_Msk             (0x1ul << PWM_INTSTS0_PIF5_Pos)

#define PWM_INTSTS0_IFAIF2_3_Pos         (15)

#define PWM_INTSTS0_IFAIF2_3_Msk         (0x1ul << PWM_INTSTS0_IFAIF2_3_Pos)

#define PWM_INTSTS0_CMPUIFn_Pos          (16)

#define PWM_INTSTS0_CMPUIFn_Msk          (0x3ful << PWM_INTSTS0_CMPUIFn_Pos)

#define PWM_INTSTS0_CMPUIF0_Pos          (16)

#define PWM_INTSTS0_CMPUIF0_Msk          (0x1ul << PWM_INTSTS0_CMPUIF0_Pos)

#define PWM_INTSTS0_CMPUIF1_Pos          (17)

#define PWM_INTSTS0_CMPUIF1_Msk          (0x1ul << PWM_INTSTS0_CMPUIF1_Pos)

#define PWM_INTSTS0_CMPUIF2_Pos          (18)

#define PWM_INTSTS0_CMPUIF2_Msk          (0x1ul << PWM_INTSTS0_CMPUIF2_Pos)

#define PWM_INTSTS0_CMPUIF3_Pos          (19)

#define PWM_INTSTS0_CMPUIF3_Msk          (0x1ul << PWM_INTSTS0_CMPUIF3_Pos)

#define PWM_INTSTS0_CMPUIF4_Pos          (20)

#define PWM_INTSTS0_CMPUIF4_Msk          (0x1ul << PWM_INTSTS0_CMPUIF4_Pos)

#define PWM_INTSTS0_CMPUIF5_Pos          (21)

#define PWM_INTSTS0_CMPUIF5_Msk          (0x1ul << PWM_INTSTS0_CMPUIF5_Pos)

#define PWM_INTSTS0_IFAIF4_5_Pos         (23)

#define PWM_INTSTS0_IFAIF4_5_Msk         (0x1ul << PWM_INTSTS0_IFAIF4_5_Pos)

#define PWM_INTSTS0_CMPDIFn_Pos          (24)

#define PWM_INTSTS0_CMPDIFn_Msk          (0x3ful << PWM_INTSTS0_CMPDIFn_Pos)

#define PWM_INTSTS0_CMPDIF0_Pos          (24)

#define PWM_INTSTS0_CMPDIF0_Msk          (0x1ul << PWM_INTSTS0_CMPDIF0_Pos)

#define PWM_INTSTS0_CMPDIF1_Pos          (25)

#define PWM_INTSTS0_CMPDIF1_Msk          (0x1ul << PWM_INTSTS0_CMPDIF1_Pos)

#define PWM_INTSTS0_CMPDIF2_Pos          (26)

#define PWM_INTSTS0_CMPDIF2_Msk          (0x1ul << PWM_INTSTS0_CMPDIF2_Pos)

#define PWM_INTSTS0_CMPDIF3_Pos          (27)

#define PWM_INTSTS0_CMPDIF3_Msk          (0x1ul << PWM_INTSTS0_CMPDIF3_Pos)

#define PWM_INTSTS0_CMPDIF4_Pos          (28)

#define PWM_INTSTS0_CMPDIF4_Msk          (0x1ul << PWM_INTSTS0_CMPDIF4_Pos)

#define PWM_INTSTS0_CMPDIF5_Pos          (29)

#define PWM_INTSTS0_CMPDIF5_Msk          (0x1ul << PWM_INTSTS0_CMPDIF5_Pos)

#define PWM_INTSTS1_BRKEIFn_Pos          (0)

#define PWM_INTSTS1_BRKEIFn_Msk          (0x3ful << PWM_INTSTS1_BRKEIFn_Pos)

#define PWM_INTSTS1_BRKEIF0_Pos          (0)

#define PWM_INTSTS1_BRKEIF0_Msk          (0x1ul << PWM_INTSTS1_BRKEIF0_Pos)

#define PWM_INTSTS1_BRKEIF1_Pos          (1)

#define PWM_INTSTS1_BRKEIF1_Msk          (0x1ul << PWM_INTSTS1_BRKEIF1_Pos)

#define PWM_INTSTS1_BRKEIF2_Pos          (2)

#define PWM_INTSTS1_BRKEIF2_Msk          (0x1ul << PWM_INTSTS1_BRKEIF2_Pos)

#define PWM_INTSTS1_BRKEIF3_Pos          (3)

#define PWM_INTSTS1_BRKEIF3_Msk          (0x1ul << PWM_INTSTS1_BRKEIF3_Pos)

#define PWM_INTSTS1_BRKEIF4_Pos          (4)

#define PWM_INTSTS1_BRKEIF4_Msk          (0x1ul << PWM_INTSTS1_BRKEIF4_Pos)

#define PWM_INTSTS1_BRKEIF5_Pos          (5)

#define PWM_INTSTS1_BRKEIF5_Msk          (0x1ul << PWM_INTSTS1_BRKEIF5_Pos)

#define PWM_INTSTS1_BRKLIFn_Pos          (8)

#define PWM_INTSTS1_BRKLIFn_Msk          (0x3ful << PWM_INTSTS1_BRKLIFn_Pos)

#define PWM_INTSTS1_BRKLIF0_Pos          (8)

#define PWM_INTSTS1_BRKLIF0_Msk          (0x1ul << PWM_INTSTS1_BRKLIF0_Pos)

#define PWM_INTSTS1_BRKLIF1_Pos          (9)

#define PWM_INTSTS1_BRKLIF1_Msk          (0x1ul << PWM_INTSTS1_BRKLIF1_Pos)

#define PWM_INTSTS1_BRKLIF2_Pos          (10)

#define PWM_INTSTS1_BRKLIF2_Msk          (0x1ul << PWM_INTSTS1_BRKLIF2_Pos)

#define PWM_INTSTS1_BRKLIF3_Pos          (11)

#define PWM_INTSTS1_BRKLIF3_Msk          (0x1ul << PWM_INTSTS1_BRKLIF3_Pos)

#define PWM_INTSTS1_BRKLIF4_Pos          (12)

#define PWM_INTSTS1_BRKLIF4_Msk          (0x1ul << PWM_INTSTS1_BRKLIF4_Pos)

#define PWM_INTSTS1_BRKLIF5_Pos          (13)

#define PWM_INTSTS1_BRKLIF5_Msk          (0x1ul << PWM_INTSTS1_BRKLIF5_Pos)

#define PWM_INTSTS1_BRKESTS0_Pos         (16)

#define PWM_INTSTS1_BRKESTS0_Msk         (0x1ul << PWM_INTSTS1_BRKESTS0_Pos)

#define PWM_INTSTS1_BRKESTS1_Pos         (17)

#define PWM_INTSTS1_BRKESTS1_Msk         (0x1ul << PWM_INTSTS1_BRKESTS1_Pos)

#define PWM_INTSTS1_BRKESTS2_Pos         (18)

#define PWM_INTSTS1_BRKESTS2_Msk         (0x1ul << PWM_INTSTS1_BRKESTS2_Pos)

#define PWM_INTSTS1_BRKESTS3_Pos         (19)

#define PWM_INTSTS1_BRKESTS3_Msk         (0x1ul << PWM_INTSTS1_BRKESTS3_Pos)

#define PWM_INTSTS1_BRKESTS4_Pos         (20)

#define PWM_INTSTS1_BRKESTS4_Msk         (0x1ul << PWM_INTSTS1_BRKESTS4_Pos)

#define PWM_INTSTS1_BRKESTS5_Pos         (21)

#define PWM_INTSTS1_BRKESTS5_Msk         (0x1ul << PWM_INTSTS1_BRKESTS5_Pos)

#define PWM_INTSTS1_BRKLSTS0_Pos         (24)

#define PWM_INTSTS1_BRKLSTS0_Msk         (0x1ul << PWM_INTSTS1_BRKLSTS0_Pos)

#define PWM_INTSTS1_BRKLSTS1_Pos         (25)

#define PWM_INTSTS1_BRKLSTS1_Msk         (0x1ul << PWM_INTSTS1_BRKLSTS1_Pos)

#define PWM_INTSTS1_BRKLSTS2_Pos         (26)

#define PWM_INTSTS1_BRKLSTS2_Msk         (0x1ul << PWM_INTSTS1_BRKLSTS2_Pos)

#define PWM_INTSTS1_BRKLSTS3_Pos         (27)

#define PWM_INTSTS1_BRKLSTS3_Msk         (0x1ul << PWM_INTSTS1_BRKLSTS3_Pos)

#define PWM_INTSTS1_BRKLSTS4_Pos         (28)

#define PWM_INTSTS1_BRKLSTS4_Msk         (0x1ul << PWM_INTSTS1_BRKLSTS4_Pos)

#define PWM_INTSTS1_BRKLSTS5_Pos         (29)

#define PWM_INTSTS1_BRKLSTS5_Msk         (0x1ul << PWM_INTSTS1_BRKLSTS5_Pos)

#define PWM_IFA_IFCNT0_1_Pos             (0)

#define PWM_IFA_IFCNT0_1_Msk             (0xful << PWM_IFA_IFCNT0_1_Pos)

#define PWM_IFA_IFSEL0_1_Pos             (4)

#define PWM_IFA_IFSEL0_1_Msk             (0x7ul << PWM_IFA_IFSEL0_1_Pos)

#define PWM_IFA_IFAEN0_1_Pos             (7)

#define PWM_IFA_IFAEN0_1_Msk             (0x1ul << PWM_IFA_IFAEN0_1_Pos)

#define PWM_IFA_IFCNT2_3_Pos             (8)

#define PWM_IFA_IFCNT2_3_Msk             (0xful << PWM_IFA_IFCNT2_3_Pos)

#define PWM_IFA_IFSEL2_3_Pos             (12)

#define PWM_IFA_IFSEL2_3_Msk             (0x7ul << PWM_IFA_IFSEL2_3_Pos)

#define PWM_IFA_IFAEN2_3_Pos             (15)

#define PWM_IFA_IFAEN2_3_Msk             (0x1ul << PWM_IFA_IFAEN2_3_Pos)

#define PWM_IFA_IFCNT4_5_Pos             (16)

#define PWM_IFA_IFCNT4_5_Msk             (0xful << PWM_IFA_IFCNT4_5_Pos)

#define PWM_IFA_IFSEL4_5_Pos             (20)

#define PWM_IFA_IFSEL4_5_Msk             (0x7ul << PWM_IFA_IFSEL4_5_Pos)

#define PWM_IFA_IFAEN4_5_Pos             (23)

#define PWM_IFA_IFAEN4_5_Msk             (0x1ul << PWM_IFA_IFAEN4_5_Pos)

#define PWM_EADCTS0_TRGSEL0_Pos          (0)

#define PWM_EADCTS0_TRGSEL0_Msk          (0xful << PWM_EADCTS0_TRGSEL0_Pos)

#define PWM_EADCTS0_TRGEN0_Pos           (7)

#define PWM_EADCTS0_TRGEN0_Msk           (0x1ul << PWM_EADCTS0_TRGEN0_Pos)

#define PWM_EADCTS0_TRGSEL1_Pos          (8)

#define PWM_EADCTS0_TRGSEL1_Msk          (0xful << PWM_EADCTS0_TRGSEL1_Pos)

#define PWM_EADCTS0_TRGEN1_Pos           (15)

#define PWM_EADCTS0_TRGEN1_Msk           (0x1ul << PWM_EADCTS0_TRGEN1_Pos)

#define PWM_EADCTS0_TRGSEL2_Pos          (16)

#define PWM_EADCTS0_TRGSEL2_Msk          (0xful << PWM_EADCTS0_TRGSEL2_Pos)

#define PWM_EADCTS0_TRGEN2_Pos           (23)

#define PWM_EADCTS0_TRGEN2_Msk           (0x1ul << PWM_EADCTS0_TRGEN2_Pos)

#define PWM_EADCTS0_TRGSEL3_Pos          (24)

#define PWM_EADCTS0_TRGSEL3_Msk          (0xful << PWM_EADCTS0_TRGSEL3_Pos)

#define PWM_EADCTS0_TRGEN3_Pos           (31)

#define PWM_EADCTS0_TRGEN3_Msk           (0x1ul << PWM_EADCTS0_TRGEN3_Pos)

#define PWM_EADCTS1_TRGSEL4_Pos          (0)

#define PWM_EADCTS1_TRGSEL4_Msk          (0xful << PWM_EADCTS1_TRGSEL4_Pos)

#define PWM_EADCTS1_TRGEN4_Pos           (7)

#define PWM_EADCTS1_TRGEN4_Msk           (0x1ul << PWM_EADCTS1_TRGEN4_Pos)

#define PWM_EADCTS1_TRGSEL5_Pos          (8)

#define PWM_EADCTS1_TRGSEL5_Msk          (0xful << PWM_EADCTS1_TRGSEL5_Pos)

#define PWM_EADCTS1_TRGEN5_Pos           (15)

#define PWM_EADCTS1_TRGEN5_Msk           (0x1ul << PWM_EADCTS1_TRGEN5_Pos)

#define PWM_FTCMPDAT0_1_FTCMP_Pos        (0)

#define PWM_FTCMPDAT0_1_FTCMP_Msk        (0xfffful << PWM_FTCMPDAT0_1_FTCMP_Pos)

#define PWM_FTCMPDAT2_3_FTCMP_Pos        (0)

#define PWM_FTCMPDAT2_3_FTCMP_Msk        (0xfffful << PWM_FTCMPDAT2_3_FTCMP_Pos)

#define PWM_FTCMPDAT4_5_FTCMP_Pos        (0)

#define PWM_FTCMPDAT4_5_FTCMP_Msk        (0xfffful << PWM_FTCMPDAT4_5_FTCMP_Pos)

#define PWM_SSCTL_SSENn_Pos              (0)

#define PWM_SSCTL_SSENn_Msk              (0x3ful << PWM_SSCTL_SSENn_Pos)

#define PWM_SSCTL_SSEN0_Pos              (0)

#define PWM_SSCTL_SSEN0_Msk              (0x1ul << PWM_SSCTL_SSEN0_Pos)

#define PWM_SSCTL_SSEN1_Pos              (1)

#define PWM_SSCTL_SSEN1_Msk              (0x1ul << PWM_SSCTL_SSEN1_Pos)

#define PWM_SSCTL_SSEN2_Pos              (2)

#define PWM_SSCTL_SSEN2_Msk              (0x1ul << PWM_SSCTL_SSEN2_Pos)

#define PWM_SSCTL_SSEN3_Pos              (3)

#define PWM_SSCTL_SSEN3_Msk              (0x1ul << PWM_SSCTL_SSEN3_Pos)

#define PWM_SSCTL_SSEN4_Pos              (4)

#define PWM_SSCTL_SSEN4_Msk              (0x1ul << PWM_SSCTL_SSEN4_Pos)

#define PWM_SSCTL_SSEN5_Pos              (5)

#define PWM_SSCTL_SSEN5_Msk              (0x1ul << PWM_SSCTL_SSEN5_Pos)

#define PWM_SSTRG_CNTSEN_Pos             (0)

#define PWM_SSTRG_CNTSEN_Msk             (0x1ul << PWM_SSTRG_CNTSEN_Pos)

#define PWM_STATUS_CNTMAXFn_Pos          (0)

#define PWM_STATUS_CNTMAXFn_Msk          (0x3ful << PWM_STATUS_CNTMAXFn_Pos)

#define PWM_STATUS_CNTMAXF0_Pos          (0)

#define PWM_STATUS_CNTMAXF0_Msk          (0x1ul << PWM_STATUS_CNTMAXF0_Pos)

#define PWM_STATUS_CNTMAXF1_Pos          (1)

#define PWM_STATUS_CNTMAXF1_Msk          (0x1ul << PWM_STATUS_CNTMAXF1_Pos)

#define PWM_STATUS_CNTMAXF2_Pos          (2)

#define PWM_STATUS_CNTMAXF2_Msk          (0x1ul << PWM_STATUS_CNTMAXF2_Pos)

#define PWM_STATUS_CNTMAXF3_Pos          (3)

#define PWM_STATUS_CNTMAXF3_Msk          (0x1ul << PWM_STATUS_CNTMAXF3_Pos)

#define PWM_STATUS_CNTMAXF4_Pos          (4)

#define PWM_STATUS_CNTMAXF4_Msk          (0x1ul << PWM_STATUS_CNTMAXF4_Pos)

#define PWM_STATUS_CNTMAXF5_Pos          (5)

#define PWM_STATUS_CNTMAXF5_Msk          (0x1ul << PWM_STATUS_CNTMAXF5_Pos)

#define PWM_STATUS_SYNCINFn_Pos          (8)

#define PWM_STATUS_SYNCINFn_Msk          (0x7ul << PWM_STATUS_SYNCINFn_Pos)

#define PWM_STATUS_SYNCINF0_Pos          (8)

#define PWM_STATUS_SYNCINF0_Msk          (0x1ul << PWM_STATUS_SYNCINF0_Pos)

#define PWM_STATUS_SYNCINF2_Pos          (9)

#define PWM_STATUS_SYNCINF2_Msk          (0x1ul << PWM_STATUS_SYNCINF2_Pos)

#define PWM_STATUS_SYNCINF4_Pos          (10)

#define PWM_STATUS_SYNCINF4_Msk          (0x1ul << PWM_STATUS_SYNCINF4_Pos)

#define PWM_STATUS_ADCTRGFn_Pos          (16)

#define PWM_STATUS_ADCTRGFn_Msk          (0x3ful << PWM_STATUS_ADCTRGFn_Pos)

#define PWM_STATUS_ADCTRGF0_Pos          (16)

#define PWM_STATUS_ADCTRGF0_Msk          (0x1ul << PWM_STATUS_ADCTRGF0_Pos)

#define PWM_STATUS_ADCTRGF1_Pos          (17)

#define PWM_STATUS_ADCTRGF1_Msk          (0x1ul << PWM_STATUS_ADCTRGF1_Pos)

#define PWM_STATUS_ADCTRGF2_Pos          (18)

#define PWM_STATUS_ADCTRGF2_Msk          (0x1ul << PWM_STATUS_ADCTRGF2_Pos)

#define PWM_STATUS_ADCTRGF3_Pos          (19)

#define PWM_STATUS_ADCTRGF3_Msk          (0x1ul << PWM_STATUS_ADCTRGF3_Pos)

#define PWM_STATUS_ADCTRGF4_Pos          (20)

#define PWM_STATUS_ADCTRGF4_Msk          (0x1ul << PWM_STATUS_ADCTRGF4_Pos)

#define PWM_STATUS_ADCTRGF5_Pos          (21)

#define PWM_STATUS_ADCTRGF5_Msk          (0x1ul << PWM_STATUS_ADCTRGF5_Pos)

#define PWM_CAPINEN_CAPINENn_Pos         (0)

#define PWM_CAPINEN_CAPINENn_Msk         (0x3ful << PWM_CAPINEN_CAPINENn_Pos)

#define PWM_CAPINEN_CAPINEN0_Pos         (0)

#define PWM_CAPINEN_CAPINEN0_Msk         (0x1ul << PWM_CAPINEN_CAPINEN0_Pos)

#define PWM_CAPINEN_CAPINEN1_Pos         (1)

#define PWM_CAPINEN_CAPINEN1_Msk         (0x1ul << PWM_CAPINEN_CAPINEN1_Pos)

#define PWM_CAPINEN_CAPINEN2_Pos         (2)

#define PWM_CAPINEN_CAPINEN2_Msk         (0x1ul << PWM_CAPINEN_CAPINEN2_Pos)

#define PWM_CAPINEN_CAPINEN3_Pos         (3)

#define PWM_CAPINEN_CAPINEN3_Msk         (0x1ul << PWM_CAPINEN_CAPINEN3_Pos)

#define PWM_CAPINEN_CAPINEN4_Pos         (4)

#define PWM_CAPINEN_CAPINEN4_Msk         (0x1ul << PWM_CAPINEN_CAPINEN4_Pos)

#define PWM_CAPINEN_CAPINEN5_Pos         (5)

#define PWM_CAPINEN_CAPINEN5_Msk         (0x1ul << PWM_CAPINEN_CAPINEN5_Pos)

#define PWM_CAPCTL_CAPENn_Pos            (0)

#define PWM_CAPCTL_CAPENn_Msk            (0x3ful << PWM_CAPCTL_CAPENn_Pos)

#define PWM_CAPCTL_CAPEN0_Pos            (0)

#define PWM_CAPCTL_CAPEN0_Msk            (0x1ul << PWM_CAPCTL_CAPEN0_Pos)

#define PWM_CAPCTL_CAPEN1_Pos            (1)

#define PWM_CAPCTL_CAPEN1_Msk            (0x1ul << PWM_CAPCTL_CAPEN1_Pos)

#define PWM_CAPCTL_CAPEN2_Pos            (2)

#define PWM_CAPCTL_CAPEN2_Msk            (0x1ul << PWM_CAPCTL_CAPEN2_Pos)

#define PWM_CAPCTL_CAPEN3_Pos            (3)

#define PWM_CAPCTL_CAPEN3_Msk            (0x1ul << PWM_CAPCTL_CAPEN3_Pos)

#define PWM_CAPCTL_CAPEN4_Pos            (4)

#define PWM_CAPCTL_CAPEN4_Msk            (0x1ul << PWM_CAPCTL_CAPEN4_Pos)

#define PWM_CAPCTL_CAPEN5_Pos            (5)

#define PWM_CAPCTL_CAPEN5_Msk            (0x1ul << PWM_CAPCTL_CAPEN5_Pos)

#define PWM_CAPCTL_CAPINVn_Pos           (8)

#define PWM_CAPCTL_CAPINVn_Msk           (0x3ful << PWM_CAPCTL_CAPINVn_Pos)

#define PWM_CAPCTL_CAPINV0_Pos           (8)

#define PWM_CAPCTL_CAPINV0_Msk           (0x1ul << PWM_CAPCTL_CAPINV0_Pos)

#define PWM_CAPCTL_CAPINV1_Pos           (9)

#define PWM_CAPCTL_CAPINV1_Msk           (0x1ul << PWM_CAPCTL_CAPINV1_Pos)

#define PWM_CAPCTL_CAPINV2_Pos           (10)

#define PWM_CAPCTL_CAPINV2_Msk           (0x1ul << PWM_CAPCTL_CAPINV2_Pos)

#define PWM_CAPCTL_CAPINV3_Pos           (11)

#define PWM_CAPCTL_CAPINV3_Msk           (0x1ul << PWM_CAPCTL_CAPINV3_Pos)

#define PWM_CAPCTL_CAPINV4_Pos           (12)

#define PWM_CAPCTL_CAPINV4_Msk           (0x1ul << PWM_CAPCTL_CAPINV4_Pos)

#define PWM_CAPCTL_CAPINV5_Pos           (13)

#define PWM_CAPCTL_CAPINV5_Msk           (0x1ul << PWM_CAPCTL_CAPINV5_Pos)

#define PWM_CAPCTL_RCRLDENn_Pos          (16)

#define PWM_CAPCTL_RCRLDENn_Msk          (0x3ful << PWM_CAPCTL_RCRLDENn_Pos)

#define PWM_CAPCTL_RCRLDEN0_Pos          (16)

#define PWM_CAPCTL_RCRLDEN0_Msk          (0x1ul << PWM_CAPCTL_RCRLDEN0_Pos)

#define PWM_CAPCTL_RCRLDEN1_Pos          (17)

#define PWM_CAPCTL_RCRLDEN1_Msk          (0x1ul << PWM_CAPCTL_RCRLDEN1_Pos)

#define PWM_CAPCTL_RCRLDEN2_Pos          (18)

#define PWM_CAPCTL_RCRLDEN2_Msk          (0x1ul << PWM_CAPCTL_RCRLDEN2_Pos)

#define PWM_CAPCTL_RCRLDEN3_Pos          (19)

#define PWM_CAPCTL_RCRLDEN3_Msk          (0x1ul << PWM_CAPCTL_RCRLDEN3_Pos)

#define PWM_CAPCTL_RCRLDEN4_Pos          (20)

#define PWM_CAPCTL_RCRLDEN4_Msk          (0x1ul << PWM_CAPCTL_RCRLDEN4_Pos)

#define PWM_CAPCTL_RCRLDEN5_Pos          (21)

#define PWM_CAPCTL_RCRLDEN5_Msk          (0x1ul << PWM_CAPCTL_RCRLDEN5_Pos)

#define PWM_CAPCTL_FCRLDENn_Pos          (24)

#define PWM_CAPCTL_FCRLDENn_Msk          (0x3ful << PWM_CAPCTL_FCRLDENn_Pos)

#define PWM_CAPCTL_FCRLDEN0_Pos          (24)

#define PWM_CAPCTL_FCRLDEN0_Msk          (0x1ul << PWM_CAPCTL_FCRLDEN0_Pos)

#define PWM_CAPCTL_FCRLDEN1_Pos          (25)

#define PWM_CAPCTL_FCRLDEN1_Msk          (0x1ul << PWM_CAPCTL_FCRLDEN1_Pos)

#define PWM_CAPCTL_FCRLDEN2_Pos          (26)

#define PWM_CAPCTL_FCRLDEN2_Msk          (0x1ul << PWM_CAPCTL_FCRLDEN2_Pos)

#define PWM_CAPCTL_FCRLDEN3_Pos          (27)

#define PWM_CAPCTL_FCRLDEN3_Msk          (0x1ul << PWM_CAPCTL_FCRLDEN3_Pos)

#define PWM_CAPCTL_FCRLDEN4_Pos          (28)

#define PWM_CAPCTL_FCRLDEN4_Msk          (0x1ul << PWM_CAPCTL_FCRLDEN4_Pos)

#define PWM_CAPCTL_FCRLDEN5_Pos          (29)

#define PWM_CAPCTL_FCRLDEN5_Msk          (0x1ul << PWM_CAPCTL_FCRLDEN5_Pos)

#define PWM_CAPSTS_CRLIFOVn_Pos          (0)

#define PWM_CAPSTS_CRLIFOVn_Msk          (0x3ful << PWM_CAPSTS_CRLIFOVn_Pos)

#define PWM_CAPSTS_CRLIFOV0_Pos          (0)

#define PWM_CAPSTS_CRLIFOV0_Msk          (0x1ul << PWM_CAPSTS_CRLIFOV0_Pos)

#define PWM_CAPSTS_CRLIFOV1_Pos          (1)

#define PWM_CAPSTS_CRLIFOV1_Msk          (0x1ul << PWM_CAPSTS_CRLIFOV1_Pos)

#define PWM_CAPSTS_CRLIFOV2_Pos          (2)

#define PWM_CAPSTS_CRLIFOV2_Msk          (0x1ul << PWM_CAPSTS_CRLIFOV2_Pos)

#define PWM_CAPSTS_CRLIFOV3_Pos          (3)

#define PWM_CAPSTS_CRLIFOV3_Msk          (0x1ul << PWM_CAPSTS_CRLIFOV3_Pos)

#define PWM_CAPSTS_CRLIFOV4_Pos          (4)

#define PWM_CAPSTS_CRLIFOV4_Msk          (0x1ul << PWM_CAPSTS_CRLIFOV4_Pos)

#define PWM_CAPSTS_CRLIFOV5_Pos          (5)

#define PWM_CAPSTS_CRLIFOV5_Msk          (0x1ul << PWM_CAPSTS_CRLIFOV5_Pos)

#define PWM_CAPSTS_CFLIFOVn_Pos          (8)

#define PWM_CAPSTS_CFLIFOVn_Msk          (0x3ful << PWM_CAPSTS_CFLIFOVn_Pos)

#define PWM_CAPSTS_CFLIFOV0_Pos          (8)

#define PWM_CAPSTS_CFLIFOV0_Msk          (0x1ul << PWM_CAPSTS_CFLIFOV0_Pos)

#define PWM_CAPSTS_CFLIFOV1_Pos          (9)

#define PWM_CAPSTS_CFLIFOV1_Msk          (0x1ul << PWM_CAPSTS_CFLIFOV1_Pos)

#define PWM_CAPSTS_CFLIFOV2_Pos          (10)

#define PWM_CAPSTS_CFLIFOV2_Msk          (0x1ul << PWM_CAPSTS_CFLIFOV2_Pos)

#define PWM_CAPSTS_CFLIFOV3_Pos          (11)

#define PWM_CAPSTS_CFLIFOV3_Msk          (0x1ul << PWM_CAPSTS_CFLIFOV3_Pos)

#define PWM_CAPSTS_CFLIFOV4_Pos          (12)

#define PWM_CAPSTS_CFLIFOV4_Msk          (0x1ul << PWM_CAPSTS_CFLIFOV4_Pos)

#define PWM_CAPSTS_CFLIFOV5_Pos          (13)

#define PWM_CAPSTS_CFLIFOV5_Msk          (0x1ul << PWM_CAPSTS_CFLIFOV5_Pos)

#define PWM_RCAPDAT0_RCAPDAT_Pos         (0)

#define PWM_RCAPDAT0_RCAPDAT_Msk         (0xfffful << PWM_RCAPDAT0_RCAPDAT_Pos)

#define PWM_FCAPDAT0_FCAPDAT_Pos         (0)

#define PWM_FCAPDAT0_FCAPDAT_Msk         (0xfffful << PWM_FCAPDAT0_FCAPDAT_Pos)

#define PWM_RCAPDAT1_RCAPDAT_Pos         (0)

#define PWM_RCAPDAT1_RCAPDAT_Msk         (0xfffful << PWM_RCAPDAT1_RCAPDAT_Pos)

#define PWM_FCAPDAT1_FCAPDAT_Pos         (0)

#define PWM_FCAPDAT1_FCAPDAT_Msk         (0xfffful << PWM_FCAPDAT1_FCAPDAT_Pos)

#define PWM_RCAPDAT2_RCAPDAT_Pos         (0)

#define PWM_RCAPDAT2_RCAPDAT_Msk         (0xfffful << PWM_RCAPDAT2_RCAPDAT_Pos)

#define PWM_FCAPDAT2_FCAPDAT_Pos         (0)

#define PWM_FCAPDAT2_FCAPDAT_Msk         (0xfffful << PWM_FCAPDAT2_FCAPDAT_Pos)

#define PWM_RCAPDAT3_RCAPDAT_Pos         (0)

#define PWM_RCAPDAT3_RCAPDAT_Msk         (0xfffful << PWM_RCAPDAT3_RCAPDAT_Pos)

#define PWM_FCAPDAT3_FCAPDAT_Pos         (0)

#define PWM_FCAPDAT3_FCAPDAT_Msk         (0xfffful << PWM_FCAPDAT3_FCAPDAT_Pos)

#define PWM_RCAPDAT4_RCAPDAT_Pos         (0)

#define PWM_RCAPDAT4_RCAPDAT_Msk         (0xfffful << PWM_RCAPDAT4_RCAPDAT_Pos)

#define PWM_FCAPDAT4_FCAPDAT_Pos         (0)

#define PWM_FCAPDAT4_FCAPDAT_Msk         (0xfffful << PWM_FCAPDAT4_FCAPDAT_Pos)

#define PWM_RCAPDAT5_RCAPDAT_Pos         (0)

#define PWM_RCAPDAT5_RCAPDAT_Msk         (0xfffful << PWM_RCAPDAT5_RCAPDAT_Pos)

#define PWM_FCAPDAT5_FCAPDAT_Pos         (0)

#define PWM_FCAPDAT5_FCAPDAT_Msk         (0xfffful << PWM_FCAPDAT5_FCAPDAT_Pos)

#define PWM_PDMACTL_CHEN0_1_Pos          (0)

#define PWM_PDMACTL_CHEN0_1_Msk          (0x1ul << PWM_PDMACTL_CHEN0_1_Pos)

#define PWM_PDMACTL_CAPMOD0_1_Pos        (1)

#define PWM_PDMACTL_CAPMOD0_1_Msk        (0x3ul << PWM_PDMACTL_CAPMOD0_1_Pos)

#define PWM_PDMACTL_CAPORD0_1_Pos        (3)

#define PWM_PDMACTL_CAPORD0_1_Msk        (0x1ul << PWM_PDMACTL_CAPORD0_1_Pos)

#define PWM_PDMACTL_CHSEL0_1_Pos         (4)

#define PWM_PDMACTL_CHSEL0_1_Msk         (0x1ul << PWM_PDMACTL_CHSEL0_1_Pos)

#define PWM_PDMACTL_CHEN2_3_Pos          (8)

#define PWM_PDMACTL_CHEN2_3_Msk          (0x1ul << PWM_PDMACTL_CHEN2_3_Pos)

#define PWM_PDMACTL_CAPMOD2_3_Pos        (9)

#define PWM_PDMACTL_CAPMOD2_3_Msk        (0x3ul << PWM_PDMACTL_CAPMOD2_3_Pos)

#define PWM_PDMACTL_CAPORD2_3_Pos        (11)

#define PWM_PDMACTL_CAPORD2_3_Msk        (0x1ul << PWM_PDMACTL_CAPORD2_3_Pos)

#define PWM_PDMACTL_CHSEL2_3_Pos         (12)

#define PWM_PDMACTL_CHSEL2_3_Msk         (0x1ul << PWM_PDMACTL_CHSEL2_3_Pos)

#define PWM_PDMACTL_CHEN4_5_Pos          (16)

#define PWM_PDMACTL_CHEN4_5_Msk          (0x1ul << PWM_PDMACTL_CHEN4_5_Pos)

#define PWM_PDMACTL_CAPMOD4_5_Pos        (17)

#define PWM_PDMACTL_CAPMOD4_5_Msk        (0x3ul << PWM_PDMACTL_CAPMOD4_5_Pos)

#define PWM_PDMACTL_CAPORD4_5_Pos        (19)

#define PWM_PDMACTL_CAPORD4_5_Msk        (0x1ul << PWM_PDMACTL_CAPORD4_5_Pos)

#define PWM_PDMACTL_CHSEL4_5_Pos         (20)

#define PWM_PDMACTL_CHSEL4_5_Msk         (0x1ul << PWM_PDMACTL_CHSEL4_5_Pos)

#define PWM_PDMACAP0_1_CAPBUF_Pos        (0)

#define PWM_PDMACAP0_1_CAPBUF_Msk        (0xfffful << PWM_PDMACAP0_1_CAPBUF_Pos)

#define PWM_PDMACAP2_3_CAPBUF_Pos        (0)

#define PWM_PDMACAP2_3_CAPBUF_Msk        (0xfffful << PWM_PDMACAP2_3_CAPBUF_Pos)

#define PWM_PDMACAP4_5_CAPBUF_Pos        (0)

#define PWM_PDMACAP4_5_CAPBUF_Msk        (0xfffful << PWM_PDMACAP4_5_CAPBUF_Pos)

#define PWM_CAPIEN_CAPRIENn_Pos          (0)

#define PWM_CAPIEN_CAPRIENn_Msk          (0x3ful << PWM_CAPIEN_CAPRIENn_Pos)

#define PWM_CAPIEN_CAPRIEN0_Pos          (0)

#define PWM_CAPIEN_CAPRIEN0_Msk          (0x1ul << PWM_CAPIEN_CAPRIEN0_Pos)

#define PWM_CAPIEN_CAPRIEN1_Pos          (1)

#define PWM_CAPIEN_CAPRIEN1_Msk          (0x1ul << PWM_CAPIEN_CAPRIEN1_Pos)

#define PWM_CAPIEN_CAPRIEN2_Pos          (2)

#define PWM_CAPIEN_CAPRIEN2_Msk          (0x1ul << PWM_CAPIEN_CAPRIEN2_Pos)

#define PWM_CAPIEN_CAPRIEN3_Pos          (3)

#define PWM_CAPIEN_CAPRIEN3_Msk          (0x1ul << PWM_CAPIEN_CAPRIEN3_Pos)

#define PWM_CAPIEN_CAPRIEN4_Pos          (4)

#define PWM_CAPIEN_CAPRIEN4_Msk          (0x1ul << PWM_CAPIEN_CAPRIEN4_Pos)

#define PWM_CAPIEN_CAPRIEN5_Pos          (5)

#define PWM_CAPIEN_CAPRIEN5_Msk          (0x1ul << PWM_CAPIEN_CAPRIEN5_Pos)

#define PWM_CAPIEN_CAPFIENn_Pos          (8)

#define PWM_CAPIEN_CAPFIENn_Msk          (0x3ful << PWM_CAPIEN_CAPFIENn_Pos)

#define PWM_CAPIEN_CAPFIEN0_Pos          (8)

#define PWM_CAPIEN_CAPFIEN0_Msk          (0x1ul << PWM_CAPIEN_CAPFIEN0_Pos)

#define PWM_CAPIEN_CAPFIEN1_Pos          (9)

#define PWM_CAPIEN_CAPFIEN1_Msk          (0x1ul << PWM_CAPIEN_CAPFIEN1_Pos)

#define PWM_CAPIEN_CAPFIEN2_Pos          (10)

#define PWM_CAPIEN_CAPFIEN2_Msk          (0x1ul << PWM_CAPIEN_CAPFIEN2_Pos)

#define PWM_CAPIEN_CAPFIEN3_Pos          (11)

#define PWM_CAPIEN_CAPFIEN3_Msk          (0x1ul << PWM_CAPIEN_CAPFIEN3_Pos)

#define PWM_CAPIEN_CAPFIEN4_Pos          (12)

#define PWM_CAPIEN_CAPFIEN4_Msk          (0x1ul << PWM_CAPIEN_CAPFIEN4_Pos)

#define PWM_CAPIEN_CAPFIEN5_Pos          (13)

#define PWM_CAPIEN_CAPFIEN5_Msk          (0x1ul << PWM_CAPIEN_CAPFIEN5_Pos)

#define PWM_CAPIF_CRLIFn_Pos             (0)

#define PWM_CAPIF_CRLIFn_Msk             (0x3ful << PWM_CAPIF_CRLIFn_Pos)

#define PWM_CAPIF_CRLIF0_Pos             (0)

#define PWM_CAPIF_CRLIF0_Msk             (0x1ul << PWM_CAPIF_CRLIF0_Pos)

#define PWM_CAPIF_CRLIF1_Pos             (1)

#define PWM_CAPIF_CRLIF1_Msk             (0x1ul << PWM_CAPIF_CRLIF1_Pos)

#define PWM_CAPIF_CRLIF2_Pos             (2)

#define PWM_CAPIF_CRLIF2_Msk             (0x1ul << PWM_CAPIF_CRLIF2_Pos)

#define PWM_CAPIF_CRLIF3_Pos             (3)

#define PWM_CAPIF_CRLIF3_Msk             (0x1ul << PWM_CAPIF_CRLIF3_Pos)

#define PWM_CAPIF_CRLIF4_Pos             (4)

#define PWM_CAPIF_CRLIF4_Msk             (0x1ul << PWM_CAPIF_CRLIF4_Pos)

#define PWM_CAPIF_CRLIF5_Pos             (5)

#define PWM_CAPIF_CRLIF5_Msk             (0x1ul << PWM_CAPIF_CRLIF5_Pos)

#define PWM_CAPIF_CFLIFn_Pos             (8)

#define PWM_CAPIF_CFLIFn_Msk             (0x3ful << PWM_CAPIF_CFLIFn_Pos)

#define PWM_CAPIF_CFLIF0_Pos             (8)

#define PWM_CAPIF_CFLIF0_Msk             (0x1ul << PWM_CAPIF_CFLIF0_Pos)

#define PWM_CAPIF_CFLIF1_Pos             (9)

#define PWM_CAPIF_CFLIF1_Msk             (0x1ul << PWM_CAPIF_CFLIF1_Pos)

#define PWM_CAPIF_CFLIF2_Pos             (10)

#define PWM_CAPIF_CFLIF2_Msk             (0x1ul << PWM_CAPIF_CFLIF2_Pos)

#define PWM_CAPIF_CFLIF3_Pos             (11)

#define PWM_CAPIF_CFLIF3_Msk             (0x1ul << PWM_CAPIF_CFLIF3_Pos)

#define PWM_CAPIF_CFLIF4_Pos             (12)

#define PWM_CAPIF_CFLIF4_Msk             (0x1ul << PWM_CAPIF_CFLIF4_Pos)

#define PWM_CAPIF_CFLIF5_Pos             (13)

#define PWM_CAPIF_CFLIF5_Msk             (0x1ul << PWM_CAPIF_CFLIF5_Pos)

#define PWM_PBUF_PBUF_Pos                (0)

#define PWM_PBUF_PBUF_Msk                (0xfffful << PWM_PBUF_PBUF_Pos)

#define PWM_CMPBUF_CMPBUF_Pos            (0)

#define PWM_CMPBUF_CMPBUF_Msk            (0xfffful << PWM_CMPBUF_CMPBUF_Pos)

#define PWM_FTCBUF0_1_FTCMPBUF_Pos       (0)

#define PWM_FTCBUF0_1_FTCMPBUF_Msk       (0xfffful << PWM_FTCBUF0_1_FTCMPBUF_Pos)

#define PWM_FTCBUF2_3_FTCMPBUF_Pos       (0)

#define PWM_FTCBUF2_3_FTCMPBUF_Msk       (0xfffful << PWM_FTCBUF2_3_FTCMPBUF_Pos)

#define PWM_FTCBUF4_5_FTCMPBUF_Pos       (0)

#define PWM_FTCBUF4_5_FTCMPBUF_Msk       (0xfffful << PWM_FTCBUF4_5_FTCMPBUF_Pos)

#define PWM_FTCI_FTCMUn_Pos              (0)

#define PWM_FTCI_FTCMUn_Msk              (0x7ul << PWM_FTCI_FTCMUn_Pos)

#define PWM_FTCI_FTCMU0_Pos              (0)

#define PWM_FTCI_FTCMU0_Msk              (0x1ul << PWM_FTCI_FTCMU0_Pos)

#define PWM_FTCI_FTCMU2_Pos              (1)

#define PWM_FTCI_FTCMU2_Msk              (0x1ul << PWM_FTCI_FTCMU2_Pos)

#define PWM_FTCI_FTCMU4_Pos              (2)

#define PWM_FTCI_FTCMU4_Msk              (0x1ul << PWM_FTCI_FTCMU4_Pos)

#define PWM_FTCI_FTCMDn_Pos              (8)

#define PWM_FTCI_FTCMDn_Msk              (0x7ul << PWM_FTCI_FTCMDn_Pos)

#define PWM_FTCI_FTCMD0_Pos              (8)

#define PWM_FTCI_FTCMD0_Msk              (0x1ul << PWM_FTCI_FTCMD0_Pos)

#define PWM_FTCI_FTCMD2_Pos              (9)

#define PWM_FTCI_FTCMD2_Msk              (0x1ul << PWM_FTCI_FTCMD2_Pos)

#define PWM_FTCI_FTCMD4_Pos              (10)

#define PWM_FTCI_FTCMD4_Msk              (0x1ul << PWM_FTCI_FTCMD4_Pos)                     /* PWM_CONST */ /* end of PWM register group */


/*---------------------- Real Time Clock Controller -------------------------*/

typedef struct

{


    __IO uint32_t INIT;          /* Offset: 0x00  RTC Initiation Register                                            */

    __O  uint32_t RWEN;          /* Offset: 0x04  RTC Access Enable Register                                         */

    __IO uint32_t FREQADJ;       /* Offset: 0x08  RTC Frequency Compensation Register                                */

    __IO uint32_t TIME;          /* Offset: 0x0C  Time Loading Register                                              */

    __IO uint32_t CAL;           /* Offset: 0x10  RTC Calendar Loading Register                                      */

    __IO uint32_t CLKFMT;        /* Offset: 0x14  Time Scale Selection Register                                      */

    __IO uint32_t WEEKDAY;       /* Offset: 0x18  Day of the Week Register                                           */

    __IO uint32_t TALM;          /* Offset: 0x1C  Time Alarm Register                                                */

    __IO uint32_t CALM;          /* Offset: 0x20  Calendar Alarm Register                                            */

    __I  uint32_t LEAPYEAR;      /* Offset: 0x24  RTC Leap Year Indicator Register                                   */

    __IO uint32_t INTEN;         /* Offset: 0x28  RTC Interrupt Enable Register                                      */

    __IO uint32_t INTSTS;        /* Offset: 0x2C  RTC Interrupt Indicator Register                                   */

    __IO uint32_t TICK;          /* Offset: 0x30  RTC Time Tick Register                                             */

    __IO uint32_t TAMSK;         /* Offset: 0x34  Time Alarm Mask Register                                           */

    __IO uint32_t CAMSK;         /* Offset: 0x38  Calendar Alarm Mask Register                                       */

    __IO uint32_t SPRCTL;        /* Offset: 0x3C  RTC Spare Functional Control Register                              */

    __IO uint32_t SPR[20];       /* Offset: 0x40 ~ 0x8C  RTC Spare Register 0 ~ 19                                   */

    __I  uint32_t RESERVE0[28];

    __IO uint32_t LXTCTL;        /* Offset: 0x100  RTC 32.768 kHz Oscillator Control Register                        */

    __IO uint32_t LXTOCTL;       /* Offset: 0x104  X32KO Pin Control Register                                        */

    __IO uint32_t LXTICTL;       /* Offset: 0x108  X32KI Pin Control Register                                        */

    __IO uint32_t TAMPCTL;       /* Offset: 0x10C  TAMPER Pin Control Register                                       */


} RTC_T;


#define RTC_INIT_ACTIVE_Pos              (0)

#define RTC_INIT_ACTIVE_Msk              (0x1ul << RTC_INIT_ACTIVE_Pos)

#define RTC_INIT_INIT_Pos                (0)

#define RTC_INIT_INIT_Msk                (0xfffffffful << RTC_INIT_INIT_Pos)

#define RTC_RWEN_RWEN_Pos                (0)

#define RTC_RWEN_RWEN_Msk                (0xfffful << RTC_RWEN_RWEN_Pos)

#define RTC_RWEN_RWENF_Pos               (16)

#define RTC_RWEN_RWENF_Msk               (0x1ul << RTC_RWEN_RWENF_Pos)

#define RTC_FREQADJ_FRACTION_Pos         (0)

#define RTC_FREQADJ_FRACTION_Msk         (0x3ful << RTC_FREQADJ_FRACTION_Pos)

#define RTC_FREQADJ_INTEGER_Pos          (8)

#define RTC_FREQADJ_INTEGER_Msk          (0xful << RTC_FREQADJ_INTEGER_Pos)

#define RTC_TIME_SEC_Pos                 (0)

#define RTC_TIME_SEC_Msk                 (0xful << RTC_TIME_SEC_Pos)

#define RTC_TIME_TENSEC_Pos              (4)

#define RTC_TIME_TENSEC_Msk              (0x7ul << RTC_TIME_TENSEC_Pos)

#define RTC_TIME_MIN_Pos                 (8)

#define RTC_TIME_MIN_Msk                 (0xful << RTC_TIME_MIN_Pos)

#define RTC_TIME_TENMIN_Pos              (12)

#define RTC_TIME_TENMIN_Msk              (0x7ul << RTC_TIME_TENMIN_Pos)

#define RTC_TIME_HR_Pos                  (16)

#define RTC_TIME_HR_Msk                  (0xful << RTC_TIME_HR_Pos)

#define RTC_TIME_TENHR_Pos               (20)

#define RTC_TIME_TENHR_Msk               (0x3ul << RTC_TIME_TENHR_Pos)

#define RTC_CAL_DAY_Pos                  (0)

#define RTC_CAL_DAY_Msk                  (0xful << RTC_CAL_DAY_Pos)

#define RTC_CAL_TENDAY_Pos               (4)

#define RTC_CAL_TENDAY_Msk               (0x3ul << RTC_CAL_TENDAY_Pos)

#define RTC_CAL_MON_Pos                  (8)

#define RTC_CAL_MON_Msk                  (0xful << RTC_CAL_MON_Pos)

#define RTC_CAL_TENMON_Pos               (12)

#define RTC_CAL_TENMON_Msk               (0x1ul << RTC_CAL_TENMON_Pos)

#define RTC_CAL_YEAR_Pos                 (16)

#define RTC_CAL_YEAR_Msk                 (0xful << RTC_CAL_YEAR_Pos)

#define RTC_CAL_TENYEAR_Pos              (20)

#define RTC_CAL_TENYEAR_Msk              (0xful << RTC_CAL_TENYEAR_Pos)

#define RTC_CLKFMT_24HEN_Pos             (0)

#define RTC_CLKFMT_24HEN_Msk             (0x1ul << RTC_CLKFMT_24HEN_Pos)

#define RTC_WEEKDAY_WEEKDAY_Pos          (0)

#define RTC_WEEKDAY_WEEKDAY_Msk          (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos)

#define RTC_TALM_SEC_Pos                 (0)

#define RTC_TALM_SEC_Msk                 (0xful << RTC_TALM_SEC_Pos)

#define RTC_TALM_TENSEC_Pos              (4)

#define RTC_TALM_TENSEC_Msk              (0x7ul << RTC_TALM_TENSEC_Pos)

#define RTC_TALM_MIN_Pos                 (8)

#define RTC_TALM_MIN_Msk                 (0xful << RTC_TALM_MIN_Pos)

#define RTC_TALM_TENMIN_Pos              (12)

#define RTC_TALM_TENMIN_Msk              (0x7ul << RTC_TALM_TENMIN_Pos)

#define RTC_TALM_HR_Pos                  (16)

#define RTC_TALM_HR_Msk                  (0xful << RTC_TALM_HR_Pos)

#define RTC_TALM_TENHR_Pos               (20)

#define RTC_TALM_TENHR_Msk               (0x3ul << RTC_TALM_TENHR_Pos)

#define RTC_CALM_DAY_Pos                 (0)

#define RTC_CALM_DAY_Msk                 (0xful << RTC_CALM_DAY_Pos)

#define RTC_CALM_TENDAY_Pos              (4)

#define RTC_CALM_TENDAY_Msk              (0x3ul << RTC_CALM_TENDAY_Pos)

#define RTC_CALM_MON_Pos                 (8)

#define RTC_CALM_MON_Msk                 (0xful << RTC_CALM_MON_Pos)

#define RTC_CALM_TENMON_Pos              (12)

#define RTC_CALM_TENMON_Msk              (0x1ul << RTC_CALM_TENMON_Pos)

#define RTC_CALM_YEAR_Pos                (16)

#define RTC_CALM_YEAR_Msk                (0xful << RTC_CALM_YEAR_Pos)

#define RTC_CALM_TENYEAR_Pos             (20)

#define RTC_CALM_TENYEAR_Msk             (0xful << RTC_CALM_TENYEAR_Pos)

#define RTC_LEAPYEAR_LEAPYEAR_Pos        (0)

#define RTC_LEAPYEAR_LEAPYEAR_Msk        (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos)

#define RTC_INTEN_ALMIEN_Pos             (0)

#define RTC_INTEN_ALMIEN_Msk             (0x1ul << RTC_INTEN_ALMIEN_Pos)

#define RTC_INTEN_TICKIEN_Pos            (1)

#define RTC_INTEN_TICKIEN_Msk            (0x1ul << RTC_INTEN_TICKIEN_Pos)

#define RTC_INTEN_SNPDIEN_Pos            (2)

#define RTC_INTEN_SNPDIEN_Msk            (0x1ul << RTC_INTEN_SNPDIEN_Pos)

#define RTC_INTSTS_ALMIF_Pos             (0)

#define RTC_INTSTS_ALMIF_Msk             (0x1ul << RTC_INTSTS_ALMIF_Pos)

#define RTC_INTSTS_TICKIF_Pos            (1)

#define RTC_INTSTS_TICKIF_Msk            (0x1ul << RTC_INTSTS_TICKIF_Pos)

#define RTC_INTSTS_SNPDIF_Pos            (2)

#define RTC_INTSTS_SNPDIF_Msk            (0x1ul << RTC_INTSTS_SNPDIF_Pos)

#define RTC_TICK_TICK_Pos                (0)

#define RTC_TICK_TICK_Msk                (0x7ul << RTC_TICK_TICK_Pos)

#define RTC_TAMSK_MSEC_Pos               (0)

#define RTC_TAMSK_MSEC_Msk               (0x1ul << RTC_TAMSK_MSEC_Pos)

#define RTC_TAMSK_MTENSEC_Pos            (1)

#define RTC_TAMSK_MTENSEC_Msk            (0x1ul << RTC_TAMSK_MTENSEC_Pos)

#define RTC_TAMSK_MMIN_Pos               (2)

#define RTC_TAMSK_MMIN_Msk               (0x1ul << RTC_TAMSK_MMIN_Pos)

#define RTC_TAMSK_MTENMIN_Pos            (3)

#define RTC_TAMSK_MTENMIN_Msk            (0x1ul << RTC_TAMSK_MTENMIN_Pos)

#define RTC_TAMSK_MHR_Pos                (4)

#define RTC_TAMSK_MHR_Msk                (0x1ul << RTC_TAMSK_MHR_Pos)

#define RTC_TAMSK_MTENHR_Pos             (5)

#define RTC_TAMSK_MTENHR_Msk             (0x1ul << RTC_TAMSK_MTENHR_Pos)

#define RTC_CAMSK_MDAY_Pos               (0)

#define RTC_CAMSK_MDAY_Msk               (0x1ul << RTC_CAMSK_MDAY_Pos)

#define RTC_CAMSK_MTENDAY_Pos            (1)

#define RTC_CAMSK_MTENDAY_Msk            (0x1ul << RTC_CAMSK_MTENDAY_Pos)

#define RTC_CAMSK_MMON_Pos               (2)

#define RTC_CAMSK_MMON_Msk               (0x1ul << RTC_CAMSK_MMON_Pos)

#define RTC_CAMSK_MTENMON_Pos            (3)

#define RTC_CAMSK_MTENMON_Msk            (0x1ul << RTC_CAMSK_MTENMON_Pos)

#define RTC_CAMSK_MYEAR_Pos              (4)

#define RTC_CAMSK_MYEAR_Msk              (0x1ul << RTC_CAMSK_MYEAR_Pos)

#define RTC_CAMSK_MTENYEAR_Pos           (5)

#define RTC_CAMSK_MTENYEAR_Msk           (0x1ul << RTC_CAMSK_MTENYEAR_Pos)

#define RTC_SPRCTL_SNPDEN_Pos            (0)

#define RTC_SPRCTL_SNPDEN_Msk            (0x1ul << RTC_SPRCTL_SNPDEN_Pos)

#define RTC_SPRCTL_SNPTYPE0_Pos          (1)

#define RTC_SPRCTL_SNPTYPE0_Msk          (0x1ul << RTC_SPRCTL_SNPTYPE0_Pos)

#define RTC_SPRCTL_SPRRWEN_Pos           (2)

#define RTC_SPRCTL_SPRRWEN_Msk           (0x1ul << RTC_SPRCTL_SPRRWEN_Pos)

#define RTC_SPRCTL_SNPTYPE1_Pos          (3)

#define RTC_SPRCTL_SNPTYPE1_Msk          (0x1ul << RTC_SPRCTL_SNPTYPE1_Pos)

#define RTC_SPRCTL_SPRCSTS_Pos           (5)

#define RTC_SPRCTL_SPRCSTS_Msk           (0x1ul << RTC_SPRCTL_SPRCSTS_Pos)

#define RTC_SPRCTL_SPRRWRDY_Pos          (7)

#define RTC_SPRCTL_SPRRWRDY_Msk          (0x1ul << RTC_SPRCTL_SPRRWRDY_Pos)

#define RTC_SPR_SPARE_Pos                (0)

#define RTC_SPR_SPARE_Msk                (0xfffffffful << RTC_SPR_SPARE_Pos)

#define RTC_LXTCTL_LXTEN_Pos             (0)

#define RTC_LXTCTL_LXTEN_Msk             (0x1ul << RTC_LXTCTL_LXTEN_Pos)

#define RTC_LXTCTL_GAIN_Pos              (1)

#define RTC_LXTCTL_GAIN_Msk              (0x7ul << RTC_LXTCTL_GAIN_Pos)

#define RTC_LXTOCTL_OPMODE_Pos           (0)

#define RTC_LXTOCTL_OPMODE_Msk           (0x3ul << RTC_LXTOCTL_OPMODE_Pos)

#define RTC_LXTOCTL_DOUT_Pos             (2)

#define RTC_LXTOCTL_DOUT_Msk             (0x1ul << RTC_LXTOCTL_DOUT_Pos)

#define RTC_LXTOCTL_CTLSEL_Pos           (3)

#define RTC_LXTOCTL_CTLSEL_Msk           (0x1ul << RTC_LXTOCTL_CTLSEL_Pos)

#define RTC_LXTICTL_OPMODE_Pos           (0)

#define RTC_LXTICTL_OPMODE_Msk           (0x3ul << RTC_LXTICTL_OPMODE_Pos)

#define RTC_LXTICTL_DOUT_Pos             (2)

#define RTC_LXTICTL_DOUT_Msk             (0x1ul << RTC_LXTICTL_DOUT_Pos)

#define RTC_LXTICTL_CTLSEL_Pos           (3)

#define RTC_LXTICTL_CTLSEL_Msk           (0x1ul << RTC_LXTICTL_CTLSEL_Pos)

#define RTC_TAMPCTL_OPMODE_Pos           (0)

#define RTC_TAMPCTL_OPMODE_Msk           (0x3ul << RTC_TAMPCTL_OPMODE_Pos)

#define RTC_TAMPCTL_DOUT_Pos             (2)

#define RTC_TAMPCTL_DOUT_Msk             (0x1ul << RTC_TAMPCTL_DOUT_Pos)

#define RTC_TAMPCTL_CTLSEL_Pos           (3)

#define RTC_TAMPCTL_CTLSEL_Msk           (0x1ul << RTC_TAMPCTL_CTLSEL_Pos)                  /* RTC_CONST */ /* end of RTC register group */


/*---------------------- Smart Card Host Interface Controller -------------------------*/

typedef struct

{


    __IO uint32_t DAT;           /* Offset: 0x00  SC Receiving/Transmit Holding Buffer Register.                     */

    __IO uint32_t CTL;           /* Offset: 0x04  SC Control Register.                                               */

    __IO uint32_t ALTCTL;        /* Offset: 0x08  SC Alternate Control Register.                                     */

    __IO uint32_t EGT;           /* Offset: 0x0C  SC Extend Guard Time Register.                                     */

    __IO uint32_t RXTOUT;        /* Offset: 0x10  SC Receive buffer Time-out Register.                               */

    __IO uint32_t ETUCTL;        /* Offset: 0x14  SC ETU Control Register.                                           */

    __IO uint32_t INTEN;         /* Offset: 0x18  SC Interrupt Enable Control Register.                              */

    __IO uint32_t INTSTS;        /* Offset: 0x1C  SC Interrupt Status Register.                                      */

    __IO uint32_t STATUS;        /* Offset: 0x20  SC Status Register.                                                */

    __IO uint32_t PINCTL;        /* Offset: 0x24  SC Pin Control State Register.                                     */

    __IO uint32_t TMRCTL0;       /* Offset: 0x28  SC Internal Timer Control Register 0.                              */

    __IO uint32_t TMRCTL1;       /* Offset: 0x2C  SC Internal Timer Control Register 1.                              */

    __IO uint32_t TMRCTL2;       /* Offset: 0x30  SC Internal Timer Control Register 2.                              */

    __IO uint32_t UARTCTL;       /* Offset: 0x34  SC UART Mode Control Register.                                     */

    __I  uint32_t TMRDAT0;       /* Offset: 0x38  SC Timer Current Data Register A.                                  */

    __I  uint32_t TMRDAT1_2;     /* Offset: 0x3C  SC Timer Current Data Register B.                                  */


} SC_T;


#define SC_DAT_DAT_Pos                   (0)

#define SC_DAT_DAT_Msk                   (0xfful << SC_DAT_DAT_Pos)

#define SC_CTL_SCEN_Pos                  (0)

#define SC_CTL_SCEN_Msk                  (0x1ul << SC_CTL_SCEN_Pos)

#define SC_CTL_RXOFF_Pos                 (1)

#define SC_CTL_RXOFF_Msk                 (0x1ul << SC_CTL_RXOFF_Pos)

#define SC_CTL_TXOFF_Pos                 (2)

#define SC_CTL_TXOFF_Msk                 (0x1ul << SC_CTL_TXOFF_Pos)

#define SC_CTL_AUTOCEN_Pos               (3)

#define SC_CTL_AUTOCEN_Msk               (0x1ul << SC_CTL_AUTOCEN_Pos)

#define SC_CTL_CONSEL_Pos                (4)

#define SC_CTL_CONSEL_Msk                (0x3ul << SC_CTL_CONSEL_Pos)

#define SC_CTL_RXTRGLV_Pos               (6)

#define SC_CTL_RXTRGLV_Msk               (0x3ul << SC_CTL_RXTRGLV_Pos)

#define SC_CTL_BGT_Pos                   (8)

#define SC_CTL_BGT_Msk                   (0x1ful << SC_CTL_BGT_Pos)

#define SC_CTL_TMRSEL_Pos                (13)

#define SC_CTL_TMRSEL_Msk                (0x3ul << SC_CTL_TMRSEL_Pos)

#define SC_CTL_NSB_Pos                   (15)

#define SC_CTL_NSB_Msk                   (0x1ul << SC_CTL_NSB_Pos)

#define SC_CTL_RXRTY_Pos                 (16)

#define SC_CTL_RXRTY_Msk                 (0x7ul << SC_CTL_RXRTY_Pos)

#define SC_CTL_RXRTYEN_Pos               (19)

#define SC_CTL_RXRTYEN_Msk               (0x1ul << SC_CTL_RXRTYEN_Pos)

#define SC_CTL_TXRTY_Pos                 (20)

#define SC_CTL_TXRTY_Msk                 (0x7ul << SC_CTL_TXRTY_Pos)

#define SC_CTL_TXRTYEN_Pos               (23)

#define SC_CTL_TXRTYEN_Msk               (0x1ul << SC_CTL_TXRTYEN_Pos)

#define SC_CTL_CDDBSEL_Pos               (24)

#define SC_CTL_CDDBSEL_Msk               (0x3ul << SC_CTL_CDDBSEL_Pos)

#define SC_CTL_CDLV_Pos                  (26)

#define SC_CTL_CDLV_Msk                  (0x1ul << SC_CTL_CDLV_Pos)

#define SC_CTL_SYNC_Pos                  (30)

#define SC_CTL_SYNC_Msk                  (0x1ul << SC_CTL_SYNC_Pos)

#define SC_CTL_ICEDEBUG_Pos              (31)

#define SC_CTL_ICEDEBUG_Msk              (0x1ul << SC_CTL_ICEDEBUG_Pos)

#define SC_ALTCTL_TXRST_Pos              (0)

#define SC_ALTCTL_TXRST_Msk              (0x1ul << SC_ALTCTL_TXRST_Pos)

#define SC_ALTCTL_RXRST_Pos              (1)

#define SC_ALTCTL_RXRST_Msk              (0x1ul << SC_ALTCTL_RXRST_Pos)

#define SC_ALTCTL_DACTEN_Pos             (2)

#define SC_ALTCTL_DACTEN_Msk             (0x1ul << SC_ALTCTL_DACTEN_Pos)

#define SC_ALTCTL_ACTEN_Pos              (3)

#define SC_ALTCTL_ACTEN_Msk              (0x1ul << SC_ALTCTL_ACTEN_Pos)

#define SC_ALTCTL_WARSTEN_Pos            (4)

#define SC_ALTCTL_WARSTEN_Msk            (0x1ul << SC_ALTCTL_WARSTEN_Pos)

#define SC_ALTCTL_CNTEN0_Pos             (5)

#define SC_ALTCTL_CNTEN0_Msk             (0x1ul << SC_ALTCTL_CNTEN0_Pos)

#define SC_ALTCTL_CNTEN1_Pos             (6)

#define SC_ALTCTL_CNTEN1_Msk             (0x1ul << SC_ALTCTL_CNTEN1_Pos)

#define SC_ALTCTL_CNTEN2_Pos             (7)

#define SC_ALTCTL_CNTEN2_Msk             (0x1ul << SC_ALTCTL_CNTEN2_Pos)

#define SC_ALTCTL_INITSEL_Pos            (8)

#define SC_ALTCTL_INITSEL_Msk            (0x3ul << SC_ALTCTL_INITSEL_Pos)

#define SC_ALTCTL_ADACEN_Pos             (11)

#define SC_ALTCTL_ADACEN_Msk             (0x1ul << SC_ALTCTL_ADACEN_Pos)

#define SC_ALTCTL_RXBGTEN_Pos            (12)

#define SC_ALTCTL_RXBGTEN_Msk            (0x1ul << SC_ALTCTL_RXBGTEN_Pos)

#define SC_ALTCTL_ACTSTS0_Pos            (13)

#define SC_ALTCTL_ACTSTS0_Msk            (0x1ul << SC_ALTCTL_ACTSTS0_Pos)

#define SC_ALTCTL_ACTSTS1_Pos            (14)

#define SC_ALTCTL_ACTSTS1_Msk            (0x1ul << SC_ALTCTL_ACTSTS1_Pos)

#define SC_ALTCTL_ACTSTS2_Pos            (15)

#define SC_ALTCTL_ACTSTS2_Msk            (0x1ul << SC_ALTCTL_ACTSTS2_Pos)

#define SC_ALTCTL_OUTSEL_Pos             (16)

#define SC_ALTCTL_OUTSEL_Msk             (0x1ul << SC_ALTCTL_OUTSEL_Pos)

#define SC_EGT_EGT_Pos                   (0)

#define SC_EGT_EGT_Msk                   (0xfful << SC_EGT_EGT_Pos)

#define SC_RXTOUT_RFTM_Pos               (0)

#define SC_RXTOUT_RFTM_Msk               (0x1fful << SC_RXTOUT_RFTM_Pos)

#define SC_ETUCTL_ETURDIV_Pos            (0)

#define SC_ETUCTL_ETURDIV_Msk            (0xffful << SC_ETUCTL_ETURDIV_Pos)

#define SC_ETUCTL_CMPEN_Pos              (15)

#define SC_ETUCTL_CMPEN_Msk              (0x1ul << SC_ETUCTL_CMPEN_Pos)

#define SC_INTEN_RDAIEN_Pos              (0)

#define SC_INTEN_RDAIEN_Msk              (0x1ul << SC_INTEN_RDAIEN_Pos)

#define SC_INTEN_TBEIEN_Pos              (1)

#define SC_INTEN_TBEIEN_Msk              (0x1ul << SC_INTEN_TBEIEN_Pos)

#define SC_INTEN_TERRIEN_Pos             (2)

#define SC_INTEN_TERRIEN_Msk             (0x1ul << SC_INTEN_TERRIEN_Pos)

#define SC_INTEN_TMR0IEN_Pos             (3)

#define SC_INTEN_TMR0IEN_Msk             (0x1ul << SC_INTEN_TMR0IEN_Pos)

#define SC_INTEN_TMR1IEN_Pos             (4)

#define SC_INTEN_TMR1IEN_Msk             (0x1ul << SC_INTEN_TMR1IEN_Pos)

#define SC_INTEN_TMR2IEN_Pos             (5)

#define SC_INTEN_TMR2IEN_Msk             (0x1ul << SC_INTEN_TMR2IEN_Pos)

#define SC_INTEN_BGTIEN_Pos              (6)

#define SC_INTEN_BGTIEN_Msk              (0x1ul << SC_INTEN_BGTIEN_Pos)

#define SC_INTEN_CDIEN_Pos               (7)

#define SC_INTEN_CDIEN_Msk               (0x1ul << SC_INTEN_CDIEN_Pos)

#define SC_INTEN_INITIEN_Pos             (8)

#define SC_INTEN_INITIEN_Msk             (0x1ul << SC_INTEN_INITIEN_Pos)

#define SC_INTEN_RXTOIF_Pos              (9)

#define SC_INTEN_RXTOIF_Msk              (0x1ul << SC_INTEN_RXTOIF_Pos)

#define SC_INTEN_ACERRIEN_Pos            (10)

#define SC_INTEN_ACERRIEN_Msk            (0x1ul << SC_INTEN_ACERRIEN_Pos)

#define SC_INTSTS_RDAIF_Pos              (0)

#define SC_INTSTS_RDAIF_Msk              (0x1ul << SC_INTSTS_RDAIF_Pos)

#define SC_INTSTS_TBEIF_Pos              (1)

#define SC_INTSTS_TBEIF_Msk              (0x1ul << SC_INTSTS_TBEIF_Pos)

#define SC_INTSTS_TERRIF_Pos             (2)

#define SC_INTSTS_TERRIF_Msk             (0x1ul << SC_INTSTS_TERRIF_Pos)

#define SC_INTSTS_TMR0IF_Pos             (3)

#define SC_INTSTS_TMR0IF_Msk             (0x1ul << SC_INTSTS_TMR0IF_Pos)

#define SC_INTSTS_TMR1IF_Pos             (4)

#define SC_INTSTS_TMR1IF_Msk             (0x1ul << SC_INTSTS_TMR1IF_Pos)

#define SC_INTSTS_TMR2IF_Pos             (5)

#define SC_INTSTS_TMR2IF_Msk             (0x1ul << SC_INTSTS_TMR2IF_Pos)

#define SC_INTSTS_BGTIF_Pos              (6)

#define SC_INTSTS_BGTIF_Msk              (0x1ul << SC_INTSTS_BGTIF_Pos)

#define SC_INTSTS_CDIF_Pos               (7)

#define SC_INTSTS_CDIF_Msk               (0x1ul << SC_INTSTS_CDIF_Pos)

#define SC_INTSTS_INITIF_Pos             (8)

#define SC_INTSTS_INITIF_Msk             (0x1ul << SC_INTSTS_INITIF_Pos)

#define SC_INTSTS_RBTOIF_Pos             (9)

#define SC_INTSTS_RBTOIF_Msk             (0x1ul << SC_INTSTS_RBTOIF_Pos)

#define SC_INTSTS_ACERRIF_Pos            (10)

#define SC_INTSTS_ACERRIF_Msk            (0x1ul << SC_INTSTS_ACERRIF_Pos)

#define SC_STATUS_RXOV_Pos               (0)

#define SC_STATUS_RXOV_Msk               (0x1ul << SC_STATUS_RXOV_Pos)

#define SC_STATUS_RXEMPTY_Pos            (1)

#define SC_STATUS_RXEMPTY_Msk            (0x1ul << SC_STATUS_RXEMPTY_Pos)

#define SC_STATUS_RXFULL_Pos             (2)

#define SC_STATUS_RXFULL_Msk             (0x1ul << SC_STATUS_RXFULL_Pos)

#define SC_STATUS_PEF_Pos                (4)

#define SC_STATUS_PEF_Msk                (0x1ul << SC_STATUS_PEF_Pos)

#define SC_STATUS_FEF_Pos                (5)

#define SC_STATUS_FEF_Msk                (0x1ul << SC_STATUS_FEF_Pos)

#define SC_STATUS_BEF_Pos                (6)

#define SC_STATUS_BEF_Msk                (0x1ul << SC_STATUS_BEF_Pos)

#define SC_STATUS_TXOV_Pos               (8)

#define SC_STATUS_TXOV_Msk               (0x1ul << SC_STATUS_TXOV_Pos)

#define SC_STATUS_TXEMPTY_Pos            (9)

#define SC_STATUS_TXEMPTY_Msk            (0x1ul << SC_STATUS_TXEMPTY_Pos)

#define SC_STATUS_TXFULL_Pos             (10)

#define SC_STATUS_TXFULL_Msk             (0x1ul << SC_STATUS_TXFULL_Pos)

#define SC_STATUS_CREMOVE_Pos            (11)

#define SC_STATUS_CREMOVE_Msk            (0x1ul << SC_STATUS_CREMOVE_Pos)

#define SC_STATUS_CINSERT_Pos            (12)

#define SC_STATUS_CINSERT_Msk            (0x1ul << SC_STATUS_CINSERT_Pos)

#define SC_STATUS_CDPINSTS_Pos           (13)

#define SC_STATUS_CDPINSTS_Msk           (0x1ul << SC_STATUS_CDPINSTS_Pos)

#define SC_STATUS_RXPOINT_Pos            (16)

#define SC_STATUS_RXPOINT_Msk            (0x3ul << SC_STATUS_RXPOINT_Pos)

#define SC_STATUS_RXRERR_Pos             (21)

#define SC_STATUS_RXRERR_Msk             (0x1ul << SC_STATUS_RXRERR_Pos)

#define SC_STATUS_RXOVERR_Pos            (22)

#define SC_STATUS_RXOVERR_Msk            (0x1ul << SC_STATUS_RXOVERR_Pos)

#define SC_STATUS_RXACT_Pos              (23)

#define SC_STATUS_RXACT_Msk              (0x1ul << SC_STATUS_RXACT_Pos)

#define SC_STATUS_TXPOINT_Pos            (24)

#define SC_STATUS_TXPOINT_Msk            (0x3ul << SC_STATUS_TXPOINT_Pos)

#define SC_STATUS_TXRERR_Pos             (29)

#define SC_STATUS_TXRERR_Msk             (0x1ul << SC_STATUS_TXRERR_Pos)

#define SC_STATUS_TXOVERR_Pos            (30)

#define SC_STATUS_TXOVERR_Msk            (0x1ul << SC_STATUS_TXOVERR_Pos)

#define SC_STATUS_TXACT_Pos              (31)

#define SC_STATUS_TXACT_Msk              (0x1ul << SC_STATUS_TXACT_Pos)

#define SC_PINCTL_PWREN_Pos              (0)

#define SC_PINCTL_PWREN_Msk              (0x1ul << SC_PINCTL_PWREN_Pos)

#define SC_PINCTL_SCRST_Pos              (1)

#define SC_PINCTL_SCRST_Msk              (0x1ul << SC_PINCTL_SCRST_Pos)

#define SC_PINCTL_CSTOPLV_Pos            (5)

#define SC_PINCTL_CSTOPLV_Msk            (0x1ul << SC_PINCTL_CSTOPLV_Pos)

#define SC_PINCTL_CLKKEEP_Pos            (6)

#define SC_PINCTL_CLKKEEP_Msk            (0x1ul << SC_PINCTL_CLKKEEP_Pos)

#define SC_PINCTL_SCDOUT_Pos             (9)

#define SC_PINCTL_SCDOUT_Msk             (0x1ul << SC_PINCTL_SCDOUT_Pos)

#define SC_PINCTL_PWRINV_Pos             (11)

#define SC_PINCTL_PWRINV_Msk             (0x1ul << SC_PINCTL_PWRINV_Pos)

#define SC_PINCTL_SCDOSTS_Pos            (12)

#define SC_PINCTL_SCDOSTS_Msk            (0x1ul << SC_PINCTL_SCDOSTS_Pos)

#define SC_PINCTL_DATSTS_Pos             (16)

#define SC_PINCTL_DATSTS_Msk             (0x1ul << SC_PINCTL_DATSTS_Pos)

#define SC_PINCTL_PWRSTS_Pos             (17)

#define SC_PINCTL_PWRSTS_Msk             (0x1ul << SC_PINCTL_PWRSTS_Pos)

#define SC_PINCTL_RSTSTS_Pos             (18)

#define SC_PINCTL_RSTSTS_Msk             (0x1ul << SC_PINCTL_RSTSTS_Pos)

#define SC_PINCTL_SYNC_Pos               (30)

#define SC_PINCTL_SYNC_Msk               (0x1ul << SC_PINCTL_SYNC_Pos)

#define SC_PINCTL_LOOPBK_Pos             (31)

#define SC_PINCTL_LOOPBK_Msk             (0x1ul << SC_PINCTL_LOOPBK_Pos)

#define SC_TMRCTL0_CNT_Pos               (0)

#define SC_TMRCTL0_CNT_Msk               (0xfffffful << SC_TMRCTL0_CNT_Pos)

#define SC_TMRCTL0_OPMODE_Pos            (24)

#define SC_TMRCTL0_OPMODE_Msk            (0xful << SC_TMRCTL0_OPMODE_Pos)

#define SC_TMRCTL1_CNT_Pos               (0)

#define SC_TMRCTL1_CNT_Msk               (0xfful << SC_TMRCTL1_CNT_Pos)

#define SC_TMRCTL1_OPMODE_Pos            (24)

#define SC_TMRCTL1_OPMODE_Msk            (0xful << SC_TMRCTL1_OPMODE_Pos)

#define SC_TMRCTL2_CNT_Pos               (0)

#define SC_TMRCTL2_CNT_Msk               (0xfful << SC_TMRCTL2_CNT_Pos)

#define SC_TMRCTL2_OPMODE_Pos            (24)

#define SC_TMRCTL2_OPMODE_Msk            (0xful << SC_TMRCTL2_OPMODE_Pos)

#define SC_UARTCTL_UARTEN_Pos            (0)

#define SC_UARTCTL_UARTEN_Msk            (0x1ul << SC_UARTCTL_UARTEN_Pos)

#define SC_UARTCTL_WLS_Pos               (4)

#define SC_UARTCTL_WLS_Msk               (0x3ul << SC_UARTCTL_WLS10_Pos)

#define SC_UARTCTL_PBOFF_Pos             (6)

#define SC_UARTCTL_PBOFF_Msk             (0x1ul << SC_UARTCTL_PBOFF_Pos)

#define SC_UARTCTL_OPE_Pos               (7)

#define SC_UARTCTL_OPE_Msk               (0x1ul << SC_UARTCTL_OPE_Pos)

#define SC_TMRDAT0_CNT0_Pos              (0)

#define SC_TMRDAT0_CNT0_Msk              (0xfffffful << SC_TMRDAT0_CNT0_Pos)

#define SC_TMRDAT1_2_CNT1_Pos            (0)

#define SC_TMRDAT1_2_CNT1_Msk            (0xfful << SC_TMRDAT1_2_CNT1_Pos)

#define SC_TMRDAT1_2_CNT2_Pos            (8)

#define SC_TMRDAT1_2_CNT2_Msk            (0xfful << SC_TMRDAT1_2_CNT2_Pos)           /* SC_CONST */ /* end of SC register group */


/*---------------------- Serial Peripheral Interface Controller -------------------------*/

typedef struct

{


    __IO uint32_t CTL;           /* Offset: 0x00  Control Register                                                   */

    __IO uint32_t CLKDIV;        /* Offset: 0x04  Clock Divider Register                                             */

    __IO uint32_t SSCTL;         /* Offset: 0x08  Slave Select Control Register                                      */

    __IO uint32_t PDMACTL;       /* Offset: 0x0C  SPI PDMA Control Register                                          */

    __IO uint32_t FIFOCTL;       /* Offset: 0x10  SPI FIFO Control Register                                          */

    __IO uint32_t STATUS;        /* Offset: 0x14  SPI Status Register                                                */

    __I  uint32_t RESERVE0[2];

    __O  uint32_t TX;            /* Offset: 0x20  Data Transmit Register                                             */

    __I  uint32_t RESERVE1[3];

    __I  uint32_t RX;            /* Offset: 0x30  Data Receive Register                                              */

    __I  uint32_t RESERVE2[11];

    __IO uint32_t I2SCTL;        /* Offset: 0x60  I2S Control Register                                               */

    __IO uint32_t I2SCLK;        /* Offset: 0x64  I2S Clock Divider Control Register                                 */

    __IO uint32_t I2SSTS;        /* Offset: 0x68  I2S Status Register                                                */


} SPI_T;


#define SPI_CTL_SPIEN_Pos                (0)

#define SPI_CTL_SPIEN_Msk                (0x1ul << SPI_CTL_SPIEN_Pos)

#define SPI_CTL_RXNEG_Pos                (1)

#define SPI_CTL_RXNEG_Msk                (0x1ul << SPI_CTL_RXNEG_Pos)

#define SPI_CTL_TXNEG_Pos                (2)

#define SPI_CTL_TXNEG_Msk                (0x1ul << SPI_CTL_TXNEG_Pos)

#define SPI_CTL_CLKPOL_Pos               (3)

#define SPI_CTL_CLKPOL_Msk               (0x1ul << SPI_CTL_CLKPOL_Pos)

#define SPI_CTL_SUSPITV_Pos              (4)

#define SPI_CTL_SUSPITV_Msk              (0xful << SPI_CTL_SUSPITV_Pos)

#define SPI_CTL_DWIDTH_Pos               (8)

#define SPI_CTL_DWIDTH_Msk               (0x1ful << SPI_CTL_DWIDTH_Pos)

#define SPI_CTL_LSB_Pos                  (13)

#define SPI_CTL_LSB_Msk                  (0x1ul << SPI_CTL_LSB_Pos)

#define SPI_CTL_TWOBIT_Pos               (16)

#define SPI_CTL_TWOBIT_Msk               (0x1ul << SPI_CTL_TWOBIT_Pos)

#define SPI_CTL_UNITIEN_Pos              (17)

#define SPI_CTL_UNITIEN_Msk              (0x1ul << SPI_CTL_UNITIEN_Pos)

#define SPI_CTL_SLAVE_Pos                (18)

#define SPI_CTL_SLAVE_Msk                (0x1ul << SPI_CTL_SLAVE_Pos)

#define SPI_CTL_REORDER_Pos              (19)

#define SPI_CTL_REORDER_Msk              (0x1ul << SPI_CTL_REORDER_Pos)

#define SPI_CTL_QDIODIR_Pos              (20)

#define SPI_CTL_QDIODIR_Msk              (0x1ul << SPI_CTL_QDIODIR_Pos)

#define SPI_CTL_DUALIOEN_Pos             (21)

#define SPI_CTL_DUALIOEN_Msk             (0x1ul << SPI_CTL_DUALIOEN_Pos)

#define SPI_CTL_QUADIOEN_Pos             (22)

#define SPI_CTL_QUADIOEN_Msk             (0x1ul << SPI_CTL_QUADIOEN_Pos)

#define SPI_CLKDIV_DIVIDER_Pos           (0)

#define SPI_CLKDIV_DIVIDER_Msk           (0xfful << SPI_CLKDIV_DIVIDER_Pos)

#define SPI_SSCTL_SS_Pos                 (0)

#define SPI_SSCTL_SS_Msk                 (0x1ul << SPI_SSCTL_SS_Pos)

#define SPI_SSCTL_SSACTPOL_Pos           (2)

#define SPI_SSCTL_SSACTPOL_Msk           (0x1ul << SPI_SSCTL_SSACTPOL_Pos)

#define SPI_SSCTL_AUTOSS_Pos             (3)

#define SPI_SSCTL_AUTOSS_Msk             (0x1ul << SPI_SSCTL_AUTOSS_Pos)

#define SPI_SSCTL_SLV3WIRE_Pos           (4)

#define SPI_SSCTL_SLV3WIRE_Msk           (0x1ul << SPI_SSCTL_SLV3WIRE_Pos)

#define SPI_SSCTL_SLVTOIEN_Pos           (5)

#define SPI_SSCTL_SLVTOIEN_Msk           (0x1ul << SPI_SSCTL_SLVTOIEN_Pos)

#define SPI_SSCTL_SLVTORST_Pos           (6)

#define SPI_SSCTL_SLVTORST_Msk           (0x1ul << SPI_SSCTL_SLVTORST_Pos)

#define SPI_SSCTL_SLVBEIEN_Pos           (8)

#define SPI_SSCTL_SLVBEIEN_Msk           (0x1ul << SPI_SSCTL_SLVBEIEN_Pos)

#define SPI_SSCTL_SLVURIEN_Pos           (9)

#define SPI_SSCTL_SLVURIEN_Msk           (0x1ul << SPI_SSCTL_SLVURIEN_Pos)

#define SPI_SSCTL_SSACTIEN_Pos           (12)

#define SPI_SSCTL_SSACTIEN_Msk           (0x1ul << SPI_SSCTL_SSACTIEN_Pos)

#define SPI_SSCTL_SSINAIEN_Pos           (13)

#define SPI_SSCTL_SSINAIEN_Msk           (0x1ul << SPI_SSCTL_SSINAIEN_Pos)

#define SPI_SSCTL_SLVTOCNT_Pos           (16)

#define SPI_SSCTL_SLVTOCNT_Msk           (0xfffful << SPI_SSCTL_SLVTOCNT_Pos)

#define SPI_PDMACTL_TXPDMAEN_Pos         (0)

#define SPI_PDMACTL_TXPDMAEN_Msk         (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos)

#define SPI_PDMACTL_RXPDMAEN_Pos         (1)

#define SPI_PDMACTL_RXPDMAEN_Msk         (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos)

#define SPI_PDMACTL_PDMARST_Pos          (2)

#define SPI_PDMACTL_PDMARST_Msk          (0x1ul << SPI_PDMACTL_PDMARST_Pos)

#define SPI_FIFOCTL_RXRST_Pos            (0)

#define SPI_FIFOCTL_RXRST_Msk            (0x1ul << SPI_FIFOCTL_RXRST_Pos)

#define SPI_FIFOCTL_TXRST_Pos            (1)

#define SPI_FIFOCTL_TXRST_Msk            (0x1ul << SPI_FIFOCTL_TXRST_Pos)

#define SPI_FIFOCTL_RXTHIEN_Pos          (2)

#define SPI_FIFOCTL_RXTHIEN_Msk          (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos)

#define SPI_FIFOCTL_TXTHIEN_Pos          (3)

#define SPI_FIFOCTL_TXTHIEN_Msk          (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos)

#define SPI_FIFOCTL_RXTOIEN_Pos          (4)

#define SPI_FIFOCTL_RXTOIEN_Msk          (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos)

#define SPI_FIFOCTL_RXOVIEN_Pos          (5)

#define SPI_FIFOCTL_RXOVIEN_Msk          (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos)

#define SPI_FIFOCTL_TXUFPOL_Pos          (6)

#define SPI_FIFOCTL_TXUFPOL_Msk          (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos)

#define SPI_FIFOCTL_TXUFIEN_Pos          (7)

#define SPI_FIFOCTL_TXUFIEN_Msk          (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos)

#define SPI_FIFOCTL_RXFBCLR_Pos          (8)

#define SPI_FIFOCTL_RXFBCLR_Msk          (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos)

#define SPI_FIFOCTL_TXFBCLR_Pos          (9)

#define SPI_FIFOCTL_TXFBCLR_Msk          (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos)

#define SPI_FIFOCTL_RXTH_Pos             (24)

#define SPI_FIFOCTL_RXTH_Msk             (0x7ul << SPI_FIFOCTL_RXTH_Pos)

#define SPI_FIFOCTL_TXTH_Pos             (28)

#define SPI_FIFOCTL_TXTH_Msk             (0x7ul << SPI_FIFOCTL_TXTH_Pos)

#define SPI_STATUS_BUSY_Pos              (0)

#define SPI_STATUS_BUSY_Msk              (0x1ul << SPI_STATUS_BUSY_Pos)

#define SPI_STATUS_UNITIF_Pos            (1)

#define SPI_STATUS_UNITIF_Msk            (0x1ul << SPI_STATUS_UNITIF_Pos)

#define SPI_STATUS_SSACTIF_Pos           (2)

#define SPI_STATUS_SSACTIF_Msk           (0x1ul << SPI_STATUS_SSACTIF_Pos)

#define SPI_STATUS_SSINAIF_Pos           (3)

#define SPI_STATUS_SSINAIF_Msk           (0x1ul << SPI_STATUS_SSINAIF_Pos)

#define SPI_STATUS_SSLINE_Pos            (4)

#define SPI_STATUS_SSLINE_Msk            (0x1ul << SPI_STATUS_SSLINE_Pos)

#define SPI_STATUS_SLVTOIF_Pos           (5)

#define SPI_STATUS_SLVTOIF_Msk           (0x1ul << SPI_STATUS_SLVTOIF_Pos)

#define SPI_STATUS_SLVBEIF_Pos           (6)

#define SPI_STATUS_SLVBEIF_Msk           (0x1ul << SPI_STATUS_SLVBEIF_Pos)

#define SPI_STATUS_SLVURIF_Pos           (7)

#define SPI_STATUS_SLVURIF_Msk           (0x1ul << SPI_STATUS_SLVURIF_Pos)

#define SPI_STATUS_RXEMPTY_Pos           (8)

#define SPI_STATUS_RXEMPTY_Msk           (0x1ul << SPI_STATUS_RXEMPTY_Pos)

#define SPI_STATUS_RXFULL_Pos            (9)

#define SPI_STATUS_RXFULL_Msk            (0x1ul << SPI_STATUS_RXFULL_Pos)

#define SPI_STATUS_RXTHIF_Pos            (10)

#define SPI_STATUS_RXTHIF_Msk            (0x1ul << SPI_STATUS_RXTHIF_Pos)

#define SPI_STATUS_RXOVIF_Pos            (11)

#define SPI_STATUS_RXOVIF_Msk            (0x1ul << SPI_STATUS_RXOVIF_Pos)

#define SPI_STATUS_RXTOIF_Pos            (12)

#define SPI_STATUS_RXTOIF_Msk            (0x1ul << SPI_STATUS_RXTOIF_Pos)

#define SPI_STATUS_SPIENSTS_Pos          (15)

#define SPI_STATUS_SPIENSTS_Msk          (0x1ul << SPI_STATUS_SPIENSTS_Pos)

#define SPI_STATUS_TXEMPTY_Pos           (16)

#define SPI_STATUS_TXEMPTY_Msk           (0x1ul << SPI_STATUS_TXEMPTY_Pos)

#define SPI_STATUS_TXFULL_Pos            (17)

#define SPI_STATUS_TXFULL_Msk            (0x1ul << SPI_STATUS_TXFULL_Pos)

#define SPI_STATUS_TXTHIF_Pos            (18)

#define SPI_STATUS_TXTHIF_Msk            (0x1ul << SPI_STATUS_TXTHIF_Pos)

#define SPI_STATUS_TXUFIF_Pos            (19)

#define SPI_STATUS_TXUFIF_Msk            (0x1ul << SPI_STATUS_TXUFIF_Pos)

#define SPI_STATUS_TXRXRST_Pos           (23)

#define SPI_STATUS_TXRXRST_Msk           (0x1ul << SPI_STATUS_TXRXRST_Pos)

#define SPI_STATUS_RXCNT_Pos             (24)

#define SPI_STATUS_RXCNT_Msk             (0xful << SPI_STATUS_RXCNT_Pos)

#define SPI_STATUS_TXCNT_Pos             (28)

#define SPI_STATUS_TXCNT_Msk             (0xful << SPI_STATUS_TXCNT_Pos)

#define SPI_TX_TX_Pos                    (0)

#define SPI_TX_TX_Msk                    (0xfffffffful << SPI_TX_TX_Pos)

#define SPI_RX_RX_Pos                    (0)

#define SPI_RX_RX_Msk                    (0xfffffffful << SPI_RX_RX_Pos)

#define SPI_I2SCTL_I2SEN_Pos             (0)

#define SPI_I2SCTL_I2SEN_Msk             (0x1ul << SPI_I2SCTL_I2SEN_Pos)

#define SPI_I2SCTL_TXEN_Pos              (1)

#define SPI_I2SCTL_TXEN_Msk              (0x1ul << SPI_I2SCTL_TXEN_Pos)

#define SPI_I2SCTL_RXEN_Pos              (2)

#define SPI_I2SCTL_RXEN_Msk              (0x1ul << SPI_I2SCTL_RXEN_Pos)

#define SPI_I2SCTL_MUTE_Pos              (3)

#define SPI_I2SCTL_MUTE_Msk              (0x1ul << SPI_I2SCTL_MUTE_Pos)

#define SPI_I2SCTL_WDWIDTH_Pos           (4)

#define SPI_I2SCTL_WDWIDTH_Msk           (0x3ul << SPI_I2SCTL_WDWIDTH_Pos)

#define SPI_I2SCTL_MONO_Pos              (6)

#define SPI_I2SCTL_MONO_Msk              (0x1ul << SPI_I2SCTL_MONO_Pos)

#define SPI_I2SCTL_ORDER_Pos             (7)

#define SPI_I2SCTL_ORDER_Msk             (0x1ul << SPI_I2SCTL_ORDER_Pos)

#define SPI_I2SCTL_SLAVE_Pos             (8)

#define SPI_I2SCTL_SLAVE_Msk             (0x1ul << SPI_I2SCTL_SLAVE_Pos)

#define SPI_I2SCTL_MCLKEN_Pos            (15)

#define SPI_I2SCTL_MCLKEN_Msk            (0x1ul << SPI_I2SCTL_MCLKEN_Pos)

#define SPI_I2SCTL_RZCEN_Pos             (16)

#define SPI_I2SCTL_RZCEN_Msk             (0x1ul << SPI_I2SCTL_RZCEN_Pos)

#define SPI_I2SCTL_LZCEN_Pos             (17)

#define SPI_I2SCTL_LZCEN_Msk             (0x1ul << SPI_I2SCTL_LZCEN_Pos)

#define SPI_I2SCTL_RXLCH_Pos             (23)

#define SPI_I2SCTL_RXLCH_Msk             (0x1ul << SPI_I2SCTL_RXLCH_Pos)

#define SPI_I2SCTL_RZCIEN_Pos            (24)

#define SPI_I2SCTL_RZCIEN_Msk            (0x1ul << SPI_I2SCTL_RZCIEN_Pos)

#define SPI_I2SCTL_LZCIEN_Pos            (25)

#define SPI_I2SCTL_LZCIEN_Msk            (0x1ul << SPI_I2SCTL_LZCIEN_Pos)

#define SPI_I2SCTL_FORMAT_Pos            (28)

#define SPI_I2SCTL_FORMAT_Msk            (0x3ul << SPI_I2SCTL_FORMAT_Pos)

#define SPI_I2SCLK_MCLKDIV_Pos           (0)

#define SPI_I2SCLK_MCLKDIV_Msk           (0x3ful << SPI_I2SCLK_MCLKDIV_Pos)

#define SPI_I2SCLK_BCLKDIV_Pos           (8)

#define SPI_I2SCLK_BCLKDIV_Msk           (0x1fful << SPI_I2SCLK_BCLKDIV_Pos)

#define SPI_I2SSTS_RIGHT_Pos             (4)

#define SPI_I2SSTS_RIGHT_Msk             (0x1ul << SPI_I2SSTS_RIGHT_Pos)

#define SPI_I2SSTS_RXEMPTY_Pos           (8)

#define SPI_I2SSTS_RXEMPTY_Msk           (0x1ul << SPI_I2SSTS_RXEMPTY_Pos)

#define SPI_I2SSTS_RXFULL_Pos            (9)

#define SPI_I2SSTS_RXFULL_Msk            (0x1ul << SPI_I2SSTS_RXFULL_Pos)

#define SPI_I2SSTS_RXTHIF_Pos            (10)

#define SPI_I2SSTS_RXTHIF_Msk            (0x1ul << SPI_I2SSTS_RXTHIF_Pos)

#define SPI_I2SSTS_RXOVIF_Pos            (11)

#define SPI_I2SSTS_RXOVIF_Msk            (0x1ul << SPI_I2SSTS_RXOVIF_Pos)

#define SPI_I2SSTS_RXTOIF_Pos            (12)

#define SPI_I2SSTS_RXTOIF_Msk            (0x1ul << SPI_I2SSTS_RXTOIF_Pos)

#define SPI_I2SSTS_I2SENSTS_Pos          (15)

#define SPI_I2SSTS_I2SENSTS_Msk          (0x1ul << SPI_I2SSTS_I2SENSTS_Pos)

#define SPI_I2SSTS_TXEMPTY_Pos           (16)

#define SPI_I2SSTS_TXEMPTY_Msk           (0x1ul << SPI_I2SSTS_TXEMPTY_Pos)

#define SPI_I2SSTS_TXFULL_Pos            (17)

#define SPI_I2SSTS_TXFULL_Msk            (0x1ul << SPI_I2SSTS_TXFULL_Pos)

#define SPI_I2SSTS_TXTHIF_Pos            (18)

#define SPI_I2SSTS_TXTHIF_Msk            (0x1ul << SPI_I2SSTS_TXTHIF_Pos)

#define SPI_I2SSTS_TXUFIF_Pos            (19)

#define SPI_I2SSTS_TXUFIF_Msk            (0x1ul << SPI_I2SSTS_TXUFIF_Pos)

#define SPI_I2SSTS_RZCIF_Pos             (20)

#define SPI_I2SSTS_RZCIF_Msk             (0x1ul << SPI_I2SSTS_RZCIF_Pos)

#define SPI_I2SSTS_LZCIF_Pos             (21)

#define SPI_I2SSTS_LZCIF_Msk             (0x1ul << SPI_I2SSTS_LZCIF_Pos)

#define SPI_I2SSTS_TXRXRST_Pos           (23)

#define SPI_I2SSTS_TXRXRST_Msk           (0x1ul << SPI_I2SSTS_TXRXRST_Pos)

#define SPI_I2SSTS_RXCNT_Pos             (24)

#define SPI_I2SSTS_RXCNT_Msk             (0x7ul << SPI_I2SSTS_RXCNT_Pos)

#define SPI_I2SSTS_TXCNT_Pos             (28)

#define SPI_I2SSTS_TXCNT_Msk             (0x7ul << SPI_I2SSTS_TXCNT_Pos)                    /* SPI_CONST */ /* end of SPI register group */


/*---------------------- System Manger Controller -------------------------*/

typedef struct

{


    __I  uint32_t PDID;          /* Offset: 0x00  Part Device Identification Number Register                         */

    __IO uint32_t RSTSTS;        /* Offset: 0x04  System Reset Status Register                                       */

    __IO uint32_t IPRST0;        /* Offset: 0x08  Peripheral  Reset Control Register 0                               */

    __IO uint32_t IPRST1;        /* Offset: 0x0C  Peripheral Reset Control Register 1                                */

    __IO uint32_t IPRST2;        /* Offset: 0x10  Peripheral Reset Control Register 2                                */

    __I  uint32_t RESERVE0[1];

    __IO uint32_t BODCTL;        /* Offset: 0x18  Brown-Out Detector Control Register                                */

    __IO uint32_t IVSCTL;        /* Offset: 0x1C  Internal Voltage Source Control Register                           */

    __I  uint32_t RESERVE1[1];

    __IO uint32_t PORCTL;        /* Offset: 0x24  Power-On-Reset Controller Register                                 */

    __IO uint32_t VREFCTL;       /* Offset: 0x28  VREF Control Register                                              */

    __IO uint32_t USBPHY;        /* Offset: 0x2C  USB PHY Control Register                                           */

    __IO uint32_t GPA_MFPL;      /* Offset: 0x30  GPIOA Low Byte Multiple Function Control Register                  */

    __IO uint32_t GPA_MFPH;      /* Offset: 0x34  GPIOA High Byte Multiple Function Control Register                 */

    __IO uint32_t GPB_MFPL;      /* Offset: 0x38  GPIOB Low Byte Multiple Function Control Register                  */

    __IO uint32_t GPB_MFPH;      /* Offset: 0x3C  GPIOB High Byte Multiple Function Control Register                 */

    __IO uint32_t GPC_MFPL;      /* Offset: 0x40  GPIOC Low Byte Multiple Function Control Register                  */

    __IO uint32_t GPC_MFPH;      /* Offset: 0x44  GPIOC High Byte Multiple Function Control Register                 */

    __IO uint32_t GPD_MFPL;      /* Offset: 0x48  GPIOD Low Byte Multiple Function Control Register                  */

    __IO uint32_t GPD_MFPH;      /* Offset: 0x4C  GPIOD High Byte Multiple Function Control Register                 */

    __IO uint32_t GPE_MFPL;      /* Offset: 0x50  GPIOE Low Byte Multiple Function Control Register                  */

    __IO uint32_t GPE_MFPH;      /* Offset: 0x54  GPIOE High Byte Multiple Function Control Register                 */

    __IO uint32_t GPF_MFPL;      /* Offset: 0x58  GPIOF Low Byte Multiple Function Control Register                  */

    __I  uint32_t RESERVE2[29];

    __IO uint32_t SRAM_BISTCTL;  /* Offset: 0xD0  System SRAM BIST Test Control Register                             */

    __I  uint32_t SRAM_BISTSTS;  /* Offset: 0xD4  System SRAM BIST Test Status Register                              */

    __I  uint32_t RESERVE3[6];

    __IO uint32_t IRCTCTL;       /* Offset: 0xF0  IRC Trim Control Register                                          */

    __IO uint32_t IRCTIEN;       /* Offset: 0xF4  IRC Trim Interrupt Enable Register                                 */

    __IO uint32_t IRCTISTS;      /* Offset: 0xF8  IRC Trim Interrupt Status Register                                 */

    __I  uint32_t RESERVE4[1];

    __IO uint32_t REGLCTL;       /* Offset: 0x100  Register Lock Control Register                                    */

    __I  uint32_t RESERVE5[11];

    __IO uint32_t IRC48MTCTL;    /* Offset: 0x130 IRC48M Trim Control Register                                       */

    __IO uint32_t IRC48MTIEN;    /* Offset: 0x134 IRC48M Trim Interrupt Enable Register                              */

    __IO uint32_t IRC48MTISTS;   /* Offset: 0x138 IRC48M Trim Interrupt Status Register                              */

} SYS_T;


#define SYS_PDID_PDID_Pos                (0)

#define SYS_PDID_PDID_Msk                (0xfffffffful << SYS_PDID_PDID_Pos)

#define SYS_RSTSTS_PORF_Pos              (0)

#define SYS_RSTSTS_PORF_Msk              (0x1ul << SYS_RSTSTS_PORF_Pos)

#define SYS_RSTSTS_PINRF_Pos             (1)

#define SYS_RSTSTS_PINRF_Msk             (0x1ul << SYS_RSTSTS_PINRF_Pos)

#define SYS_RSTSTS_WDTRF_Pos             (2)

#define SYS_RSTSTS_WDTRF_Msk             (0x1ul << SYS_RSTSTS_WDTRF_Pos)

#define SYS_RSTSTS_LVRF_Pos              (3)

#define SYS_RSTSTS_LVRF_Msk              (0x1ul << SYS_RSTSTS_LVRF_Pos)

#define SYS_RSTSTS_BODRF_Pos             (4)

#define SYS_RSTSTS_BODRF_Msk             (0x1ul << SYS_RSTSTS_BODRF_Pos)

#define SYS_RSTSTS_SYSRF_Pos             (5)

#define SYS_RSTSTS_SYSRF_Msk             (0x1ul << SYS_RSTSTS_SYSRF_Pos)

#define SYS_RSTSTS_CPURF_Pos             (7)

#define SYS_RSTSTS_CPURF_Msk             (0x1ul << SYS_RSTSTS_CPURF_Pos)

#define SYS_RSTSTS_CPULKRF_Pos           (8)

#define SYS_RSTSTS_CPULKRF_Msk           (0x1ul << SYS_RSTSTS_CPULKRF_Pos)

#define SYS_IPRST0_CHIPRST_Pos           (0)

#define SYS_IPRST0_CHIPRST_Msk           (0x1ul << SYS_IPRST0_CHIPRST_Pos)

#define SYS_IPRST0_CPURST_Pos            (1)

#define SYS_IPRST0_CPURST_Msk            (0x1ul << SYS_IPRST0_CPURST_Pos)

#define SYS_IPRST0_PDMARST_Pos           (2)

#define SYS_IPRST0_PDMARST_Msk           (0x1ul << SYS_IPRST0_PDMARST_Pos)

#define SYS_IPRST0_EBIRST_Pos            (3)

#define SYS_IPRST0_EBIRST_Msk            (0x1ul << SYS_IPRST0_EBIRST_Pos)

#define SYS_IPRST0_USBHRST_Pos           (4)

#define SYS_IPRST0_USBHRST_Msk           (0x1ul << SYS_IPRST0_USBHRST_Pos)

#define SYS_IPRST0_CRCRST_Pos            (7)

#define SYS_IPRST0_CRCRST_Msk            (0x1ul << SYS_IPRST0_CRCRST_Pos)

#define SYS_IPRST1_GPIORST_Pos           (1)

#define SYS_IPRST1_GPIORST_Msk           (0x1ul << SYS_IPRST1_GPIORST_Pos)

#define SYS_IPRST1_TMR0RST_Pos           (2)

#define SYS_IPRST1_TMR0RST_Msk           (0x1ul << SYS_IPRST1_TMR0RST_Pos)

#define SYS_IPRST1_TMR1RST_Pos           (3)

#define SYS_IPRST1_TMR1RST_Msk           (0x1ul << SYS_IPRST1_TMR1RST_Pos)

#define SYS_IPRST1_TMR2RST_Pos           (4)

#define SYS_IPRST1_TMR2RST_Msk           (0x1ul << SYS_IPRST1_TMR2RST_Pos)

#define SYS_IPRST1_TMR3RST_Pos           (5)

#define SYS_IPRST1_TMR3RST_Msk           (0x1ul << SYS_IPRST1_TMR3RST_Pos)

#define SYS_IPRST1_I2C0RST_Pos           (8)

#define SYS_IPRST1_I2C0RST_Msk           (0x1ul << SYS_IPRST1_I2C0RST_Pos)

#define SYS_IPRST1_I2C1RST_Pos           (9)

#define SYS_IPRST1_I2C1RST_Msk           (0x1ul << SYS_IPRST1_I2C1RST_Pos)

#define SYS_IPRST1_SPI0RST_Pos           (12)

#define SYS_IPRST1_SPI0RST_Msk           (0x1ul << SYS_IPRST1_SPI0RST_Pos)

#define SYS_IPRST1_SPI1RST_Pos           (13)

#define SYS_IPRST1_SPI1RST_Msk           (0x1ul << SYS_IPRST1_SPI1RST_Pos)

#define SYS_IPRST1_UART0RST_Pos          (16)

#define SYS_IPRST1_UART0RST_Msk          (0x1ul << SYS_IPRST1_UART0RST_Pos)

#define SYS_IPRST1_UART1RST_Pos          (17)

#define SYS_IPRST1_UART1RST_Msk          (0x1ul << SYS_IPRST1_UART1RST_Pos)

#define SYS_IPRST1_UART2RST_Pos          (18)

#define SYS_IPRST1_UART2RST_Msk          (0x1ul << SYS_IPRST1_UART2RST_Pos)

#define SYS_IPRST1_UART3RST_Pos          (19)

#define SYS_IPRST1_UART3RST_Msk          (0x1ul << SYS_IPRST1_UART3RST_Pos)

#define SYS_IPRST1_USBDRST_Pos           (27)

#define SYS_IPRST1_USBDRST_Msk           (0x1ul << SYS_IPRST1_USBDRST_Pos)

#define SYS_IPRST1_EADCRST_Pos           (28)

#define SYS_IPRST1_EADCRST_Msk           (0x1ul << SYS_IPRST1_EADCRST_Pos)

#define SYS_IPRST2_SC0RST_Pos            (0)

#define SYS_IPRST2_SC0RST_Msk            (0x1ul << SYS_IPRST2_SC0RST_Pos)

#define SYS_IPRST2_PWM0RST_Pos           (16)

#define SYS_IPRST2_PWM0RST_Msk           (0x1ul << SYS_IPRST2_PWM0RST_Pos)

#define SYS_IPRST2_PWM1RST_Pos           (17)

#define SYS_IPRST2_PWM1RST_Msk           (0x1ul << SYS_IPRST2_PWM1RST_Pos)

#define SYS_IPRST2_TKRST_Pos             (25)

#define SYS_IPRST2_TKRST_Msk             (0x1ul << SYS_IPRST2_TKRST_Pos)

#define SYS_BODCTL_BODEN_Pos             (0)

#define SYS_BODCTL_BODEN_Msk             (0x1ul << SYS_BODCTL_BODEN_Pos)

#define SYS_BODCTL_BODVL_Pos             (1)

#define SYS_BODCTL_BODVL_Msk             (0x3ul << SYS_BODCTL_BODVL_Pos)

#define SYS_BODCTL_BODRSTEN_Pos          (3)

#define SYS_BODCTL_BODRSTEN_Msk          (0x1ul << SYS_BODCTL_BODRSTEN_Pos)

#define SYS_BODCTL_BODIF_Pos             (4)

#define SYS_BODCTL_BODIF_Msk             (0x1ul << SYS_BODCTL_BODIF_Pos)

#define SYS_BODCTL_BODLPM_Pos            (5)

#define SYS_BODCTL_BODLPM_Msk            (0x1ul << SYS_BODCTL_BODLPM_Pos)

#define SYS_BODCTL_BODOUT_Pos            (6)

#define SYS_BODCTL_BODOUT_Msk            (0x1ul << SYS_BODCTL_BODOUT_Pos)

#define SYS_BODCTL_LVREN_Pos             (7)

#define SYS_BODCTL_LVREN_Msk             (0x1ul << SYS_BODCTL_LVREN_Pos)

#define SYS_BODCTL_BODDGSEL_Pos          (8)

#define SYS_BODCTL_BODDGSEL_Msk          (0x7ul << SYS_BODCTL_BODDGSEL_Pos)

#define SYS_BODCTL_LVRDGSEL_Pos          (12)

#define SYS_BODCTL_LVRDGSEL_Msk          (0x7ul << SYS_BODCTL_LVRDGSEL_Pos)

#define SYS_IVSCTL_VTEMPEN_Pos           (0)

#define SYS_IVSCTL_VTEMPEN_Msk           (0x1ul << SYS_IVSCTL_VTEMPEN_Pos)

#define SYS_IVSCTL_VBATUGEN_Pos          (1)

#define SYS_IVSCTL_VBATUGEN_Msk          (0x1ul << SYS_IVSCTL_VBATUGEN_Pos)

#define SYS_PORCTL_POROFF_Pos            (0)

#define SYS_PORCTL_POROFF_Msk            (0xfffful << SYS_PORCTL_POROFF_Pos)

#define SYS_VREFCTL_VREFCTL_Pos          (0)

#define SYS_VREFCTL_VREFCTL_Msk          (0x1ful << SYS_VREFCTL_VREFCTL_Pos)

#define SYS_USBPHY_USBROLE_Pos           (0)

#define SYS_USBPHY_USBROLE_Msk           (0x3ul << SYS_USBPHY_USBROLE_Pos)

#define SYS_USBPHY_LDO33EN_Pos           (8)

#define SYS_USBPHY_LDO33EN_Msk           (0x1ul << SYS_USBPHY_LDO33EN_Pos)

#define SYS_GPA_MFPL_PA0MFP_Pos          (0)

#define SYS_GPA_MFPL_PA0MFP_Msk          (0xful << SYS_GPA_MFPL_PA0MFP_Pos)

#define SYS_GPA_MFPL_PA1MFP_Pos          (4)

#define SYS_GPA_MFPL_PA1MFP_Msk          (0xful << SYS_GPA_MFPL_PA1MFP_Pos)

#define SYS_GPA_MFPL_PA2MFP_Pos          (8)

#define SYS_GPA_MFPL_PA2MFP_Msk          (0xful << SYS_GPA_MFPL_PA2MFP_Pos)

#define SYS_GPA_MFPL_PA3MFP_Pos          (12)

#define SYS_GPA_MFPL_PA3MFP_Msk          (0xful << SYS_GPA_MFPL_PA3MFP_Pos)

#define SYS_GPA_MFPL_PA4MFP_Pos          (16)

#define SYS_GPA_MFPL_PA4MFP_Msk          (0xful << SYS_GPA_MFPL_PA4MFP_Pos)

#define SYS_GPA_MFPL_PA5MFP_Pos          (20)

#define SYS_GPA_MFPL_PA5MFP_Msk          (0xful << SYS_GPA_MFPL_PA5MFP_Pos)

#define SYS_GPA_MFPL_PA6MFP_Pos          (24)

#define SYS_GPA_MFPL_PA6MFP_Msk          (0xful << SYS_GPA_MFPL_PA6MFP_Pos)

#define SYS_GPA_MFPL_PA7MFP_Pos          (28)

#define SYS_GPA_MFPL_PA7MFP_Msk          (0xful << SYS_GPA_MFPL_PA7MFP_Pos)

#define SYS_GPA_MFPH_PA8MFP_Pos          (0)

#define SYS_GPA_MFPH_PA8MFP_Msk          (0xful << SYS_GPA_MFPH_PA8MFP_Pos)

#define SYS_GPA_MFPH_PA9MFP_Pos          (4)

#define SYS_GPA_MFPH_PA9MFP_Msk          (0xful << SYS_GPA_MFPH_PA9MFP_Pos)

#define SYS_GPA_MFPH_PA10MFP_Pos         (8)

#define SYS_GPA_MFPH_PA10MFP_Msk         (0xful << SYS_GPA_MFPH_PA10MFP_Pos)

#define SYS_GPA_MFPH_PA11MFP_Pos         (12)

#define SYS_GPA_MFPH_PA11MFP_Msk         (0xful << SYS_GPA_MFPH_PA11MFP_Pos)

#define SYS_GPA_MFPH_PA12MFP_Pos         (16)

#define SYS_GPA_MFPH_PA12MFP_Msk         (0xful << SYS_GPA_MFPH_PA12MFP_Pos)

#define SYS_GPA_MFPH_PA13MFP_Pos         (20)

#define SYS_GPA_MFPH_PA13MFP_Msk         (0xful << SYS_GPA_MFPH_PA13MFP_Pos)

#define SYS_GPA_MFPH_PA14MFP_Pos         (24)

#define SYS_GPA_MFPH_PA14MFP_Msk         (0xful << SYS_GPA_MFPH_PA14MFP_Pos)

#define SYS_GPA_MFPH_PA15MFP_Pos         (28)

#define SYS_GPA_MFPH_PA15MFP_Msk         (0xful << SYS_GPA_MFPH_PA15MFP_Pos)

#define SYS_GPB_MFPL_PB0MFP_Pos          (0)

#define SYS_GPB_MFPL_PB0MFP_Msk          (0xful << SYS_GPB_MFPL_PB0MFP_Pos)

#define SYS_GPB_MFPL_PB1MFP_Pos          (4)

#define SYS_GPB_MFPL_PB1MFP_Msk          (0xful << SYS_GPB_MFPL_PB1MFP_Pos)

#define SYS_GPB_MFPL_PB2MFP_Pos          (8)

#define SYS_GPB_MFPL_PB2MFP_Msk          (0xful << SYS_GPB_MFPL_PB2MFP_Pos)

#define SYS_GPB_MFPL_PB3MFP_Pos          (12)

#define SYS_GPB_MFPL_PB3MFP_Msk          (0xful << SYS_GPB_MFPL_PB3MFP_Pos)

#define SYS_GPB_MFPL_PB4MFP_Pos          (16)

#define SYS_GPB_MFPL_PB4MFP_Msk          (0xful << SYS_GPB_MFPL_PB4MFP_Pos)

#define SYS_GPB_MFPL_PB5MFP_Pos          (20)

#define SYS_GPB_MFPL_PB5MFP_Msk          (0xful << SYS_GPB_MFPL_PB5MFP_Pos)

#define SYS_GPB_MFPL_PB6MFP_Pos          (24)

#define SYS_GPB_MFPL_PB6MFP_Msk          (0xful << SYS_GPB_MFPL_PB6MFP_Pos)

#define SYS_GPB_MFPL_PB7MFP_Pos          (28)

#define SYS_GPB_MFPL_PB7MFP_Msk          (0xful << SYS_GPB_MFPL_PB7MFP_Pos)

#define SYS_GPB_MFPH_PB8MFP_Pos          (0)

#define SYS_GPB_MFPH_PB8MFP_Msk          (0xful << SYS_GPB_MFPH_PB8MFP_Pos)

#define SYS_GPB_MFPH_PB9MFP_Pos          (4)

#define SYS_GPB_MFPH_PB9MFP_Msk          (0xful << SYS_GPB_MFPH_PB9MFP_Pos)

#define SYS_GPB_MFPH_PB10MFP_Pos         (8)

#define SYS_GPB_MFPH_PB10MFP_Msk         (0xful << SYS_GPB_MFPH_PB10MFP_Pos)

#define SYS_GPB_MFPH_PB11MFP_Pos         (12)

#define SYS_GPB_MFPH_PB11MFP_Msk         (0xful << SYS_GPB_MFPH_PB11MFP_Pos)

#define SYS_GPB_MFPH_PB12MFP_Pos         (16)

#define SYS_GPB_MFPH_PB12MFP_Msk         (0xful << SYS_GPB_MFPH_PB12MFP_Pos)

#define SYS_GPB_MFPH_PB13MFP_Pos         (20)

#define SYS_GPB_MFPH_PB13MFP_Msk         (0xful << SYS_GPB_MFPH_PB13MFP_Pos)

#define SYS_GPB_MFPH_PB14MFP_Pos         (24)

#define SYS_GPB_MFPH_PB14MFP_Msk         (0xful << SYS_GPB_MFPH_PB14MFP_Pos)

#define SYS_GPB_MFPH_PB15MFP_Pos         (28)

#define SYS_GPB_MFPH_PB15MFP_Msk         (0xful << SYS_GPB_MFPH_PB15MFP_Pos)

#define SYS_GPC_MFPL_PC0MFP_Pos          (0)

#define SYS_GPC_MFPL_PC0MFP_Msk          (0xful << SYS_GPC_MFPL_PC0MFP_Pos)

#define SYS_GPC_MFPL_PC1MFP_Pos          (4)

#define SYS_GPC_MFPL_PC1MFP_Msk          (0xful << SYS_GPC_MFPL_PC1MFP_Pos)

#define SYS_GPC_MFPL_PC2MFP_Pos          (8)

#define SYS_GPC_MFPL_PC2MFP_Msk          (0xful << SYS_GPC_MFPL_PC2MFP_Pos)

#define SYS_GPC_MFPL_PC3MFP_Pos          (12)

#define SYS_GPC_MFPL_PC3MFP_Msk          (0xful << SYS_GPC_MFPL_PC3MFP_Pos)

#define SYS_GPC_MFPL_PC4MFP_Pos          (16)

#define SYS_GPC_MFPL_PC4MFP_Msk          (0xful << SYS_GPC_MFPL_PC4MFP_Pos)

#define SYS_GPC_MFPL_PC5MFP_Pos          (20)

#define SYS_GPC_MFPL_PC5MFP_Msk          (0xful << SYS_GPC_MFPL_PC5MFP_Pos)

#define SYS_GPC_MFPL_PC6MFP_Pos          (24)

#define SYS_GPC_MFPL_PC6MFP_Msk          (0xful << SYS_GPC_MFPL_PC6MFP_Pos)

#define SYS_GPC_MFPL_PC7MFP_Pos          (28)

#define SYS_GPC_MFPL_PC7MFP_Msk          (0xful << SYS_GPC_MFPL_PC7MFP_Pos)

#define SYS_GPC_MFPH_PC8MFP_Pos          (0)

#define SYS_GPC_MFPH_PC8MFP_Msk          (0xful << SYS_GPC_MFPH_PC8MFP_Pos)

#define SYS_GPC_MFPH_PC9MFP_Pos          (4)

#define SYS_GPC_MFPH_PC9MFP_Msk          (0xful << SYS_GPC_MFPH_PC9MFP_Pos)

#define SYS_GPC_MFPH_PC10MFP_Pos         (8)

#define SYS_GPC_MFPH_PC10MFP_Msk         (0xful << SYS_GPC_MFPH_PC10MFP_Pos)

#define SYS_GPC_MFPH_PC11MFP_Pos         (12)

#define SYS_GPC_MFPH_PC11MFP_Msk         (0xful << SYS_GPC_MFPH_PC11MFP_Pos)

#define SYS_GPC_MFPH_PC12MFP_Pos         (16)

#define SYS_GPC_MFPH_PC12MFP_Msk         (0xful << SYS_GPC_MFPH_PC12MFP_Pos)

#define SYS_GPC_MFPH_PC13MFP_Pos         (20)

#define SYS_GPC_MFPH_PC13MFP_Msk         (0xful << SYS_GPC_MFPH_PC13MFP_Pos)

#define SYS_GPC_MFPH_PC14MFP_Pos         (24)

#define SYS_GPC_MFPH_PC14MFP_Msk         (0xful << SYS_GPC_MFPH_PC14MFP_Pos)

#define SYS_GPC_MFPH_PC15MFP_Pos         (28)

#define SYS_GPC_MFPH_PC15MFP_Msk         (0xful << SYS_GPC_MFPH_PC15MFP_Pos)

#define SYS_GPD_MFPL_PD0MFP_Pos          (0)

#define SYS_GPD_MFPL_PD0MFP_Msk          (0xful << SYS_GPD_MFPL_PD0MFP_Pos)

#define SYS_GPD_MFPL_PD1MFP_Pos          (4)

#define SYS_GPD_MFPL_PD1MFP_Msk          (0xful << SYS_GPD_MFPL_PD1MFP_Pos)

#define SYS_GPD_MFPL_PD2MFP_Pos          (8)

#define SYS_GPD_MFPL_PD2MFP_Msk          (0xful << SYS_GPD_MFPL_PD2MFP_Pos)

#define SYS_GPD_MFPL_PD3MFP_Pos          (12)

#define SYS_GPD_MFPL_PD3MFP_Msk          (0xful << SYS_GPD_MFPL_PD3MFP_Pos)

#define SYS_GPD_MFPL_PD4MFP_Pos          (16)

#define SYS_GPD_MFPL_PD4MFP_Msk          (0xful << SYS_GPD_MFPL_PD4MFP_Pos)

#define SYS_GPD_MFPL_PD5MFP_Pos          (20)

#define SYS_GPD_MFPL_PD5MFP_Msk          (0xful << SYS_GPD_MFPL_PD5MFP_Pos)

#define SYS_GPD_MFPL_PD6MFP_Pos          (24)

#define SYS_GPD_MFPL_PD6MFP_Msk          (0xful << SYS_GPD_MFPL_PD6MFP_Pos)

#define SYS_GPD_MFPL_PD7MFP_Pos          (28)

#define SYS_GPD_MFPL_PD7MFP_Msk          (0xful << SYS_GPD_MFPL_PD7MFP_Pos)

#define SYS_GPD_MFPH_PD8MFP_Pos          (0)

#define SYS_GPD_MFPH_PD8MFP_Msk          (0xful << SYS_GPD_MFPH_PD8MFP_Pos)

#define SYS_GPD_MFPH_PD9MFP_Pos          (4)

#define SYS_GPD_MFPH_PD9MFP_Msk          (0xful << SYS_GPD_MFPH_PD9MFP_Pos)

#define SYS_GPD_MFPH_PD10MFP_Pos         (8)

#define SYS_GPD_MFPH_PD10MFP_Msk         (0xful << SYS_GPD_MFPH_PD10MFP_Pos)

#define SYS_GPD_MFPH_PD11MFP_Pos         (12)

#define SYS_GPD_MFPH_PD11MFP_Msk         (0xful << SYS_GPD_MFPH_PD11MFP_Pos)

#define SYS_GPD_MFPH_PD12MFP_Pos         (16)

#define SYS_GPD_MFPH_PD12MFP_Msk         (0xful << SYS_GPD_MFPH_PD12MFP_Pos)

#define SYS_GPD_MFPH_PD13MFP_Pos         (20)

#define SYS_GPD_MFPH_PD13MFP_Msk         (0xful << SYS_GPD_MFPH_PD13MFP_Pos)

#define SYS_GPD_MFPH_PD14MFP_Pos         (24)

#define SYS_GPD_MFPH_PD14MFP_Msk         (0xful << SYS_GPD_MFPH_PD14MFP_Pos)

#define SYS_GPD_MFPH_PD15MFP_Pos         (28)

#define SYS_GPD_MFPH_PD15MFP_Msk         (0xful << SYS_GPD_MFPH_PD15MFP_Pos)

#define SYS_GPE_MFPL_PE0MFP_Pos          (0)

#define SYS_GPE_MFPL_PE0MFP_Msk          (0xful << SYS_GPE_MFPL_PE0MFP_Pos)

#define SYS_GPE_MFPL_PE1MFP_Pos          (4)

#define SYS_GPE_MFPL_PE1MFP_Msk          (0xful << SYS_GPE_MFPL_PE1MFP_Pos)

#define SYS_GPE_MFPL_PE2MFP_Pos          (8)

#define SYS_GPE_MFPL_PE2MFP_Msk          (0xful << SYS_GPE_MFPL_PE2MFP_Pos)

#define SYS_GPE_MFPL_PE3MFP_Pos          (12)

#define SYS_GPE_MFPL_PE3MFP_Msk          (0xful << SYS_GPE_MFPL_PE3MFP_Pos)

#define SYS_GPE_MFPL_PE4MFP_Pos          (16)

#define SYS_GPE_MFPL_PE4MFP_Msk          (0xful << SYS_GPE_MFPL_PE4MFP_Pos)

#define SYS_GPE_MFPL_PE5MFP_Pos          (20)

#define SYS_GPE_MFPL_PE5MFP_Msk          (0xful << SYS_GPE_MFPL_PE5MFP_Pos)

#define SYS_GPE_MFPL_PE6MFP_Pos          (24)

#define SYS_GPE_MFPL_PE6MFP_Msk          (0xful << SYS_GPE_MFPL_PE6MFP_Pos)

#define SYS_GPE_MFPL_PE7MFP_Pos          (28)

#define SYS_GPE_MFPL_PE7MFP_Msk          (0xful << SYS_GPE_MFPL_PE7MFP_Pos)

#define SYS_GPE_MFPH_PE8MFP_Pos          (0)

#define SYS_GPE_MFPH_PE8MFP_Msk          (0xful << SYS_GPE_MFPH_PE8MFP_Pos)

#define SYS_GPE_MFPH_PE9MFP_Pos          (4)

#define SYS_GPE_MFPH_PE9MFP_Msk          (0xful << SYS_GPE_MFPH_PE9MFP_Pos)

#define SYS_GPE_MFPH_PE10MFP_Pos         (8)

#define SYS_GPE_MFPH_PE10MFP_Msk         (0xful << SYS_GPE_MFPH_PE10MFP_Pos)

#define SYS_GPE_MFPH_PE11MFP_Pos         (12)

#define SYS_GPE_MFPH_PE11MFP_Msk         (0xful << SYS_GPE_MFPH_PE11MFP_Pos)

#define SYS_GPE_MFPH_PE12MFP_Pos         (16)

#define SYS_GPE_MFPH_PE12MFP_Msk         (0xful << SYS_GPE_MFPH_PE12MFP_Pos)

#define SYS_GPE_MFPH_PE13MFP_Pos         (20)

#define SYS_GPE_MFPH_PE13MFP_Msk         (0xful << SYS_GPE_MFPH_PE13MFP_Pos)

#define SYS_GPE_MFPH_PE14MFP_Pos         (24)

#define SYS_GPE_MFPH_PE14MFP_Msk         (0xful << SYS_GPE_MFPH_PE14MFP_Pos)

#define SYS_GPF_MFPL_PF0MFP_Pos          (0)

#define SYS_GPF_MFPL_PF0MFP_Msk          (0xful << SYS_GPF_MFPL_PF0MFP_Pos)

#define SYS_GPF_MFPL_PF1MFP_Pos          (4)

#define SYS_GPF_MFPL_PF1MFP_Msk          (0xful << SYS_GPF_MFPL_PF1MFP_Pos)

#define SYS_GPF_MFPL_PF2MFP_Pos          (8)

#define SYS_GPF_MFPL_PF2MFP_Msk          (0xful << SYS_GPF_MFPL_PF2MFP_Pos)

#define SYS_GPF_MFPL_PF3MFP_Pos          (12)

#define SYS_GPF_MFPL_PF3MFP_Msk          (0xful << SYS_GPF_MFPL_PF3MFP_Pos)

#define SYS_GPF_MFPL_PF4MFP_Pos          (16)

#define SYS_GPF_MFPL_PF4MFP_Msk          (0xful << SYS_GPF_MFPL_PF4MFP_Pos)

#define SYS_GPF_MFPL_PF5MFP_Pos          (20)

#define SYS_GPF_MFPL_PF5MFP_Msk          (0xful << SYS_GPF_MFPL_PF5MFP_Pos)

#define SYS_GPF_MFPL_PF6MFP_Pos          (24)

#define SYS_GPF_MFPL_PF6MFP_Msk          (0xful << SYS_GPF_MFPL_PF6MFP_Pos)

#define SYS_GPF_MFPL_PF7MFP_Pos          (28)

#define SYS_GPF_MFPL_PF7MFP_Msk          (0xful << SYS_GPF_MFPL_PF7MFP_Pos)

#define SYS_SRAM_BISTCTL_SRBIST0_Pos     (0)

#define SYS_SRAM_BISTCTL_SRBIST0_Msk     (0x1ul << SYS_SRAM_BISTCTL_SRBIST0_Pos)

#define SYS_SRAM_BISTCTL_SRBIST1_Pos     (1)

#define SYS_SRAM_BISTCTL_SRBIST1_Msk     (0x1ul << SYS_SRAM_BISTCTL_SRBIST1_Pos)

#define SYS_SRAM_BISTCTL_CRBIST_Pos      (2)

#define SYS_SRAM_BISTCTL_CRBIST_Msk      (0x1ul << SYS_SRAM_BISTCTL_CRBIST_Pos)

#define SYS_SRAM_BISTCTL_USBBIST_Pos     (4)

#define SYS_SRAM_BISTCTL_USBBIST_Msk     (0x1ul << SYS_SRAM_BISTCTL_USBBIST_Pos)

#define SYS_SRAM_BISTSTS_SRBISTEF0_Pos   (0)

#define SYS_SRAM_BISTSTS_SRBISTEF0_Msk   (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF0_Pos)

#define SYS_SRAM_BISTSTS_SRBISTEF1_Pos   (1)

#define SYS_SRAM_BISTSTS_SRBISTEF1_Msk   (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF1_Pos)

#define SYS_SRAM_BISTSTS_CRBISTEF_Pos    (2)

#define SYS_SRAM_BISTSTS_CRBISTEF_Msk    (0x1ul << SYS_SRAM_BISTSTS_CRBISTEF_Pos)

#define SYS_SRAM_BISTSTS_USBBEF_Pos      (4)

#define SYS_SRAM_BISTSTS_USBBEF_Msk      (0x1ul << SYS_SRAM_BISTSTS_USBBEF_Pos)

#define SYS_SRAM_BISTSTS_SRBEND0_Pos     (16)

#define SYS_SRAM_BISTSTS_SRBEND0_Msk     (0x1ul << SYS_SRAM_BISTSTS_SRBEND0_Pos)

#define SYS_SRAM_BISTSTS_SRBEND1_Pos     (17)

#define SYS_SRAM_BISTSTS_SRBEND1_Msk     (0x1ul << SYS_SRAM_BISTSTS_SRBEND1_Pos)

#define SYS_SRAM_BISTSTS_CRBEND_Pos      (18)

#define SYS_SRAM_BISTSTS_CRBEND_Msk      (0x1ul << SYS_SRAM_BISTSTS_CRBEND_Pos)

#define SYS_SRAM_BISTSTS_USBBEND_Pos     (20)

#define SYS_SRAM_BISTSTS_USBBEND_Msk     (0x1ul << SYS_SRAM_BISTSTS_USBBEND_Pos)

#define SYS_IRCTCTL_FREQSEL_Pos          (0)

#define SYS_IRCTCTL_FREQSEL_Msk          (0x3ul << SYS_IRCTCTL_FREQSEL_Pos)

#define SYS_IRCTCTL_LOOPSEL_Pos          (4)

#define SYS_IRCTCTL_LOOPSEL_Msk          (0x3ul << SYS_IRCTCTL_LOOPSEL_Pos)

#define SYS_IRCTCTL_RETRYCNT_Pos         (6)

#define SYS_IRCTCTL_RETRYCNT_Msk         (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos)

#define SYS_IRCTCTL_CESTOPEN_Pos         (8)

#define SYS_IRCTCTL_CESTOPEN_Msk         (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos)

#define SYS_IRCTIEN_TFAILIEN_Pos         (1)

#define SYS_IRCTIEN_TFAILIEN_Msk         (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos)

#define SYS_IRCTIEN_CLKEIEN_Pos          (2)

#define SYS_IRCTIEN_CLKEIEN_Msk          (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos)

#define SYS_IRCTISTS_FREQLOCK_Pos        (0)

#define SYS_IRCTISTS_FREQLOCK_Msk        (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos)

#define SYS_IRCTISTS_TFAILIF_Pos         (1)

#define SYS_IRCTISTS_TFAILIF_Msk         (0x1ul << SYS_IRCTISTS_TFAILIF_Pos)

#define SYS_IRCTISTS_CLKERRIF_Pos        (2)

#define SYS_IRCTISTS_CLKERRIF_Msk        (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos)

#define SYS_REGLCTL_REGLCTL_Pos          (0)

#define SYS_REGLCTL_REGLCTL_Msk          (0xfful << SYS_REGLCTL_REGLCTL_Pos)

#define SYS_IRC48MTCTL_FREQSEL_Pos       (0)

#define SYS_IRC48MTCTL_FREQSEL_Msk       (0x3ul << SYS_IRC48MTCTL_FREQSEL_Pos)

#define SYS_IRC48MTCTL_LOOPSEL_Pos       (4)

#define SYS_IRC48MTCTL_LOOPSEL_Msk       (0x3ul << SYS_IRC48MTCTL_LOOPSEL_Pos)

#define SYS_IRC48MTCTL_RETRYCNT_Pos      (6)

#define SYS_IRC48MTCTL_RETRYCNT_Msk      (0x3ul << SYS_IRC48MTCTL_RETRYCNT_Pos)

#define SYS_IRC48MTCTL_CESTOPEN_Pos      (8)

#define SYS_IRC48MTCTL_CESTOPEN_Msk      (0x1ul << SYS_IRC48MTCTL_CESTOPEN_Pos)

#define SYS_IRC48MTCTL_REFCKSEL_Pos      (10)

#define SYS_IRC48MTCTL_REFCKSEL_Msk      (0x1ul << SYS_IRC48MTCTL_REFCKSEL_Pos)

#define SYS_IRC48MTIEN_TFAILIEN_Pos      (1)

#define SYS_IRC48MTIEN_TFAILIEN_Msk      (0x1ul << SYS_IRC48MTIEN_TFAILIEN_Pos)

#define SYS_IRC48MTIEN_CLKEIEN_Pos       (2)

#define SYS_IRC48MTIEN_CLKEIEN_Msk       (0x1ul << SYS_IRC48MTIEN_CLKEIEN_Pos)

#define SYS_IRC48MTISTS_FREQLOCK_Pos     (0)

#define SYS_IRC48MTISTS_FREQLOCK_Msk     (0x1ul << SYS_IRC48MTISTS_FREQLOCK_Pos)

#define SYS_IRC48MTISTS_TFAILIF_Pos      (1)

#define SYS_IRC48MTISTS_TFAILIF_Msk      (0x1ul << SYS_IRC48MTISTS_TFAILIF_Pos)

#define SYS_IRC48MTISTS_CLKERRIF_Pos     (2)

#define SYS_IRC48MTISTS_CLKERRIF_Msk     (0x1ul << SYS_IRC48MTISTS_CLKERRIF_Pos)            /* SYS_CONST */


typedef struct

{


    __IO  uint32_t NMIEN;          /* Offset: 0x00  NMI Source Interrupt Enable Register                               */

    __I   uint32_t NMISTS;         /* Offset: 0x04  NMI source interrupt Status Register                               */


} SYS_INT_T;


#define SYS_NMIEN_BODOUT_Pos             (0)

#define SYS_NMIEN_BODOUT_Msk             (0x1ul << SYS_NMIEN_BODOUT_Pos )

#define SYS_NMIEN_IRC_INT_Pos            (1)

#define SYS_NMIEN_IRC_INT_Msk            (0x1ul << SYS_NMIEN_IRC_INT_Pos )

#define SYS_NMIEN_PWRWU_INT_Pos          (2)

#define SYS_NMIEN_PWRWU_INT_Msk          (0x1ul << SYS_NMIEN_PWRWU_INT_Pos )

#define SYS_NMIEN_CLKFAIL_Pos            (4)

#define SYS_NMIEN_CLKFAIL_Msk            (0x1ul << SYS_NMIEN_CLKFAIL_Pos )

#define SYS_NMIEN_RTC_INT_Pos            (6)

#define SYS_NMIEN_RTC_INT_Msk            (0x1ul << SYS_NMIEN_RTC_INT_Pos )

#define SYS_NMIEN_TAMPER_INT_Pos         (7)

#define SYS_NMIEN_TAMPER_INT_Msk         (0x1ul << SYS_NMIEN_TAMPER_INT_Pos )

#define SYS_NMIEN_EINT0_Pos              (8)

#define SYS_NMIEN_EINT0_Msk              (0x1ul << SYS_NMIEN_EINT0_Pos )

#define SYS_NMIEN_EINT1_Pos              (9)

#define SYS_NMIEN_EINT1_Msk              (0x1ul << SYS_NMIEN_EINT1_Pos )

#define SYS_NMIEN_EINT2_Pos              (10)

#define SYS_NMIEN_EINT2_Msk              (0x1ul << SYS_NMIEN_EINT2_Pos )

#define SYS_NMIEN_EINT3_Pos              (11)

#define SYS_NMIEN_EINT3_Msk              (0x1ul << SYS_NMIEN_EINT3_Pos )

#define SYS_NMIEN_EINT4_Pos              (12)

#define SYS_NMIEN_EINT4_Msk              (0x1ul << SYS_NMIEN_EINT4_Pos )

#define SYS_NMIEN_EINT5_Pos              (13)

#define SYS_NMIEN_EINT5_Msk              (0x1ul << SYS_NMIEN_EINT5_Pos )

#define SYS_NMIEN_UART0_INT_Pos          (14)

#define SYS_NMIEN_UART0_INT_Msk          (0x1ul << SYS_NMIEN_UART0_INT_Pos )

#define SYS_NMIEN_UART1_INT_Pos          (15)

#define SYS_NMIEN_UART1_INT_Msk          (0x1ul << SYS_NMIEN_UART1_INT_Pos )

#define SYS_NMISTS_BODOUT_Pos            (0)

#define SYS_NMISTS_BODOUT_Msk            (0x1ul << SYS_NMISTS_BODOUT_Pos )

#define SYS_NMISTS_IRC_INT_Pos           (1)

#define SYS_NMISTS_IRC_INT_Msk           (0x1ul << SYS_NMISTS_IRC_INT_Pos )

#define SYS_NMISTS_PWRWU_INT_Pos         (2)

#define SYS_NMISTS_PWRWU_INT_Msk         (0x1ul << SYS_NMISTS_PWRWU_INT_Pos )

#define SYS_NMISTS_CLKFAIL_Pos           (4)

#define SYS_NMISTS_CLKFAIL_Msk           (0x1ul << SYS_NMISTS_CLKFAIL_Pos )

#define SYS_NMISTS_RTC_INT_Pos           (6)

#define SYS_NMISTS_RTC_INT_Msk           (0x1ul << SYS_NMISTS_RTC_INT_Pos )

#define SYS_NMISTS_TAMPER_INT_Pos        (7)

#define SYS_NMISTS_TAMPER_INT_Msk        (0x1ul << SYS_NMISTS_TAMPER_INT_Pos )

#define SYS_NMISTS_EINT0_Pos             (8)

#define SYS_NMISTS_EINT0_Msk             (0x1ul << SYS_NMISTS_EINT0_Pos )

#define SYS_NMISTS_EINT1_Pos             (9)

#define SYS_NMISTS_EINT1_Msk             (0x1ul << SYS_NMISTS_EINT1_Pos )

#define SYS_NMISTS_EINT2_Pos             (10)

#define SYS_NMISTS_EINT2_Msk             (0x1ul << SYS_NMISTS_EINT2_Pos )

#define SYS_NMISTS_EINT3_Pos             (11)

#define SYS_NMISTS_EINT3_Msk             (0x1ul << SYS_NMISTS_EINT3_Pos )

#define SYS_NMISTS_EINT4_Pos             (12)

#define SYS_NMISTS_EINT4_Msk             (0x1ul << SYS_NMISTS_EINT4_Pos )

#define SYS_NMISTS_EINT5_Pos             (13)

#define SYS_NMISTS_EINT5_Msk             (0x1ul << SYS_NMISTS_EINT5_Pos )

#define SYS_NMISTS_UART0_INT_Pos         (14)

#define SYS_NMISTS_UART0_INT_Msk         (0x1ul << SYS_NMISTS_UART0_INT_Pos )

#define SYS_NMISTS_UART1_INT_Pos         (15)

#define SYS_NMISTS_UART1_INT_Msk         (0x1ul << SYS_NMISTS_UART1_INT_Pos )               /* INT_CONST */ /* end of SYS register group */


/*---------------------- Timer Controller -------------------------*/

typedef struct

{


    __IO uint32_t CTL;           /* Offset: 0x00  Timer Control and Status Register                                  */

    __IO uint32_t CMP;           /* Offset: 0x04  Timer Compare Register                                             */

    __IO uint32_t INTSTS;        /* Offset: 0x08  Timer Interrupt Status Register                                    */

    __I  uint32_t CNT;           /* Offset: 0x0C  Timer Data Register                                                */

    __I  uint32_t CAP;           /* Offset: 0x10  Timer Capture Data Register                                        */

    __IO uint32_t EXTCTL;        /* Offset: 0x14  Timer External Control Register                                    */

    __IO uint32_t EINTSTS;       /* Offset: 0x18  Timer External Interrupt Status Register                           */


} TIMER_T;


#define TIMER_CTL_PSC_Pos                  (0)

#define TIMER_CTL_PSC_Msk                  (0xfful << TIMER_CTL_PSC_Pos)

#define TIMER_CTL_WKTKEN_Pos               (17)

#define TIMER_CTL_WKTKEN_Msk               (0x1ul << TIMER_CTL_WKTKEN_Pos)

#define TIMER_CTL_TRGSSEL_Pos              (18)

#define TIMER_CTL_TRGSSEL_Msk              (0x1ul << TIMER_CTL_TRGSSEL_Pos)

#define TIMER_CTL_TRGPWM_Pos               (19)

#define TIMER_CTL_TRGPWM_Msk               (0x1ul << TIMER_CTL_TRGPWM_Pos)

#define TIMER_CTL_TRGEADC_Pos              (21)

#define TIMER_CTL_TRGEADC_Msk              (0x1ul << TIMER_CTL_TRGEADC_Pos)

#define TIMER_CTL_TGLPINSEL_Pos            (22)

#define TIMER_CTL_TGLPINSEL_Msk            (0x1ul << TIMER_CTL_TGLPINSEL_Pos)

#define TIMER_CTL_WKEN_Pos                 (23)

#define TIMER_CTL_WKEN_Msk                 (0x1ul << TIMER_CTL_WKEN_Pos)

#define TIMER_CTL_EXTCNTEN_Pos             (24)

#define TIMER_CTL_EXTCNTEN_Msk             (0x1ul << TIMER_CTL_EXTCNTEN_Pos)

#define TIMER_CTL_ACTSTS_Pos               (25)

#define TIMER_CTL_ACTSTS_Msk               (0x1ul << TIMER_CTL_ACTSTS_Pos)

#define TIMER_CTL_RSTCNT_Pos               (26)

#define TIMER_CTL_RSTCNT_Msk               (0x1ul << TIMER_CTL_RSTCNT_Pos)

#define TIMER_CTL_OPMODE_Pos               (27)

#define TIMER_CTL_OPMODE_Msk               (0x3ul << TIMER_CTL_OPMODE_Pos)

#define TIMER_CTL_INTEN_Pos                (29)

#define TIMER_CTL_INTEN_Msk                (0x1ul << TIMER_CTL_INTEN_Pos)

#define TIMER_CTL_CNTEN_Pos                (30)

#define TIMER_CTL_CNTEN_Msk                (0x1ul << TIMER_CTL_CNTEN_Pos)

#define TIMER_CTL_ICEDEBUG_Pos             (31)

#define TIMER_CTL_ICEDEBUG_Msk             (0x1ul << TIMER_CTL_ICEDEBUG_Pos)

#define TIMER_CMP_CMPDAT_Pos               (0)

#define TIMER_CMP_CMPDAT_Msk               (0xfffffful << TIMER_CMP_CMPDAT_Pos)

#define TIMER_INTSTS_TIF_Pos               (0)

#define TIMER_INTSTS_TIF_Msk               (0x1ul << TIMER_INTSTS_TIF_Pos)

#define TIMER_INTSTS_TWKF_Pos              (1)

#define TIMER_INTSTS_TWKF_Msk              (0x1ul << TIMER_INTSTS_TWKF_Pos)

#define TIMER_CNT_CNT_Pos                  (0)

#define TIMER_CNT_CNT_Msk                  (0xfffffful << TIMER_CNT_CNT_Pos)

#define TIMER_CAP_CAPDAT_Pos               (0)

#define TIMER_CAP_CAPDAT_Msk               (0xfffffful << TIMER_CAP_CAPDAT_Pos)

#define TIMER_EXTCTL_CNTPHASE_Pos          (0)

#define TIMER_EXTCTL_CNTPHASE_Msk          (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos)

#define TIMER_EXTCTL_CAPEDGE_Pos           (1)

#define TIMER_EXTCTL_CAPEDGE_Msk           (0x3ul << TIMER_EXTCTL_CAPEDGE_Pos)

#define TIMER_EXTCTL_CAPEN_Pos             (3)

#define TIMER_EXTCTL_CAPEN_Msk             (0x1ul << TIMER_EXTCTL_CAPEN_Pos)

#define TIMER_EXTCTL_CAPFUNCS_Pos          (4)

#define TIMER_EXTCTL_CAPFUNCS_Msk          (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos)

#define TIMER_EXTCTL_CAPIEN_Pos            (5)

#define TIMER_EXTCTL_CAPIEN_Msk            (0x1ul << TIMER_EXTCTL_CAPIEN_Pos)

#define TIMER_EXTCTL_CAPDBEN_Pos           (6)

#define TIMER_EXTCTL_CAPDBEN_Msk           (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos)

#define TIMER_EXTCTL_CNTDBEN_Pos           (7)

#define TIMER_EXTCTL_CNTDBEN_Msk           (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos)

#define TIMER_EINTSTS_CAPIF_Pos            (0)

#define TIMER_EINTSTS_CAPIF_Msk            (0x1ul << TIMER_EINTSTS_CAPIF_Pos)               /* TIMER_CONST */ /* end of TIMER register group */


/*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/

typedef struct

{


    __IO uint32_t DAT;           /* Offset: 0x00  UART Receive/Transmit Buffer Register                              */

    __IO uint32_t INTEN;         /* Offset: 0x04  UART Interrupt Enable Register                                     */

    __IO uint32_t FIFO;          /* Offset: 0x08  UART FIFO Control Register                                         */

    __IO uint32_t LINE;          /* Offset: 0x0C  UART Line Control Register                                         */

    __IO uint32_t MODEM;         /* Offset: 0x10  UART Modem Control Register                                        */

    __IO uint32_t MODEMSTS;      /* Offset: 0x14  UART Modem Status Register                                         */

    __IO uint32_t FIFOSTS;       /* Offset: 0x18  UART FIFO Status Register                                          */

    __IO uint32_t INTSTS;        /* Offset: 0x1C  UART Interrupt Status Register                                     */

    __IO uint32_t TOUT;          /* Offset: 0x20  UART Time-out Register                                             */

    __IO uint32_t BAUD;          /* Offset: 0x24  UART Baud Rate Divisor Register                                    */

    __IO uint32_t IRDA;          /* Offset: 0x28  UART IrDA Control Register                                         */

    __IO uint32_t ALTCTL;        /* Offset: 0x2C  UART Alternate Control/Status Register                             */

    __IO uint32_t FUNCSEL;       /* Offset: 0x30  UART Function Select Register                                      */

} UART_T;


#define UART_DAT_DAT_Pos                 (0)

#define UART_DAT_DAT_Msk                 (0xfful << UART_DAT_DAT_Pos)

#define UART_INTEN_RDAIEN_Pos            (0)

#define UART_INTEN_RDAIEN_Msk            (0x1ul << UART_INTEN_RDAIEN_Pos)

#define UART_INTEN_THREIEN_Pos           (1)

#define UART_INTEN_THREIEN_Msk           (0x1ul << UART_INTEN_THREIEN_Pos)

#define UART_INTEN_RLSIEN_Pos            (2)

#define UART_INTEN_RLSIEN_Msk            (0x1ul << UART_INTEN_RLSIEN_Pos)

#define UART_INTEN_MODEMIEN_Pos          (3)

#define UART_INTEN_MODEMIEN_Msk          (0x1ul << UART_INTEN_MODEMIEN_Pos)

#define UART_INTEN_RXTOIEN_Pos           (4)

#define UART_INTEN_RXTOIEN_Msk           (0x1ul << UART_INTEN_RXTOIEN_Pos)

#define UART_INTEN_BUFERRIEN_Pos         (5)

#define UART_INTEN_BUFERRIEN_Msk         (0x1ul << UART_INTEN_BUFERRIEN_Pos)

#define UART_INTEN_LINIEN_Pos            (8)

#define UART_INTEN_LINIEN_Msk            (0x1ul << UART_INTEN_LINIEN_Pos)

#define UART_INTEN_WKCTSIEN_Pos          (9)

#define UART_INTEN_WKCTSIEN_Msk          (0x1ul << UART_INTEN_WKCTSIEN_Pos)

#define UART_INTEN_WKDATIEN_Pos          (10)

#define UART_INTEN_WKDATIEN_Msk          (0x1ul << UART_INTEN_WKDATIEN_Pos)

#define UART_INTEN_TOCNTEN_Pos           (11)

#define UART_INTEN_TOCNTEN_Msk           (0x1ul << UART_INTEN_TOCNTEN_Pos)

#define UART_INTEN_ATORTSEN_Pos          (12)

#define UART_INTEN_ATORTSEN_Msk          (0x1ul << UART_INTEN_ATORTSEN_Pos)

#define UART_INTEN_ATOCTSEN_Pos          (13)

#define UART_INTEN_ATOCTSEN_Msk          (0x1ul << UART_INTEN_ATOCTSEN_Pos)

#define UART_INTEN_TXPDMAEN_Pos          (14)

#define UART_INTEN_TXPDMAEN_Msk          (0x1ul << UART_INTEN_TXPDMAEN_Pos)

#define UART_INTEN_RXPDMAEN_Pos          (15)

#define UART_INTEN_RXPDMAEN_Msk          (0x1ul << UART_INTEN_RXPDMAEN_Pos)

#define UART_INTEN_ABRIEN_Pos            (18)

#define UART_INTEN_ABRIEN_Msk            (0x1ul << UART_INTEN_ABRIEN_Pos)

#define UART_FIFO_RXRST_Pos              (1)

#define UART_FIFO_RXRST_Msk              (0x1ul << UART_FIFO_RXRST_Pos)

#define UART_FIFO_TXRST_Pos              (2)

#define UART_FIFO_TXRST_Msk              (0x1ul << UART_FIFO_TXRST_Pos)

#define UART_FIFO_RFITL_Pos              (4)

#define UART_FIFO_RFITL_Msk              (0xful << UART_FIFO_RFITL_Pos)

#define UART_FIFO_RXOFF_Pos              (8)

#define UART_FIFO_RXOFF_Msk              (0x1ul << UART_FIFO_RXOFF_Pos)

#define UART_FIFO_RTSTRGLV_Pos           (16)

#define UART_FIFO_RTSTRGLV_Msk           (0xful << UART_FIFO_RTSTRGLV_Pos)

#define UART_LINE_WLS_Pos                (0)

#define UART_LINE_WLS_Msk                (0x3ul << UART_LINE_WLS_Pos)

#define UART_LINE_NSB_Pos                (2)

#define UART_LINE_NSB_Msk                (0x1ul << UART_LINE_NSB_Pos)

#define UART_LINE_PBE_Pos                (3)

#define UART_LINE_PBE_Msk                (0x1ul << UART_LINE_PBE_Pos)

#define UART_LINE_EPE_Pos                (4)

#define UART_LINE_EPE_Msk                (0x1ul << UART_LINE_EPE_Pos)

#define UART_LINE_SPE_Pos                (5)

#define UART_LINE_SPE_Msk                (0x1ul << UART_LINE_SPE_Pos)

#define UART_LINE_BCB_Pos                (6)

#define UART_LINE_BCB_Msk                (0x1ul << UART_LINE_BCB_Pos)

#define UART_MODEM_RTS_Pos               (1)

#define UART_MODEM_RTS_Msk               (0x1ul << UART_MODEM_RTS_Pos)

#define UART_MODEM_RTSACTLV_Pos          (9)

#define UART_MODEM_RTSACTLV_Msk          (0x1ul << UART_MODEM_RTSACTLV_Pos)

#define UART_MODEM_RTSSTS_Pos            (13)

#define UART_MODEM_RTSSTS_Msk            (0x1ul << UART_MODEM_RTSSTS_Pos)

#define UART_MODEMSTS_CTSDETF_Pos        (0)

#define UART_MODEMSTS_CTSDETF_Msk        (0x1ul << UART_MODEMSTS_CTSDETF_Pos)

#define UART_MODEMSTS_CTSSTS_Pos         (4)

#define UART_MODEMSTS_CTSSTS_Msk         (0x1ul << UART_MODEMSTS_CTSSTS_Pos)

#define UART_MODEMSTS_CTSACTLV_Pos       (8)

#define UART_MODEMSTS_CTSACTLV_Msk       (0x1ul << UART_MODEMSTS_CTSACTLV_Pos)

#define UART_FIFOSTS_RXOVIF_Pos          (0)

#define UART_FIFOSTS_RXOVIF_Msk          (0x1ul << UART_FIFOSTS_RXOVIF_Pos)

#define UART_FIFOSTS_ABRDIF_Pos          (1)

#define UART_FIFOSTS_ABRDIF_Msk          (0x1ul << UART_FIFOSTS_ABRDIF_Pos)

#define UART_FIFOSTS_ABRDTOIF_Pos        (2)

#define UART_FIFOSTS_ABRDTOIF_Msk        (0x1ul << UART_FIFOSTS_ABRDTOIF_Pos)

#define UART_FIFOSTS_ADDRDETF_Pos        (3)

#define UART_FIFOSTS_ADDRDETF_Msk        (0x1ul << UART_FIFOSTS_ADDRDETF_Pos)

#define UART_FIFOSTS_PEF_Pos             (4)

#define UART_FIFOSTS_PEF_Msk             (0x1ul << UART_FIFOSTS_PEF_Pos)

#define UART_FIFOSTS_FEF_Pos             (5)

#define UART_FIFOSTS_FEF_Msk             (0x1ul << UART_FIFOSTS_FEF_Pos)

#define UART_FIFOSTS_BIF_Pos             (6)

#define UART_FIFOSTS_BIF_Msk             (0x1ul << UART_FIFOSTS_BIF_Pos)

#define UART_FIFOSTS_RXPTR_Pos           (8)

#define UART_FIFOSTS_RXPTR_Msk           (0x3ful << UART_FIFOSTS_RXPTR_Pos)

#define UART_FIFOSTS_RXEMPTY_Pos         (14)

#define UART_FIFOSTS_RXEMPTY_Msk         (0x1ul << UART_FIFOSTS_RXEMPTY_Pos)

#define UART_FIFOSTS_RXFULL_Pos          (15)

#define UART_FIFOSTS_RXFULL_Msk          (0x1ul << UART_FIFOSTS_RXFULL_Pos)

#define UART_FIFOSTS_TXPTR_Pos           (16)

#define UART_FIFOSTS_TXPTR_Msk           (0x3ful << UART_FIFOSTS_TXPTR_Pos)

#define UART_FIFOSTS_TXEMPTY_Pos         (22)

#define UART_FIFOSTS_TXEMPTY_Msk         (0x1ul << UART_FIFOSTS_TXEMPTY_Pos)

#define UART_FIFOSTS_TXFULL_Pos          (23)

#define UART_FIFOSTS_TXFULL_Msk          (0x1ul << UART_FIFOSTS_TXFULL_Pos)

#define UART_FIFOSTS_TXOVIF_Pos          (24)

#define UART_FIFOSTS_TXOVIF_Msk          (0x1ul << UART_FIFOSTS_TXOVIF_Pos)

#define UART_FIFOSTS_TXEMPTYF_Pos        (28)

#define UART_FIFOSTS_TXEMPTYF_Msk        (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos)

#define UART_INTSTS_RDAIF_Pos            (0)

#define UART_INTSTS_RDAIF_Msk            (0x1ul << UART_INTSTS_RDAIF_Pos)

#define UART_INTSTS_THREIF_Pos           (1)

#define UART_INTSTS_THREIF_Msk           (0x1ul << UART_INTSTS_THREIF_Pos)

#define UART_INTSTS_RLSIF_Pos            (2)

#define UART_INTSTS_RLSIF_Msk            (0x1ul << UART_INTSTS_RLSIF_Pos)

#define UART_INTSTS_MODEMIF_Pos          (3)

#define UART_INTSTS_MODEMIF_Msk          (0x1ul << UART_INTSTS_MODEMIF_Pos)

#define UART_INTSTS_RXTOIF_Pos           (4)

#define UART_INTSTS_RXTOIF_Msk           (0x1ul << UART_INTSTS_RXTOIF_Pos)

#define UART_INTSTS_BUFERRIF_Pos         (5)

#define UART_INTSTS_BUFERRIF_Msk         (0x1ul << UART_INTSTS_BUFERRIF_Pos)

#define UART_INTSTS_WKIF_Pos             (6)

#define UART_INTSTS_WKIF_Msk             (0x1ul << UART_INTSTS_WKIF_Pos)

#define UART_INTSTS_LINIF_Pos            (7)

#define UART_INTSTS_LINIF_Msk            (0x1ul << UART_INTSTS_LINIF_Pos)

#define UART_INTSTS_RDAINT_Pos           (8)

#define UART_INTSTS_RDAINT_Msk           (0x1ul << UART_INTSTS_RDAINT_Pos)

#define UART_INTSTS_THREINT_Pos          (9)

#define UART_INTSTS_THREINT_Msk          (0x1ul << UART_INTSTS_THREINT_Pos)

#define UART_INTSTS_RLSINT_Pos           (10)

#define UART_INTSTS_RLSINT_Msk           (0x1ul << UART_INTSTS_RLSINT_Pos)

#define UART_INTSTS_MODEMINT_Pos         (11)

#define UART_INTSTS_MODEMINT_Msk         (0x1ul << UART_INTSTS_MODEMINT_Pos)

#define UART_INTSTS_RXTOINT_Pos          (12)

#define UART_INTSTS_RXTOINT_Msk          (0x1ul << UART_INTSTS_RXTOINT_Pos)

#define UART_INTSTS_BUFERRINT_Pos        (13)

#define UART_INTSTS_BUFERRINT_Msk        (0x1ul << UART_INTSTS_BUFERRINT_Pos)

#define UART_INTSTS_LININT_Pos           (15)

#define UART_INTSTS_LININT_Msk           (0x1ul << UART_INTSTS_LININT_Pos)

#define UART_INTSTS_CTSWKIF_Pos          (16)

#define UART_INTSTS_CTSWKIF_Msk          (0x1ul << UART_INTSTS_CTSWKIF_Pos)

#define UART_INTSTS_DATWKIF_Pos          (17)

#define UART_INTSTS_DATWKIF_Msk          (0x1ul << UART_INTSTS_DATWKIF_Pos)

#define UART_INTSTS_HWRLSIF_Pos          (18)

#define UART_INTSTS_HWRLSIF_Msk          (0x1ul << UART_INTSTS_HWRLSIF_Pos)

#define UART_INTSTS_HWMODIF_Pos          (19)

#define UART_INTSTS_HWMODIF_Msk          (0x1ul << UART_INTSTS_HWMODIF_Pos)

#define UART_INTSTS_HWTOIF_Pos           (20)

#define UART_INTSTS_HWTOIF_Msk           (0x1ul << UART_INTSTS_HWTOIF_Pos)

#define UART_INTSTS_HWBUFEIF_Pos         (21)

#define UART_INTSTS_HWBUFEIF_Msk         (0x1ul << UART_INTSTS_HWBUFEIF_Pos)

#define UART_INTSTS_HWRLSINT_Pos         (26)

#define UART_INTSTS_HWRLSINT_Msk         (0x1ul << UART_INTSTS_HWRLSINT_Pos)

#define UART_INTSTS_HWMODINT_Pos         (27)

#define UART_INTSTS_HWMODINT_Msk         (0x1ul << UART_INTSTS_HWMODINT_Pos)

#define UART_INTSTS_HWTOINT_Pos          (28)

#define UART_INTSTS_HWTOINT_Msk          (0x1ul << UART_INTSTS_HWTOINT_Pos)

#define UART_INTSTS_HWBUFEINT_Pos        (29)

#define UART_INTSTS_HWBUFEINT_Msk        (0x1ul << UART_INTSTS_HWBUFEINT_Pos)

#define UART_TOUT_TOIC_Pos               (0)

#define UART_TOUT_TOIC_Msk               (0xfful << UART_TOUT_TOIC_Pos)

#define UART_TOUT_DLY_Pos                (8)

#define UART_TOUT_DLY_Msk                (0xfful << UART_TOUT_DLY_Pos)

#define UART_BAUD_BRD_Pos                (0)

#define UART_BAUD_BRD_Msk                (0xfffful << UART_BAUD_BRD_Pos)

#define UART_BAUD_EDIVM1_Pos             (24)

#define UART_BAUD_EDIVM1_Msk             (0xful << UART_BAUD_EDIVM1_Pos)

#define UART_BAUD_BAUDM0_Pos             (28)

#define UART_BAUD_BAUDM0_Msk             (0x1ul << UART_BAUD_BAUDM0_Pos)

#define UART_BAUD_BAUDM1_Pos             (29)

#define UART_BAUD_BAUDM1_Msk             (0x1ul << UART_BAUD_BAUDM1_Pos)

#define UART_IRDA_TXEN_Pos               (1)

#define UART_IRDA_TXEN_Msk               (0x1ul << UART_IRDA_TXEN_Pos)

#define UART_IRDA_TXINV_Pos              (5)

#define UART_IRDA_TXINV_Msk              (0x1ul << UART_IRDA_TXINV_Pos)

#define UART_IRDA_RXINV_Pos              (6)

#define UART_IRDA_RXINV_Msk              (0x1ul << UART_IRDA_RXINV_Pos)

#define UART_ALTCTL_BRKFL_Pos            (0)

#define UART_ALTCTL_BRKFL_Msk            (0xful << UART_ALTCTL_BRKFL_Pos)

#define UART_ALTCTL_LINRXEN_Pos          (6)

#define UART_ALTCTL_LINRXEN_Msk          (0x1ul << UART_ALTCTL_LINRXEN_Pos)

#define UART_ALTCTL_LINTXEN_Pos          (7)

#define UART_ALTCTL_LINTXEN_Msk          (0x1ul << UART_ALTCTL_LINTXEN_Pos)

#define UART_ALTCTL_RS485NMM_Pos         (8)

#define UART_ALTCTL_RS485NMM_Msk         (0x1ul << UART_ALTCTL_RS485NMM_Pos)

#define UART_ALTCTL_RS485AAD_Pos         (9)

#define UART_ALTCTL_RS485AAD_Msk         (0x1ul << UART_ALTCTL_RS485AAD_Pos)

#define UART_ALTCTL_RS485AUD_Pos         (10)

#define UART_ALTCTL_RS485AUD_Msk         (0x1ul << UART_ALTCTL_RS485AUD_Pos)

#define UART_ALTCTL_ADDRDEN_Pos          (15)

#define UART_ALTCTL_ADDRDEN_Msk          (0x1ul << UART_ALTCTL_ADDRDEN_Pos)

#define UART_ALTCTL_ABRIF_Pos            (17)

#define UART_ALTCTL_ABRIF_Msk            (0x1ul << UART_ALTCTL_ABRIF_Pos)

#define UART_ALTCTL_ABRDEN_Pos           (18)

#define UART_ALTCTL_ABRDEN_Msk           (0x1ul << UART_ALTCTL_ABRDEN_Pos)

#define UART_ALTCTL_ABRDBITS_Pos         (19)

#define UART_ALTCTL_ABRDBITS_Msk         (0x3ul << UART_ALTCTL_ABRDBITS_Pos)

#define UART_ALTCTL_ADDRMV_Pos           (24)

#define UART_ALTCTL_ADDRMV_Msk           (0xfful << UART_ALTCTL_ADDRMV_Pos)

#define UART_FUNCSEL_FUNCSEL_Pos         (0)

#define UART_FUNCSEL_FUNCSEL_Msk         (0x3ul << UART_FUNCSEL_FUNCSEL_Pos)                /* UART_CONST */ /* end of UART register group */


/*---------------------- Universal Serial Bus Controller -------------------------*/

typedef struct

{


    __IO uint32_t BUFSEG;        /* Offset: 0x500/0x510/0x520/0x530/0x540/0x550/0x560/0x570  Endpoint 0~7 Buffer Segmentation Register */

    __IO uint32_t MXPLD;         /* Offset: 0x504/0x514/0x524/0x534/0x544/0x554/0x564/0x574  Endpoint 0~7 Maximal Payload Register */

    __IO uint32_t CFG;           /* Offset: 0x508/0x518/0x528/0x538/0x548/0x558/0x568/0x578  Endpoint 0~7 Configuration Register */

    __IO uint32_t CFGP;          /* Offset: 0x50C/0x51C/0x52C/0x53C/0x54C/0x55C/0x56C/0x57C  Endpoint 0~7 Set Stall and Clear In/Out Ready Control Register */


} USBD_EP_T;


typedef struct

{


    __IO uint32_t INTEN;         /* Offset: 0x00  USB Interrupt Enable Register                                      */

    __IO uint32_t INTSTS;        /* Offset: 0x04  USB Interrupt Event Status Register                                */

    __IO uint32_t FADDR;         /* Offset: 0x08  USB Device Function Address Register                               */

    __I  uint32_t EPSTS;         /* Offset: 0x0C  USB Endpoint Status Register                                       */

    __IO uint32_t ATTR;          /* Offset: 0x10  USB Bus Status and Attribution Register                            */

    __I  uint32_t VBUSDET;       /* Offset: 0x14  USB Device VBUS Detection Register                                 */

    __IO uint32_t STBUFSEG;      /* Offset: 0x18  Setup Token Buffer Segmentation Register                           */

    __I  uint32_t RESERVE0[29];

    __IO uint32_t SE0;           /* Offset: 0x90  USB Drive SE0 Control Register                                     */

    __I  uint32_t RESERVE1[283];

    USBD_EP_T     EP[8];         /* Offset: 0x500 ~ 0x57C  USB End Point 0 ~ 7 Configuration Register                */


} USBD_T;


#define USBD_INTEN_BUSIEN_Pos            (0)

#define USBD_INTEN_BUSIEN_Msk            (0x1ul << USBD_INTEN_BUSIEN_Pos)

#define USBD_INTEN_USBIEN_Pos            (1)

#define USBD_INTEN_USBIEN_Msk            (0x1ul << USBD_INTEN_USBIEN_Pos)

#define USBD_INTEN_VBDETIEN_Pos          (2)

#define USBD_INTEN_VBDETIEN_Msk          (0x1ul << USBD_INTEN_VBDETIEN_Pos)

#define USBD_INTEN_NEVWKIEN_Pos          (3)

#define USBD_INTEN_NEVWKIEN_Msk          (0x1ul << USBD_INTEN_NEVWKIEN_Pos)

#define USBD_INTEN_WKEN_Pos              (8)

#define USBD_INTEN_WKEN_Msk              (0x1ul << USBD_INTEN_WKEN_Pos)

#define USBD_INTEN_INNAKEN_Pos           (15)

#define USBD_INTEN_INNAKEN_Msk           (0x1ul << USBD_INTEN_INNAKEN_Pos)

#define USBD_INTSTS_BUSIF_Pos            (0)

#define USBD_INTSTS_BUSIF_Msk            (0x1ul << USBD_INTSTS_BUSIF_Pos)

#define USBD_INTSTS_USBIF_Pos            (1)

#define USBD_INTSTS_USBIF_Msk            (0x1ul << USBD_INTSTS_USBIF_Pos)

#define USBD_INTSTS_VBDETIF_Pos          (2)

#define USBD_INTSTS_VBDETIF_Msk          (0x1ul << USBD_INTSTS_VBDETIF_Pos)

#define USBD_INTSTS_NEVWKIF_Pos          (3)

#define USBD_INTSTS_NEVWKIF_Msk          (0x1ul << USBD_INTSTS_NEVWKIF_Pos)

#define USBD_INTSTS_SOFIF_Pos            (4)

#define USBD_INTSTS_SOFIF_Msk            (0x1ul << USBD_INTSTS_SOFIF_Pos)

#define USBD_INTSTS_EPEVT0_Pos           (16)

#define USBD_INTSTS_EPEVT0_Msk           (0x1ul << USBD_INTSTS_EPEVT0_Pos)

#define USBD_INTSTS_EPEVT1_Pos           (17)

#define USBD_INTSTS_EPEVT1_Msk           (0x1ul << USBD_INTSTS_EPEVT1_Pos)

#define USBD_INTSTS_EPEVT2_Pos           (18)

#define USBD_INTSTS_EPEVT2_Msk           (0x1ul << USBD_INTSTS_EPEVT2_Pos)

#define USBD_INTSTS_EPEVT3_Pos           (19)

#define USBD_INTSTS_EPEVT3_Msk           (0x1ul << USBD_INTSTS_EPEVT3_Pos)

#define USBD_INTSTS_EPEVT4_Pos           (20)

#define USBD_INTSTS_EPEVT4_Msk           (0x1ul << USBD_INTSTS_EPEVT4_Pos)

#define USBD_INTSTS_EPEVT5_Pos           (21)

#define USBD_INTSTS_EPEVT5_Msk           (0x1ul << USBD_INTSTS_EPEVT5_Pos)

#define USBD_INTSTS_EPEVT6_Pos           (22)

#define USBD_INTSTS_EPEVT6_Msk           (0x1ul << USBD_INTSTS_EPEVT6_Pos)

#define USBD_INTSTS_EPEVT7_Pos           (23)

#define USBD_INTSTS_EPEVT7_Msk           (0x1ul << USBD_INTSTS_EPEVT7_Pos)

#define USBD_INTSTS_SETUP_Pos            (31)

#define USBD_INTSTS_SETUP_Msk            (0x1ul << USBD_INTSTS_SETUP_Pos)

#define USBD_FADDR_FADDR_Pos             (0)

#define USBD_FADDR_FADDR_Msk             (0x7ful << USBD_FADDR_FADDR_Pos)

#define USBD_EPSTS_OV_Pos                (7)

#define USBD_EPSTS_OV_Msk                (0x1ul << USBD_EPSTS_OV_Pos)

#define USBD_EPSTS_EPSTS0_Pos            (8)

#define USBD_EPSTS_EPSTS0_Msk            (0x7ul << USBD_EPSTS_EPSTS0_Pos)

#define USBD_EPSTS_EPSTS1_Pos            (11)

#define USBD_EPSTS_EPSTS1_Msk            (0x7ul << USBD_EPSTS_EPSTS1_Pos)

#define USBD_EPSTS_EPSTS2_Pos            (14)

#define USBD_EPSTS_EPSTS2_Msk            (0x7ul << USBD_EPSTS_EPSTS2_Pos)

#define USBD_EPSTS_EPSTS3_Pos            (17)

#define USBD_EPSTS_EPSTS3_Msk            (0x7ul << USBD_EPSTS_EPSTS3_Pos)

#define USBD_EPSTS_EPSTS4_Pos            (20)

#define USBD_EPSTS_EPSTS4_Msk            (0x7ul << USBD_EPSTS_EPSTS4_Pos)

#define USBD_EPSTS_EPSTS5_Pos            (23)

#define USBD_EPSTS_EPSTS5_Msk            (0x7ul << USBD_EPSTS_EPSTS5_Pos)

#define USBD_EPSTS_EPSTS6_Pos            (26)

#define USBD_EPSTS_EPSTS6_Msk            (0x7ul << USBD_EPSTS_EPSTS6_Pos)

#define USBD_EPSTS_EPSTS7_Pos            (29)

#define USBD_EPSTS_EPSTS7_Msk            (0x7ul << USBD_EPSTS_EPSTS7_Pos)

#define USBD_ATTR_USBRST_Pos             (0)

#define USBD_ATTR_USBRST_Msk             (0x1ul << USBD_ATTR_USBRST_Pos)

#define USBD_ATTR_SUSPEND_Pos            (1)

#define USBD_ATTR_SUSPEND_Msk            (0x1ul << USBD_ATTR_SUSPEND_Pos)

#define USBD_ATTR_RESUME_Pos             (2)

#define USBD_ATTR_RESUME_Msk             (0x1ul << USBD_ATTR_RESUME_Pos)

#define USBD_ATTR_TOUT_Pos               (3)

#define USBD_ATTR_TOUT_Msk               (0x1ul << USBD_ATTR_TOUT_Pos)

#define USBD_ATTR_PHYEN_Pos              (4)

#define USBD_ATTR_PHYEN_Msk              (0x1ul << USBD_ATTR_PHYEN_Pos)

#define USBD_ATTR_RWAKEUP_Pos            (5)

#define USBD_ATTR_RWAKEUP_Msk            (0x1ul << USBD_ATTR_RWAKEUP_Pos)

#define USBD_ATTR_USBEN_Pos              (7)

#define USBD_ATTR_USBEN_Msk              (0x1ul << USBD_ATTR_USBEN_Pos)

#define USBD_ATTR_DPPUEN_Pos             (8)

#define USBD_ATTR_DPPUEN_Msk             (0x1ul << USBD_ATTR_DPPUEN_Pos)

#define USBD_ATTR_PWRDN_Pos              (9)

#define USBD_ATTR_PWRDN_Msk              (0x1ul << USBD_ATTR_PWRDN_Pos)

#define USBD_ATTR_BYTEM_Pos              (10)

#define USBD_ATTR_BYTEM_Msk              (0x1ul << USBD_ATTR_BYTEM_Pos)

#define USBD_VBUSDET_VBUSDET_Pos         (0)

#define USBD_VBUSDET_VBUSDET_Msk         (0x1ul << USBD_VBUSDET_VBUSDET_Pos)

#define USBD_STBUFSEG_STBUFSEG_Pos       (3)

#define USBD_STBUFSEG_STBUFSEG_Msk       (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos)

#define USBD_SE0_SE0_Pos                 (0)

#define USBD_SE0_SE0_Msk                 (0x1ul << USBD_SE0_SE0_Pos)

#define USBD_BUFSEG_BUFSEG_Pos           (3)

#define USBD_BUFSEG_BUFSEG_Msk           (0x3ful << USBD_BUFSEG_BUFSEG_Pos)

#define USBD_MXPLD_MXPLD_Pos             (0)

#define USBD_MXPLD_MXPLD_Msk             (0x1fful << USBD_MXPLD_MXPLD_Pos)

#define USBD_CFG_EPNUM_Pos               (0)

#define USBD_CFG_EPNUM_Msk               (0xful << USBD_CFG_EPNUM_Pos)

#define USBD_CFG_ISOCH_Pos               (4)

#define USBD_CFG_ISOCH_Msk               (0x1ul << USBD_CFG_ISOCH_Pos)

#define USBD_CFG_STATE_Pos               (5)

#define USBD_CFG_STATE_Msk               (0x3ul << USBD_CFG_STATE_Pos)

#define USBD_CFG_DSQSYNC_Pos             (7)

#define USBD_CFG_DSQSYNC_Msk             (0x1ul << USBD_CFG_DSQSYNC_Pos)

#define USBD_CFG_CSTALL_Pos              (9)

#define USBD_CFG_CSTALL_Msk              (0x1ul << USBD_CFG_CSTALL_Pos)

#define USBD_CFGP_CLRRDY_Pos             (0)

#define USBD_CFGP_CLRRDY_Msk             (0x1ul << USBD_CFGP_CLRRDY_Pos)

#define USBD_CFGP_SSTALL_Pos             (1)

#define USBD_CFGP_SSTALL_Msk             (0x1ul << USBD_CFGP_SSTALL_Pos)                    /* USB_CONST */ /* end of USB register group */


/*---------------------- USB Host Controller -------------------------*/

typedef struct

{


    __I  uint32_t HcRevision;    /* Offset: 0x00  Host Controller Revision Register                                  */

    __IO uint32_t HcControl;     /* Offset: 0x04  Host Controller Control Register                                 */

    __IO uint32_t HcCommandStatus; /* Offset: 0x08  Host Controller CMD Status Register                                */

    __IO uint32_t HcInterruptStatus; /* Offset: 0x0C  Host Controller Interrupt Status Register                          */

    __IO uint32_t HcInterruptEnable; /* Offset: 0x10  Host Controller Interrupt Enable Register                          */

    __IO uint32_t HcInterruptDisable; /* Offset: 0x14  Host Controller Interrupt Disable Register                         */

    __IO uint32_t HcHCCA;        /* Offset: 0x18  Host Controller Communication Area Register                        */

    __IO uint32_t HcPeriodCurrentED; /* Offset: 0x1C  Host Controller Period Current ED Register                         */

    __IO uint32_t HcControlHeadED; /* Offset: 0x20  Host Controller Control Head ED Register                           */

    __IO uint32_t HcControlCurrentED; /* Offset: 0x24  Host Controller Control Current ED Register                        */

    __IO uint32_t HcBulkHeadED;  /* Offset: 0x28  Host Controller Bulk Head ED Register                              */

    __IO uint32_t HcBulkCurrentED; /* Offset: 0x2C  Host Controller Bulk Current ED Register                           */

    __IO uint32_t HcDoneHead;    /* Offset: 0x30  Host Controller Done Head Register                                 */

    __IO uint32_t HcFmInterval;  /* Offset: 0x34  Host Controller Frame Interval Register                            */

    __I  uint32_t HcFmRemaining; /* Offset: 0x38  Host Controller Frame Remaining Register                           */

    __I  uint32_t HcFmNumber;    /* Offset: 0x3C  Host Controller Frame Number Register                              */

    __IO uint32_t HcPeriodicStart; /* Offset: 0x40  Host Controller Periodic Start Register                            */

    __IO uint32_t HcLSThreshold; /* Offset: 0x44  Host Controller Low-speed Threshold Register                       */

    __IO uint32_t HcRhDescriptorA; /* Offset: 0x48  Host Controller Root Hub Descriptor A Register                     */

    __IO uint32_t HcRhDescriptorB; /* Offset: 0x4C  Host Controller Root Hub Descriptor B Register                     */

    __IO uint32_t HcRhStatus;    /* Offset: 0x50  Host Controller Root Hub Status Register                           */

    __IO uint32_t HcRhPortStatus[2]; /* Offset: 0x54  Host Controller Root Hub Port Status [1]                           */

    __I  uint32_t RESERVE0[105];

    __IO uint32_t HcPhyControl;  /* Offset: 0x200  USB Host Controller PHY Control Register                          */

    __IO uint32_t HcMiscControl; /* Offset: 0x204  USB Host Controller Miscellaneous Control Register                */


} USBH_T;


#define USBH_HcRevision_REV_Pos          (0)

#define USBH_HcRevision_REV_Msk          (0xfful << USBH_HcRevision_REV_Pos)

#define USBH_HcControl_CBSR_Pos          (0)

#define USBH_HcControl_CBSR_Msk          (0x3ul << USBH_HcControl_CBSR_Pos)

#define USBH_HcControl_PLE_Pos           (2)

#define USBH_HcControl_PLE_Msk           (0x1ul << USBH_HcControl_PLE_Pos)

#define USBH_HcControl_IE_Pos            (3)

#define USBH_HcControl_IE_Msk            (0x1ul << USBH_HcControl_IE_Pos)

#define USBH_HcControl_CLE_Pos           (4)

#define USBH_HcControl_CLE_Msk           (0x1ul << USBH_HcControl_CLE_Pos)

#define USBH_HcControl_BLE_Pos           (5)

#define USBH_HcControl_BLE_Msk           (0x1ul << USBH_HcControl_BLE_Pos)

#define USBH_HcControl_HCFS_Pos          (6)

#define USBH_HcControl_HCFS_Msk          (0x3ul << USBH_HcControl_HCFS_Pos)

#define USBH_HcCommandStatus_HCR_Pos     (0)

#define USBH_HcCommandStatus_HCR_Msk     (0x1ul << USBH_HcCommandStatus_HCR_Pos)

#define USBH_HcCommandStatus_CLF_Pos     (1)

#define USBH_HcCommandStatus_CLF_Msk     (0x1ul << USBH_HcCommandStatus_CLF_Pos)

#define USBH_HcCommandStatus_BLF_Pos     (2)

#define USBH_HcCommandStatus_BLF_Msk     (0x1ul << USBH_HcCommandStatus_BLF_Pos)

#define USBH_HcCommandStatus_SOC_Pos     (16)

#define USBH_HcCommandStatus_SOC_Msk     (0x3ul << USBH_HcCommandStatus_SOC_Pos)

#define USBH_HcInterruptStatus_SO_Pos    (0)

#define USBH_HcInterruptStatus_SO_Msk    (0x1ul << USBH_HcInterruptStatus_SO_Pos)

#define USBH_HcInterruptStatus_WDH_Pos   (1)

#define USBH_HcInterruptStatus_WDH_Msk   (0x1ul << USBH_HcInterruptStatus_WDH_Pos)

#define USBH_HcInterruptStatus_SF_Pos    (2)

#define USBH_HcInterruptStatus_SF_Msk    (0x1ul << USBH_HcInterruptStatus_SF_Pos)

#define USBH_HcInterruptStatus_RD_Pos    (3)

#define USBH_HcInterruptStatus_RD_Msk    (0x1ul << USBH_HcInterruptStatus_RD_Pos)

#define USBH_HcInterruptStatus_FNO_Pos   (5)

#define USBH_HcInterruptStatus_FNO_Msk   (0x1ul << USBH_HcInterruptStatus_FNO_Pos)

#define USBH_HcInterruptStatus_RHSC_Pos  (6)

#define USBH_HcInterruptStatus_RHSC_Msk  (0x1ul << USBH_HcInterruptStatus_RHSC_Pos)

#define USBH_HcInterruptEnable_SO_Pos    (0)

#define USBH_HcInterruptEnable_SO_Msk    (0x1ul << USBH_HcInterruptEnable_SO_Pos)

#define USBH_HcInterruptEnable_WDH_Pos   (1)

#define USBH_HcInterruptEnable_WDH_Msk   (0x1ul << USBH_HcInterruptEnable_WDH_Pos)

#define USBH_HcInterruptEnable_SF_Pos    (2)

#define USBH_HcInterruptEnable_SF_Msk    (0x1ul << USBH_HcInterruptEnable_SF_Pos)

#define USBH_HcInterruptEnable_RD_Pos    (3)

#define USBH_HcInterruptEnable_RD_Msk    (0x1ul << USBH_HcInterruptEnable_RD_Pos)

#define USBH_HcInterruptEnable_FNO_Pos   (5)

#define USBH_HcInterruptEnable_FNO_Msk   (0x1ul << USBH_HcInterruptEnable_FNO_Pos)

#define USBH_HcInterruptEnable_RHSC_Pos  (6)

#define USBH_HcInterruptEnable_RHSC_Msk  (0x1ul << USBH_HcInterruptEnable_RHSC_Pos)

#define USBH_HcInterruptEnable_MIE_Pos   (31)

#define USBH_HcInterruptEnable_MIE_Msk   (0x1ul << USBH_HcInterruptEnable_MIE_Pos)

#define USBH_HcInterruptDisable_SO_Pos   (0)

#define USBH_HcInterruptDisable_SO_Msk   (0x1ul << USBH_HcInterruptDisable_SO_Pos)

#define USBH_HcInterruptDisable_WDH_Pos  (1)

#define USBH_HcInterruptDisable_WDH_Msk  (0x1ul << USBH_HcInterruptDisable_WDH_Pos)

#define USBH_HcInterruptDisable_SF_Pos   (2)

#define USBH_HcInterruptDisable_SF_Msk   (0x1ul << USBH_HcInterruptDisable_SF_Pos)

#define USBH_HcInterruptDisable_RD_Pos   (3)

#define USBH_HcInterruptDisable_RD_Msk   (0x1ul << USBH_HcInterruptDisable_RD_Pos)

#define USBH_HcInterruptDisable_FNO_Pos  (5)

#define USBH_HcInterruptDisable_FNO_Msk  (0x1ul << USBH_HcInterruptDisable_FNO_Pos)

#define USBH_HcInterruptDisable_RHSC_Pos (6)

#define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos)

#define USBH_HcInterruptDisable_MIE_Pos  (31)

#define USBH_HcInterruptDisable_MIE_Msk  (0x1ul << USBH_HcInterruptDisable_MIE_Pos)

#define USBH_HcHCCA_HCCA_Pos             (8)

#define USBH_HcHCCA_HCCA_Msk             (0xfffffful << USBH_HcHCCA_HCCA_Pos)

#define USBH_HcPeriodCurrentED_PCED_Pos  (4)

#define USBH_HcPeriodCurrentED_PCED_Msk  (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos)

#define USBH_HcControlHeadED_CHED_Pos    (4)

#define USBH_HcControlHeadED_CHED_Msk    (0xffffffful << USBH_HcControlHeadED_CHED_Pos)

#define USBH_HcControlCurrentED_CCED_Pos (4)

#define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos)

#define USBH_HcBulkHeadED_BHED_Pos       (4)

#define USBH_HcBulkHeadED_BHED_Msk       (0xffffffful << USBH_HcBulkHeadED_BHED_Pos)

#define USBH_HcBulkCurrentED_BCED_Pos    (4)

#define USBH_HcBulkCurrentED_BCED_Msk    (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos)

#define USBH_HcDoneHead_DH_Pos           (4)

#define USBH_HcDoneHead_DH_Msk           (0xffffffful << USBH_HcDoneHead_DH_Pos)

#define USBH_HcFmInterval_FI_Pos         (0)

#define USBH_HcFmInterval_FI_Msk         (0x3ffful << USBH_HcFmInterval_FI_Pos)

#define USBH_HcFmInterval_FSMPS_Pos      (16)

#define USBH_HcFmInterval_FSMPS_Msk      (0x7ffful << USBH_HcFmInterval_FSMPS_Pos)

#define USBH_HcFmInterval_FIT_Pos        (31)

#define USBH_HcFmInterval_FIT_Msk        (0x1ul << USBH_HcFmInterval_FIT_Pos)

#define USBH_HcFmRemaining_FR_Pos        (0)

#define USBH_HcFmRemaining_FR_Msk        (0x3ffful << USBH_HcFmRemaining_FR_Pos)

#define USBH_HcFmRemaining_FRT_Pos       (31)

#define USBH_HcFmRemaining_FRT_Msk       (0x1ul << USBH_HcFmRemaining_FRT_Pos)

#define USBH_HcFmNumber_FN_Pos           (0)

#define USBH_HcFmNumber_FN_Msk           (0xfffful << USBH_HcFmNumber_FN_Pos)

#define USBH_HcPeriodicStart_PS_Pos      (0)

#define USBH_HcPeriodicStart_PS_Msk      (0x3ffful << USBH_HcPeriodicStart_PS_Pos)

#define USBH_HcLSThreshold_LST_Pos       (0)

#define USBH_HcLSThreshold_LST_Msk       (0xffful << USBH_HcLSThreshold_LST_Pos)

#define USBH_HcRhDescriptorA_NDP_Pos     (0)

#define USBH_HcRhDescriptorA_NDP_Msk     (0xfful << USBH_HcRhDescriptorA_NDP_Pos)

#define USBH_HcRhDescriptorA_PSM_Pos     (8)

#define USBH_HcRhDescriptorA_PSM_Msk     (0x1ul << USBH_HcRhDescriptorA_PSM_Pos)

#define USBH_HcRhDescriptorA_OCPM_Pos    (11)

#define USBH_HcRhDescriptorA_OCPM_Msk    (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos)

#define USBH_HcRhDescriptorA_NOCP_Pos    (12)

#define USBH_HcRhDescriptorA_NOCP_Msk    (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos)

#define USBH_HcRhDescriptorB_PPCM_Pos    (16)

#define USBH_HcRhDescriptorB_PPCM_Msk    (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos)

#define USBH_HcRhStatus_LPS_Pos          (0)

#define USBH_HcRhStatus_LPS_Msk          (0x1ul << USBH_HcRhStatus_LPS_Pos)

#define USBH_HcRhStatus_OCI_Pos          (1)

#define USBH_HcRhStatus_OCI_Msk          (0x1ul << USBH_HcRhStatus_OCI_Pos)

#define USBH_HcRhStatus_DRWE_Pos         (15)

#define USBH_HcRhStatus_DRWE_Msk         (0x1ul << USBH_HcRhStatus_DRWE_Pos)

#define USBH_HcRhStatus_LPSC_Pos         (16)

#define USBH_HcRhStatus_LPSC_Msk         (0x1ul << USBH_HcRhStatus_LPSC_Pos)

#define USBH_HcRhStatus_OCIC_Pos         (17)

#define USBH_HcRhStatus_OCIC_Msk         (0x1ul << USBH_HcRhStatus_OCIC_Pos)

#define USBH_HcRhStatus_CRWE_Pos         (31)

#define USBH_HcRhStatus_CRWE_Msk         (0x1ul << USBH_HcRhStatus_CRWE_Pos)

#define USBH_HcRhPortStatus_CCS_Pos      (0)

#define USBH_HcRhPortStatus_CCS_Msk      (0x1ul << USBH_HcRhPortStatus_CCS_Pos)

#define USBH_HcRhPortStatus_PES_Pos      (1)

#define USBH_HcRhPortStatus_PES_Msk      (0x1ul << USBH_HcRhPortStatus_PES_Pos)

#define USBH_HcRhPortStatus_PSS_Pos      (2)

#define USBH_HcRhPortStatus_PSS_Msk      (0x1ul << USBH_HcRhPortStatus_PSS_Pos)

#define USBH_HcRhPortStatus_POCI_Pos     (3)

#define USBH_HcRhPortStatus_POCI_Msk     (0x1ul << USBH_HcRhPortStatus_POCI_Pos)

#define USBH_HcRhPortStatus_PRS_Pos      (4)

#define USBH_HcRhPortStatus_PRS_Msk      (0x1ul << USBH_HcRhPortStatus_PRS_Pos)

#define USBH_HcRhPortStatus_PPS_Pos      (8)

#define USBH_HcRhPortStatus_PPS_Msk      (0x1ul << USBH_HcRhPortStatus_PPS_Pos)

#define USBH_HcRhPortStatus_LSDA_Pos     (9)

#define USBH_HcRhPortStatus_LSDA_Msk     (0x1ul << USBH_HcRhPortStatus_LSDA_Pos)

#define USBH_HcRhPortStatus_CSC_Pos      (16)

#define USBH_HcRhPortStatus_CSC_Msk      (0x1ul << USBH_HcRhPortStatus_CSC_Pos)

#define USBH_HcRhPortStatus_PESC_Pos     (17)

#define USBH_HcRhPortStatus_PESC_Msk     (0x1ul << USBH_HcRhPortStatus_PESC_Pos)

#define USBH_HcRhPortStatus_PSSC_Pos     (18)

#define USBH_HcRhPortStatus_PSSC_Msk     (0x1ul << USBH_HcRhPortStatus_PSSC_Pos)

#define USBH_HcRhPortStatus_OCIC_Pos     (19)

#define USBH_HcRhPortStatus_OCIC_Msk     (0x1ul << USBH_HcRhPortStatus_OCIC_Pos)

#define USBH_HcRhPortStatus_PRSC_Pos     (20)

#define USBH_HcRhPortStatus_PRSC_Msk     (0x1ul << USBH_HcRhPortStatus_PRSC_Pos)

#define USBH_HcPhyControl_STBYEN_Pos     (27)

#define USBH_HcPhyControl_STBYEN_Msk     (0x1ul << USBH_HcPhyControl_STBYEN_Pos)

#define USBH_HcMiscControl_ABORT_Pos     (1)

#define USBH_HcMiscControl_ABORT_Msk     (0x1ul << USBH_HcMiscControl_ABORT_Pos)

#define USBH_HcMiscControl_OCAL_Pos      (3)

#define USBH_HcMiscControl_OCAL_Msk      (0x1ul << USBH_HcMiscControl_OCAL_Pos)

#define USBH_HcMiscControl_DPRT1_Pos     (16)

#define USBH_HcMiscControl_DPRT1_Msk     (0x1ul << USBH_HcMiscControl_DPRT1_Pos)            /* USBH_CONST */ /* end of USBH register group */


/*---------------------- Watch Dog Timer Controller -------------------------*/

typedef struct

{


    __IO uint32_t CTL;           /* Offset: 0x00  WDT Control Register                                               */

    __IO uint32_t ALTCTL;        /* Offset: 0x04  WDT Alternative Control Register                                   */


} WDT_T;


#define WDT_CTL_RSTCNT_Pos               (0)

#define WDT_CTL_RSTCNT_Msk               (0x1ul << WDT_CTL_RSTCNT_Pos)

#define WDT_CTL_RSTEN_Pos                (1)

#define WDT_CTL_RSTEN_Msk                (0x1ul << WDT_CTL_RSTEN_Pos)

#define WDT_CTL_RSTF_Pos                 (2)

#define WDT_CTL_RSTF_Msk                 (0x1ul << WDT_CTL_RSTF_Pos)

#define WDT_CTL_IF_Pos                   (3)

#define WDT_CTL_IF_Msk                   (0x1ul << WDT_CTL_IF_Pos)

#define WDT_CTL_WKEN_Pos                 (4)

#define WDT_CTL_WKEN_Msk                 (0x1ul << WDT_CTL_WKEN_Pos)

#define WDT_CTL_WKF_Pos                  (5)

#define WDT_CTL_WKF_Msk                  (0x1ul << WDT_CTL_WKF_Pos)

#define WDT_CTL_INTEN_Pos                (6)

#define WDT_CTL_INTEN_Msk                (0x1ul << WDT_CTL_INTEN_Pos)

#define WDT_CTL_WDTEN_Pos                (7)

#define WDT_CTL_WDTEN_Msk                (0x1ul << WDT_CTL_WDTEN_Pos)

#define WDT_CTL_TOUTSEL_Pos              (8)

#define WDT_CTL_TOUTSEL_Msk              (0x7ul << WDT_CTL_TOUTSEL_Pos)

#define WDT_CTL_ICEDEBUG_Pos             (31)

#define WDT_CTL_ICEDEBUG_Msk             (0x1ul << WDT_CTL_ICEDEBUG_Pos)

#define WDT_ALTCTL_RSTDSEL_Pos           (0)

#define WDT_ALTCTL_RSTDSEL_Msk           (0x3ul << WDT_ALTCTL_RSTDSEL_Pos)                  /* WDT_CONST */ /* end of WDT register group */


/*---------------------- Window Watchdog Timer -------------------------*/

typedef struct

{


    __O  uint32_t RLDCNT;        /* Offset: 0x00  WWDT Reload Counter Register                                       */

    __IO uint32_t CTL;           /* Offset: 0x04  WWDT Control Register                                              */

    __IO uint32_t STATUS;        /* Offset: 0x08  WWDT Status Register                                               */

    __I  uint32_t CNT;           /* Offset: 0x0C  WWDT Counter Value Register                                        */


} WWDT_T;


#define WWDT_RLDCNT_WWDT_RLDCNT_Pos      (0)

#define WWDT_RLDCNT_WWDT_RLDCNT_Msk      (0xfffffffful << WWDT_RLDCNT_WWDT_RLDCNT_Pos)

#define WWDT_CTL_WWDTEN_Pos              (0)

#define WWDT_CTL_WWDTEN_Msk              (0x1ul << WWDT_CTL_WWDTEN_Pos)

#define WWDT_CTL_INTEN_Pos               (1)

#define WWDT_CTL_INTEN_Msk               (0x1ul << WWDT_CTL_INTEN_Pos)

#define WWDT_CTL_PSCSEL_Pos              (8)

#define WWDT_CTL_PSCSEL_Msk              (0xful << WWDT_CTL_PSCSEL_Pos)

#define WWDT_CTL_CMPDAT_Pos              (16)

#define WWDT_CTL_CMPDAT_Msk              (0x3ful << WWDT_CTL_CMPDAT_Pos)

#define WWDT_CTL_ICEDEBUG_Pos            (31)

#define WWDT_CTL_ICEDEBUG_Msk            (0x1ul << WWDT_CTL_ICEDEBUG_Pos)

#define WWDT_STATUS_WWDTIF_Pos           (0)

#define WWDT_STATUS_WWDTIF_Msk           (0x1ul << WWDT_STATUS_WWDTIF_Pos)

#define WWDT_STATUS_WWDTRF_Pos           (1)

#define WWDT_STATUS_WWDTRF_Msk           (0x1ul << WWDT_STATUS_WWDTRF_Pos)

#define WWDT_CNT_CNTDAT_Pos              (0)

#define WWDT_CNT_CNTDAT_Msk              (0x3ful << WWDT_CNT_CNTDAT_Pos)                    /* WWDT_CONST */ /* end of WWDT register group */


 /* end of REGISTER group */


/******************************************************************************/

/*                         Peripheral memory map                              */

/******************************************************************************/

/* Peripheral and SRAM base address */

#define SRAM_BASE            (0x20000000UL)

#define PERIPH_BASE          (0x40000000UL)

/* Peripheral memory map */

#define AHBPERIPH_BASE       PERIPH_BASE

#define APBPERIPH_BASE       (PERIPH_BASE + 0x00040000)


#define GCR_BASE             (AHBPERIPH_BASE + 0x00000)

#define CLK_BASE             (AHBPERIPH_BASE + 0x00200)

#define INT_BASE             (AHBPERIPH_BASE + 0x00300)

#define GPIO_BASE            (AHBPERIPH_BASE + 0x04000)

#define GPIOA_BASE           (AHBPERIPH_BASE + 0x04000)

#define GPIOB_BASE           (AHBPERIPH_BASE + 0x04040)

#define GPIOC_BASE           (AHBPERIPH_BASE + 0x04080)

#define GPIOD_BASE           (AHBPERIPH_BASE + 0x040C0)

#define GPIOE_BASE           (AHBPERIPH_BASE + 0x04100)

#define GPIOF_BASE           (AHBPERIPH_BASE + 0x04140)

#define GPIO_DBCTL_BASE      (AHBPERIPH_BASE + 0x04440)

#define GPIO_PIN_DATA_BASE   (AHBPERIPH_BASE + 0x04800)

#define PDMA_BASE            (AHBPERIPH_BASE + 0x08000)

#define USBH_BASE            (AHBPERIPH_BASE + 0x09000)

#define FMC_BASE             (AHBPERIPH_BASE + 0x0C000)

#define EBI_BASE             (AHBPERIPH_BASE + 0x10000)

#define CRC_BASE             (AHBPERIPH_BASE + 0x31000)


#define WDT_BASE             (APBPERIPH_BASE + 0x00000)

#define WWDT_BASE            (APBPERIPH_BASE + 0x00100)

#define TMR01_BASE           (APBPERIPH_BASE + 0x10000)

#define PWM0_BASE            (APBPERIPH_BASE + 0x18000)

#define SPI0_BASE            (APBPERIPH_BASE + 0x20000)

#define UART0_BASE           (APBPERIPH_BASE + 0x30000)

#define UART2_BASE           (APBPERIPH_BASE + 0x32000)

#define I2C0_BASE            (APBPERIPH_BASE + 0x40000)

#define SC0_BASE             (APBPERIPH_BASE + 0x50000)

#define USBD_BASE            (APBPERIPH_BASE + 0x80000)


#define RTC_BASE             (APBPERIPH_BASE + 0x01000)

#define EADC0_BASE           (APBPERIPH_BASE + 0x03000)

#define TMR23_BASE           (APBPERIPH_BASE + 0x11000)

#define PWM1_BASE            (APBPERIPH_BASE + 0x19000)

#define SPI1_BASE            (APBPERIPH_BASE + 0x21000)

#define UART1_BASE           (APBPERIPH_BASE + 0x31000)

#define UART3_BASE           (APBPERIPH_BASE + 0x33000)

#define I2C1_BASE            (APBPERIPH_BASE + 0x41000) /* end of group MemoryMap */


/******************************************************************************/

/*                         Peripheral declaration                             */

/******************************************************************************/

#define SYS                  ((SYS_T *)   GCR_BASE)

#define SYSINT               ((SYS_INT_T *) INT_BASE)

#define CLK                  ((CLK_T *)   CLK_BASE)

#define PA                   ((GPIO_T *)  GPIOA_BASE)

#define PB                   ((GPIO_T *)  GPIOB_BASE)

#define PC                   ((GPIO_T *)  GPIOC_BASE)

#define PD                   ((GPIO_T *)  GPIOD_BASE)

#define PE                   ((GPIO_T *)  GPIOE_BASE)

#define PF                   ((GPIO_T *)  GPIOF_BASE)

#define GPIO                 ((GPIO_DBCTL_T *) GPIO_DBCTL_BASE)

#define PDMA                 ((PDMA_T *)  PDMA_BASE)

#define USBH                 ((USBH_T *)  USBH_BASE)

#define FMC                  ((FMC_T *)   FMC_BASE)

#define EBI                  ((EBI_T *)   EBI_BASE)

#define CRC                  ((CRC_T *)   CRC_BASE)


#define WDT                  ((WDT_T *)   WDT_BASE)

#define WWDT                 ((WWDT_T *)  WWDT_BASE)

#define RTC                  ((RTC_T *)   RTC_BASE)

#define EADC                  ((EADC_T *)   EADC0_BASE)


#define USBD                 ((USBD_T *)  USBD_BASE)

#define TIMER0               ((TIMER_T *) TMR01_BASE)

#define TIMER1               ((TIMER_T *) (TMR01_BASE + 0x20))

#define TIMER2               ((TIMER_T *) TMR23_BASE)

#define TIMER3               ((TIMER_T *) (TMR23_BASE + 0x20))

#define PWM0                 ((PWM_T *)   PWM0_BASE)

#define PWM1                 ((PWM_T *)   PWM1_BASE)

#define SPI0                 ((SPI_T *)   SPI0_BASE)

#define SPI1                 ((SPI_T *)   SPI1_BASE)

#define UART0                ((UART_T *)  UART0_BASE)

#define UART1                ((UART_T *)  UART1_BASE)

#define UART2                ((UART_T *)  UART2_BASE)

#define UART3                ((UART_T *)  UART3_BASE)

#define I2C0                 ((I2C_T *)   I2C0_BASE)

#define I2C1                 ((I2C_T *)   I2C1_BASE)

#define SC0                  ((SC_T *)    SC0_BASE)


/* One Bit Mask Definitions */

#define BIT0    0x00000001

#define BIT1    0x00000002

#define BIT2    0x00000004

#define BIT3    0x00000008

#define BIT4    0x00000010

#define BIT5    0x00000020

#define BIT6    0x00000040

#define BIT7    0x00000080

#define BIT8    0x00000100

#define BIT9    0x00000200

#define BIT10   0x00000400

#define BIT11   0x00000800

#define BIT12   0x00001000

#define BIT13   0x00002000

#define BIT14   0x00004000

#define BIT15   0x00008000

#define BIT16   0x00010000

#define BIT17   0x00020000

#define BIT18   0x00040000

#define BIT19   0x00080000

#define BIT20   0x00100000

#define BIT21   0x00200000

#define BIT22   0x00400000

#define BIT23   0x00800000

#define BIT24   0x01000000

#define BIT25   0x02000000

#define BIT26   0x04000000

#define BIT27   0x08000000

#define BIT28   0x10000000

#define BIT29   0x20000000

#define BIT30   0x40000000

#define BIT31   0x80000000


/* Byte Mask Definitions */

#define BYTE0_Msk               (0x000000FF)

#define BYTE1_Msk               (0x0000FF00)

#define BYTE2_Msk               (0x00FF0000)

#define BYTE3_Msk               (0xFF000000)


#define _GET_BYTE0(u32Param)    (((u32Param) & BYTE0_Msk)      )

#define _GET_BYTE1(u32Param)    (((u32Param) & BYTE1_Msk) >>  8)

#define _GET_BYTE2(u32Param)    (((u32Param) & BYTE2_Msk) >> 16)

#define _GET_BYTE3(u32Param)    (((u32Param) & BYTE3_Msk) >> 24)

#ifndef TRUE

# define TRUE 1

#endif

#ifndef FALSE

# define FALSE 0

#endif


#ifndef NULL

#define NULL        0

#endif


#include "sys.h"

#include "clk.h"

#include "gpio.h"

#include "i2c.h"

#include "crc.h"

#include "ebi.h"

#include "rtc.h"

#include "timer.h"

#include "wdt.h"

#include "wwdt.h"

#include "spi.h"

#include "sc.h"

#include "scuart.h"

#include "eadc.h"

#include "usbd.h"

#include "fmc.h"

#include "uart.h"

#include "pwm.h"

#include "pdma.h"


typedef volatile unsigned char  vu8;

typedef volatile unsigned long  vu32;

typedef volatile unsigned short vu16;

#define M8(adr)  (*((vu8  *) (adr)))

#define M16(adr) (*((vu16 *) (adr)))

#define M32(adr) (*((vu32 *) (adr)))


#define outpw(port,value)   (*((volatile unsigned int *)(port))=(value))

#define inpw(port)          (*((volatile unsigned int *)(port)))

#define outpb(port,value)   (*((volatile unsigned char *)(port))=(value))

#define inpb(port)          (*((volatile unsigned char *)(port)))

#define outps(port,value)   (*((volatile unsigned short *)(port))=(value))

#define inps(port)          (*((volatile unsigned short *)(port)))


#define outp32(port,value)  (*((volatile unsigned int *)(port))=(value))

#define inp32(port)         (*((volatile unsigned int *)(port)))

#define outp8(port,value)   (*((volatile unsigned char *)(port))=(value))

#define inp8(port)          (*((volatile unsigned char *)(port)))

#define outp16(port,value)  (*((volatile unsigned short *)(port))=(value))

#define inp16(port)         (*((volatile unsigned short *)(port)))

 /* end of group PeripheralDecl */


#ifdef __cplusplus

}

#endif


#endif  /* __M4521_H__ */


clk.h
M4521 CLK Header File.

crc.h
M4521 CRC driver header file.

eadc.h
M4521 EADC driver header file.

ebi.h
M4521 EBI driver header file.

fmc.h
M4521 Flash Memory Controller Driver Header File.

gpio.h
M4521 GPIO driver header file.

IRQn_Type
enum IRQn IRQn_Type

IRQn
IRQn
Definition: M4521.h:73

PendSV_IRQn
@ PendSV_IRQn
Definition: M4521.h:81

EINT0_IRQn
@ EINT0_IRQn
Definition: M4521.h:94

GPF_IRQn
@ GPF_IRQn
Definition: M4521.h:105

USBH_IRQn
@ USBH_IRQn
Definition: M4521.h:132

I2C0_IRQn
@ I2C0_IRQn
Definition: M4521.h:122

UART3_IRQn
@ UART3_IRQn
Definition: M4521.h:130

EINT3_IRQn
@ EINT3_IRQn
Definition: M4521.h:97

EINT4_IRQn
@ EINT4_IRQn
Definition: M4521.h:98

PWM1P2_IRQn
@ PWM1P2_IRQn
Definition: M4521.h:115

GPA_IRQn
@ GPA_IRQn
Definition: M4521.h:100

ADC02_IRQn
@ ADC02_IRQn
Definition: M4521.h:127

TAMPER_IRQn
@ TAMPER_IRQn
Definition: M4521.h:91

SC0_IRQn
@ SC0_IRQn
Definition: M4521.h:133

MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: M4521.h:76

USBD_IRQn
@ USBD_IRQn
Definition: M4521.h:131

EINT2_IRQn
@ EINT2_IRQn
Definition: M4521.h:96

PWRWU_IRQn
@ PWRWU_IRQn
Definition: M4521.h:88

SVCall_IRQn
@ SVCall_IRQn
Definition: M4521.h:79

BRAKE0_IRQn
@ BRAKE0_IRQn
Definition: M4521.h:108

EINT5_IRQn
@ EINT5_IRQn
Definition: M4521.h:99

PWM0P2_IRQn
@ PWM0P2_IRQn
Definition: M4521.h:111

PWM1P0_IRQn
@ PWM1P0_IRQn
Definition: M4521.h:113

UsageFault_IRQn
@ UsageFault_IRQn
Definition: M4521.h:78

GPC_IRQn
@ GPC_IRQn
Definition: M4521.h:102

SysTick_IRQn
@ SysTick_IRQn
Definition: M4521.h:82

ADC01_IRQn
@ ADC01_IRQn
Definition: M4521.h:126

GPD_IRQn
@ GPD_IRQn
Definition: M4521.h:103

ADC03_IRQn
@ ADC03_IRQn
Definition: M4521.h:128

WDT_IRQn
@ WDT_IRQn
Definition: M4521.h:92

PWM0P0_IRQn
@ PWM0P0_IRQn
Definition: M4521.h:109

PDMA_IRQn
@ PDMA_IRQn
Definition: M4521.h:124

TMR1_IRQn
@ TMR1_IRQn
Definition: M4521.h:117

BusFault_IRQn
@ BusFault_IRQn
Definition: M4521.h:77

WWDT_IRQn
@ WWDT_IRQn
Definition: M4521.h:93

DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: M4521.h:80

TMR2_IRQn
@ TMR2_IRQn
Definition: M4521.h:118

PWM1P1_IRQn
@ PWM1P1_IRQn
Definition: M4521.h:114

UART1_IRQn
@ UART1_IRQn
Definition: M4521.h:121

IRC_IRQn
@ IRC_IRQn
Definition: M4521.h:87

PWM0P1_IRQn
@ PWM0P1_IRQn
Definition: M4521.h:110

SPI1_IRQn
@ SPI1_IRQn
Definition: M4521.h:107

UART2_IRQn
@ UART2_IRQn
Definition: M4521.h:129

TMR0_IRQn
@ TMR0_IRQn
Definition: M4521.h:116

BOD_IRQn
@ BOD_IRQn
Definition: M4521.h:86

CKFAIL_IRQn
@ CKFAIL_IRQn
Definition: M4521.h:89

BRAKE1_IRQn
@ BRAKE1_IRQn
Definition: M4521.h:112

EINT1_IRQn
@ EINT1_IRQn
Definition: M4521.h:95

RTC_IRQn
@ RTC_IRQn
Definition: M4521.h:90

NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: M4521.h:75

TMR3_IRQn
@ TMR3_IRQn
Definition: M4521.h:119

UART0_IRQn
@ UART0_IRQn
Definition: M4521.h:120

GPE_IRQn
@ GPE_IRQn
Definition: M4521.h:104

I2C1_IRQn
@ I2C1_IRQn
Definition: M4521.h:123

GPB_IRQn
@ GPB_IRQn
Definition: M4521.h:101

SPI0_IRQn
@ SPI0_IRQn
Definition: M4521.h:106

ADC00_IRQn
@ ADC00_IRQn
Definition: M4521.h:125

USBH_T::HcBulkCurrentED
__IO uint32_t HcBulkCurrentED
Definition: M4521.h:13227

UART_T::DAT
__IO uint32_t DAT
Definition: M4521.h:11887

TIMER_T::CNT
__I uint32_t CNT
Definition: M4521.h:11259

PWM_T::SSTRG
__O uint32_t SSTRG
Definition: M4521.h:5870

PWM_T::FCAPDAT2
__I uint32_t FCAPDAT2
Definition: M4521.h:5882

SYS_T::SRAM_BISTCTL
__IO uint32_t SRAM_BISTCTL
Definition: M4521.h:10336

CLK_T::PWRCTL
__IO uint32_t PWRCTL
Definition: M4521.h:1417

I2C_T::CLKTOUT
__IO uint32_t CLKTOUT
Definition: M4521.h:3727

PWM_T::DTCTL2_3
__IO uint32_t DTCTL2_3
Definition: M4521.h:5836

FMC_T::FTCTL
__IO uint32_t FTCTL
Definition: M4521.h:2345

SPI_T::I2SCLK
__IO uint32_t I2SCLK
Definition: M4521.h:9321

SC_T::DAT
__IO uint32_t DAT
Definition: M4521.h:8496

USBD_T::SE0
__IO uint32_t SE0
Definition: M4521.h:12521

PDMA_T::TOUTEN
__IO uint32_t TOUTEN
Definition: M4521.h:4342

FMC_T::ISPCMD
__IO uint32_t ISPCMD
Definition: M4521.h:2342

FMC_T::MPADDR
__I uint32_t MPADDR
Definition: M4521.h:2355

RTC_T::CLKFMT
__IO uint32_t CLKFMT
Definition: M4521.h:7646

I2C_T::ADDR2
__IO uint32_t ADDR2
Definition: M4521.h:3712

CLK_T::APBCLK0
__IO uint32_t APBCLK0
Definition: M4521.h:1419

UART_T::INTEN
__IO uint32_t INTEN
Definition: M4521.h:11888

USBD_EP_T::CFG
__IO uint32_t CFG
Definition: M4521.h:12277

PDMA_T::SCATSTS
__IO uint32_t SCATSTS
Definition: M4521.h:4339

CRC_T::SEED
__IO uint32_t SEED
Definition: M4521.h:1814

EADC_T::CTL
__IO uint32_t CTL
Definition: M4521.h:727

PDMA_T::TOUTIEN
__IO uint32_t TOUTIEN
Definition: M4521.h:4343

PWM_T::CNTEN
__IO uint32_t CNTEN
Definition: M4521.h:5827

PDMA_T::REQSEL8_11
__IO uint32_t REQSEL8_11
Definition: M4521.h:4352

SC_T::TMRCTL2
__IO uint32_t TMRCTL2
Definition: M4521.h:8508

SYS_T::IRC48MTIEN
__IO uint32_t IRC48MTIEN
Definition: M4521.h:10346

UART_T::FIFOSTS
__IO uint32_t FIFOSTS
Definition: M4521.h:11893

PWM_T::RCAPDAT5
__I uint32_t RCAPDAT5
Definition: M4521.h:5887

USBH_T::HcRhDescriptorB
__IO uint32_t HcRhDescriptorB
Definition: M4521.h:13235

PDMA_T::PRISET
__IO uint32_t PRISET
Definition: M4521.h:4333

SYS_T::IPRST2
__IO uint32_t IPRST2
Definition: M4521.h:10316

PWM_T::FTCMPDAT4_5
__IO uint32_t FTCMPDAT4_5
Definition: M4521.h:5867

FMC_T::ISPTRG
__IO uint32_t ISPTRG
Definition: M4521.h:2343

SPI_T::I2SCTL
__IO uint32_t I2SCTL
Definition: M4521.h:9320

USBH_T::HcPhyControl
__IO uint32_t HcPhyControl
Definition: M4521.h:13239

SYS_T::REGLCTL
__IO uint32_t REGLCTL
Definition: M4521.h:10343

DSCT_T::SA
__IO uint32_t SA
Definition: M4521.h:3997

SYS_T::IRCTISTS
__IO uint32_t IRCTISTS
Definition: M4521.h:10341

USBD_T::INTEN
__IO uint32_t INTEN
Definition: M4521.h:12513

FMC_T::MPDAT2
__IO uint32_t MPDAT2
Definition: M4521.h:2351

SC_T::ALTCTL
__IO uint32_t ALTCTL
Definition: M4521.h:8498

SC_T::TMRDAT0
__I uint32_t TMRDAT0
Definition: M4521.h:8510

GPIO_T::SLEWCTL
__IO uint32_t SLEWCTL
Definition: M4521.h:2666

SYS_T::GPA_MFPH
__IO uint32_t GPA_MFPH
Definition: M4521.h:10325

EADC_T::PENDSTS
__IO uint32_t PENDSTS
Definition: M4521.h:729

CLK_T::APBCLK1
__IO uint32_t APBCLK1
Definition: M4521.h:1420

UART_T::ALTCTL
__IO uint32_t ALTCTL
Definition: M4521.h:11898

PWM_T::CLKSRC
__IO uint32_t CLKSRC
Definition: M4521.h:5823

CLK_T::CLKOCTL
__IO uint32_t CLKOCTL
Definition: M4521.h:1432

RTC_T::LXTCTL
__IO uint32_t LXTCTL
Definition: M4521.h:7659

SYS_INT_T::NMISTS
__I uint32_t NMISTS
Definition: M4521.h:10980

USBH_T::HcFmInterval
__IO uint32_t HcFmInterval
Definition: M4521.h:13229

PDMA_T::TACTSTS
__I uint32_t TACTSTS
Definition: M4521.h:4340

TIMER_T::INTSTS
__IO uint32_t INTSTS
Definition: M4521.h:11258

SC_T::ETUCTL
__IO uint32_t ETUCTL
Definition: M4521.h:8501

EBI_T::CTL0
__IO uint32_t CTL0
Definition: M4521.h:2000

CLK_T::CLKDIV1
__IO uint32_t CLKDIV1
Definition: M4521.h:1426

PDMA_T::TOC6_7
__IO uint32_t TOC6_7
Definition: M4521.h:4348

PWM_T::FCAPDAT3
__I uint32_t FCAPDAT3
Definition: M4521.h:5884

RTC_T::TAMPCTL
__IO uint32_t TAMPCTL
Definition: M4521.h:7662

I2C_T::BUSTCTL
__IO uint32_t BUSTCTL
Definition: M4521.h:3722

EADC_T::OVSTS
__IO uint32_t OVSTS
Definition: M4521.h:730

SPI_T::I2SSTS
__IO uint32_t I2SSTS
Definition: M4521.h:9322

PDMA_T::TDSTS
__IO uint32_t TDSTS
Definition: M4521.h:4338

RTC_T::LXTICTL
__IO uint32_t LXTICTL
Definition: M4521.h:7661

SYS_T::RSTSTS
__IO uint32_t RSTSTS
Definition: M4521.h:10313

CLK_T::CLKSEL1
__IO uint32_t CLKSEL1
Definition: M4521.h:1422

PWM_T::RCAPDAT2
__I uint32_t RCAPDAT2
Definition: M4521.h:5881

EADC_T::STATUS0
__I uint32_t STATUS0
Definition: M4521.h:736

I2C_T::ADDR3
__IO uint32_t ADDR3
Definition: M4521.h:3713

RTC_T::RWEN
__O uint32_t RWEN
Definition: M4521.h:7642

RTC_T::FREQADJ
__IO uint32_t FREQADJ
Definition: M4521.h:7643

PWM_T::IFA
__IO uint32_t IFA
Definition: M4521.h:5861

PWM_T::WGCTL0
__IO uint32_t WGCTL0
Definition: M4521.h:5845

PWM_T::RCAPDAT3
__I uint32_t RCAPDAT3
Definition: M4521.h:5883

GPIO_T::DINOFF
__IO uint32_t DINOFF
Definition: M4521.h:2657

I2C_T::ADDRMSK1
__IO uint32_t ADDRMSK1
Definition: M4521.h:3715

PWM_T::CNTCLR
__IO uint32_t CNTCLR
Definition: M4521.h:5828

PWM_T::FTCMPDAT2_3
__IO uint32_t FTCMPDAT2_3
Definition: M4521.h:5866

PWM_T::INTEN1
__IO uint32_t INTEN1
Definition: M4521.h:5858

PWM_T::INTSTS0
__IO uint32_t INTSTS0
Definition: M4521.h:5859

PWM_T::FTCBUF4_5
__I uint32_t FTCBUF4_5
Definition: M4521.h:5902

FMC_T::MPDAT0
__IO uint32_t MPDAT0
Definition: M4521.h:2349

RTC_T::CAMSK
__IO uint32_t CAMSK
Definition: M4521.h:7655

SPI_T::FIFOCTL
__IO uint32_t FIFOCTL
Definition: M4521.h:9313

SYS_T::GPB_MFPH
__IO uint32_t GPB_MFPH
Definition: M4521.h:10327

PWM_T::CLKPSC0_1
__IO uint32_t CLKPSC0_1
Definition: M4521.h:5824

USBH_T::HcInterruptDisable
__IO uint32_t HcInterruptDisable
Definition: M4521.h:13221

SPI_T::STATUS
__IO uint32_t STATUS
Definition: M4521.h:9314

SYS_T::IRC48MTCTL
__IO uint32_t IRC48MTCTL
Definition: M4521.h:10345

SYS_T::VREFCTL
__IO uint32_t VREFCTL
Definition: M4521.h:10322

PWM_T::EADCTS1
__IO uint32_t EADCTS1
Definition: M4521.h:5864

GPIO_T::DBEN
__IO uint32_t DBEN
Definition: M4521.h:2661

SPI_T::CTL
__IO uint32_t CTL
Definition: M4521.h:9309

EADC_T::CURDAT
__I uint32_t CURDAT
Definition: M4521.h:726

PDMA_T::TOC0_1
__IO uint32_t TOC0_1
Definition: M4521.h:4345

SYS_T::IRCTIEN
__IO uint32_t IRCTIEN
Definition: M4521.h:10340

FMC_T::MPDAT3
__IO uint32_t MPDAT3
Definition: M4521.h:2352

PWM_T::SSCTL
__IO uint32_t SSCTL
Definition: M4521.h:5869

SPI_T::RX
__I uint32_t RX
Definition: M4521.h:9318

I2C_T::ADDR0
__IO uint32_t ADDR0
Definition: M4521.h:3706

USBH_T::HcLSThreshold
__IO uint32_t HcLSThreshold
Definition: M4521.h:13233

EBI_T::TCTL0
__IO uint32_t TCTL0
Definition: M4521.h:2001

SC_T::INTEN
__IO uint32_t INTEN
Definition: M4521.h:8502

PWM_T::DTCTL0_1
__IO uint32_t DTCTL0_1
Definition: M4521.h:5835

RTC_T::INTSTS
__IO uint32_t INTSTS
Definition: M4521.h:7652

PDMA_T::STOP
__O uint32_t STOP
Definition: M4521.h:4330

I2C_T::TOCTL
__IO uint32_t TOCTL
Definition: M4521.h:3710

PDMA_T::PRICLR
__O uint32_t PRICLR
Definition: M4521.h:4334

SYS_T::IVSCTL
__IO uint32_t IVSCTL
Definition: M4521.h:10319

CLK_T::CLKDIV0
__IO uint32_t CLKDIV0
Definition: M4521.h:1425

CLK_T::CLKSEL0
__IO uint32_t CLKSEL0
Definition: M4521.h:1421

GPIO_T::MODE
__IO uint32_t MODE
Definition: M4521.h:2656

SYS_T::PORCTL
__IO uint32_t PORCTL
Definition: M4521.h:10321

PWM_T::FCAPDAT1
__I uint32_t FCAPDAT1
Definition: M4521.h:5880

FMC_T::MPDAT1
__IO uint32_t MPDAT1
Definition: M4521.h:2350

I2C_T::CLKDIV
__IO uint32_t CLKDIV
Definition: M4521.h:3709

GPIO_T::DATMSK
__IO uint32_t DATMSK
Definition: M4521.h:2659

PDMA_T::TRGSTS
__I uint32_t TRGSTS
Definition: M4521.h:4332

SC_T::CTL
__IO uint32_t CTL
Definition: M4521.h:8497

RTC_T::LXTOCTL
__IO uint32_t LXTOCTL
Definition: M4521.h:7660

PWM_T::MSKEN
__IO uint32_t MSKEN
Definition: M4521.h:5847

UART_T::FUNCSEL
__IO uint32_t FUNCSEL
Definition: M4521.h:11899

UART_T::BAUD
__IO uint32_t BAUD
Definition: M4521.h:11896

PWM_T::FCAPDAT5
__I uint32_t FCAPDAT5
Definition: M4521.h:5888

I2C_T::CTL
__IO uint32_t CTL
Definition: M4521.h:3705

PWM_T::CAPIF
__IO uint32_t CAPIF
Definition: M4521.h:5895

PWM_T::CAPSTS
__I uint32_t CAPSTS
Definition: M4521.h:5876

PDMA_T::TOC4_5
__IO uint32_t TOC4_5
Definition: M4521.h:4347

PWM_T::FCAPDAT0
__I uint32_t FCAPDAT0
Definition: M4521.h:5878

PWM_T::FTCI
__IO uint32_t FTCI
Definition: M4521.h:5903

USBD_EP_T::MXPLD
__IO uint32_t MXPLD
Definition: M4521.h:12276

PWM_T::SYNC
__IO uint32_t SYNC
Definition: M4521.h:5821

I2C_T::DAT
__IO uint32_t DAT
Definition: M4521.h:3707

TIMER_T::EINTSTS
__IO uint32_t EINTSTS
Definition: M4521.h:11262

I2C_T::PKTCRC
__I uint32_t PKTCRC
Definition: M4521.h:3725

vu32
volatile unsigned long vu32
Definition: M4521.h:13937

USBD_EP_T::CFGP
__IO uint32_t CFGP
Definition: M4521.h:12278

FMC_T::ISPSTS
__IO uint32_t ISPSTS
Definition: M4521.h:2347

PWM_T::INTSTS1
__IO uint32_t INTSTS1
Definition: M4521.h:5860

PDMA_T::SWREQ
__O uint32_t SWREQ
Definition: M4521.h:4331

SPI_T::PDMACTL
__IO uint32_t PDMACTL
Definition: M4521.h:9312

CLK_T::STATUS
__I uint32_t STATUS
Definition: M4521.h:1430

GPIO_T::PIN
__I uint32_t PIN
Definition: M4521.h:2660

PWM_T::RCAPDAT4
__I uint32_t RCAPDAT4
Definition: M4521.h:5885

CRC_T::CHECKSUM
__I uint32_t CHECKSUM
Definition: M4521.h:1815

I2C_T::ADDR1
__IO uint32_t ADDR1
Definition: M4521.h:3711

PWM_T::POLCTL
__IO uint32_t POLCTL
Definition: M4521.h:5854

I2C_T::BUSTOUT
__IO uint32_t BUSTOUT
Definition: M4521.h:3726

RTC_T::TAMSK
__IO uint32_t TAMSK
Definition: M4521.h:7654

FMC_T::ISPADDR
__IO uint32_t ISPADDR
Definition: M4521.h:2340

SC_T::STATUS
__IO uint32_t STATUS
Definition: M4521.h:8504

SYS_T::GPE_MFPL
__IO uint32_t GPE_MFPL
Definition: M4521.h:10332

USBH_T::HcHCCA
__IO uint32_t HcHCCA
Definition: M4521.h:13222

SC_T::PINCTL
__IO uint32_t PINCTL
Definition: M4521.h:8505

GPIO_T::INTTYPE
__IO uint32_t INTTYPE
Definition: M4521.h:2662

TIMER_T::CMP
__IO uint32_t CMP
Definition: M4521.h:11257

SC_T::TMRCTL0
__IO uint32_t TMRCTL0
Definition: M4521.h:8506

PWM_T::INTEN0
__IO uint32_t INTEN0
Definition: M4521.h:5857

PWM_T::SWBRK
__O uint32_t SWBRK
Definition: M4521.h:5856

TIMER_T::CAP
__I uint32_t CAP
Definition: M4521.h:11260

EADC_T::STATUS2
__IO uint32_t STATUS2
Definition: M4521.h:738

WWDT_T::CNT
__I uint32_t CNT
Definition: M4521.h:13708

PWM_T::CTL0
__IO uint32_t CTL0
Definition: M4521.h:5819

TIMER_T::CTL
__IO uint32_t CTL
Definition: M4521.h:11256

PWM_T::WGCTL1
__IO uint32_t WGCTL1
Definition: M4521.h:5846

DSCT_T::NEXT
__IO uint32_t NEXT
Definition: M4521.h:3999

PDMA_T::REQSEL4_7
__IO uint32_t REQSEL4_7
Definition: M4521.h:4351

SYS_T::USBPHY
__IO uint32_t USBPHY
Definition: M4521.h:10323

SYS_INT_T::NMIEN
__IO uint32_t NMIEN
Definition: M4521.h:10979

USBD_T::EPSTS
__I uint32_t EPSTS
Definition: M4521.h:12516

PDMA_T::SCATBA
__IO uint32_t SCATBA
Definition: M4521.h:4344

SPI_T::SSCTL
__IO uint32_t SSCTL
Definition: M4521.h:9311

SYS_T::GPE_MFPH
__IO uint32_t GPE_MFPH
Definition: M4521.h:10333

CLK_T::AHBCLK
__IO uint32_t AHBCLK
Definition: M4521.h:1418

PWM_T::CLKPSC2_3
__IO uint32_t CLKPSC2_3
Definition: M4521.h:5825

PWM_T::FTCBUF0_1
__I uint32_t FTCBUF0_1
Definition: M4521.h:5900

SC_T::TMRCTL1
__IO uint32_t TMRCTL1
Definition: M4521.h:8507

GPIO_T::DOUT
__IO uint32_t DOUT
Definition: M4521.h:2658

SYS_T::GPD_MFPL
__IO uint32_t GPD_MFPL
Definition: M4521.h:10330

USBH_T::HcControl
__IO uint32_t HcControl
Definition: M4521.h:13217

WWDT_T::STATUS
__IO uint32_t STATUS
Definition: M4521.h:13707

SYS_T::PDID
__I uint32_t PDID
Definition: M4521.h:10312

I2C_T::ADDRMSK2
__IO uint32_t ADDRMSK2
Definition: M4521.h:3716

PWM_T::PDMACAP2_3
__I uint32_t PDMACAP2_3
Definition: M4521.h:5891

SYS_T::GPA_MFPL
__IO uint32_t GPA_MFPL
Definition: M4521.h:10324

GPIO_T::INTEN
__IO uint32_t INTEN
Definition: M4521.h:2663

RTC_T::INIT
__IO uint32_t INIT
Definition: M4521.h:7641

PWM_T::PHS2_3
__IO uint32_t PHS2_3
Definition: M4521.h:5840

PWM_T::CLKPSC4_5
__IO uint32_t CLKPSC4_5
Definition: M4521.h:5826

I2C_T::BUSSTS
__IO uint32_t BUSSTS
Definition: M4521.h:3723

USBD_T::STBUFSEG
__IO uint32_t STBUFSEG
Definition: M4521.h:12519

FMC_T::ISPDAT
__IO uint32_t ISPDAT
Definition: M4521.h:2341

SYS_T::SRAM_BISTSTS
__I uint32_t SRAM_BISTSTS
Definition: M4521.h:10337

FMC_T::DFBA
__I uint32_t DFBA
Definition: M4521.h:2344

UART_T::FIFO
__IO uint32_t FIFO
Definition: M4521.h:11889

CLK_T::CDUPB
__IO uint32_t CDUPB
Definition: M4521.h:1436

vu16
volatile unsigned short vu16
Definition: M4521.h:13938

EBI_T::CTL1
__IO uint32_t CTL1
Definition: M4521.h:2003

USBH_T::HcRevision
__I uint32_t HcRevision
Definition: M4521.h:13216

SYS_T::BODCTL
__IO uint32_t BODCTL
Definition: M4521.h:10318

TIMER_T::EXTCTL
__IO uint32_t EXTCTL
Definition: M4521.h:11261

EADC_T::STATUS3
__I uint32_t STATUS3
Definition: M4521.h:739

USBH_T::HcDoneHead
__IO uint32_t HcDoneHead
Definition: M4521.h:13228

USBD_T::FADDR
__IO uint32_t FADDR
Definition: M4521.h:12515

UART_T::MODEM
__IO uint32_t MODEM
Definition: M4521.h:11891

UART_T::MODEMSTS
__IO uint32_t MODEMSTS
Definition: M4521.h:11892

USBD_EP_T::BUFSEG
__IO uint32_t BUFSEG
Definition: M4521.h:12275

USBH_T::HcPeriodCurrentED
__IO uint32_t HcPeriodCurrentED
Definition: M4521.h:13223

RTC_T::LEAPYEAR
__I uint32_t LEAPYEAR
Definition: M4521.h:7650

PWM_T::FTCBUF2_3
__I uint32_t FTCBUF2_3
Definition: M4521.h:5901

SYS_T::IRCTCTL
__IO uint32_t IRCTCTL
Definition: M4521.h:10339

PDMA_T::ABTSTS
__IO uint32_t ABTSTS
Definition: M4521.h:4337

I2C_T::ADDRMSK0
__IO uint32_t ADDRMSK0
Definition: M4521.h:3714

PWM_T::CAPINEN
__IO uint32_t CAPINEN
Definition: M4521.h:5874

CLK_T::CLKDCTL
__IO uint32_t CLKDCTL
Definition: M4521.h:1434

SPI_T::CLKDIV
__IO uint32_t CLKDIV
Definition: M4521.h:9310

PWM_T::DTCTL4_5
__IO uint32_t DTCTL4_5
Definition: M4521.h:5837

GPIO_DBCTL_T::DBCTL
__IO uint32_t DBCTL
Definition: M4521.h:2711

SYS_T::IRC48MTISTS
__IO uint32_t IRC48MTISTS
Definition: M4521.h:10347

SPI_T::TX
__O uint32_t TX
Definition: M4521.h:9316

USBD_T::VBUSDET
__I uint32_t VBUSDET
Definition: M4521.h:12518

RTC_T::SPRCTL
__IO uint32_t SPRCTL
Definition: M4521.h:7656

SC_T::INTSTS
__IO uint32_t INTSTS
Definition: M4521.h:8503

RTC_T::TALM
__IO uint32_t TALM
Definition: M4521.h:7648

USBH_T::HcBulkHeadED
__IO uint32_t HcBulkHeadED
Definition: M4521.h:13226

SC_T::UARTCTL
__IO uint32_t UARTCTL
Definition: M4521.h:8509

CRC_T::DAT
__IO uint32_t DAT
Definition: M4521.h:1813

USBH_T::HcControlCurrentED
__IO uint32_t HcControlCurrentED
Definition: M4521.h:13225

RTC_T::CALM
__IO uint32_t CALM
Definition: M4521.h:7649

CLK_T::CLKDSTS
__IO uint32_t CLKDSTS
Definition: M4521.h:1435

PWM_T::BNF
__IO uint32_t BNF
Definition: M4521.h:5849

EBI_T::TCTL1
__IO uint32_t TCTL1
Definition: M4521.h:2004

PWM_T::RCAPDAT1
__I uint32_t RCAPDAT1
Definition: M4521.h:5879

EADC_T::STATUS1
__I uint32_t STATUS1
Definition: M4521.h:737

PWM_T::BRKCTL2_3
__IO uint32_t BRKCTL2_3
Definition: M4521.h:5852

WWDT_T::RLDCNT
__O uint32_t RLDCNT
Definition: M4521.h:13705

I2C_T::BUSCTL
__IO uint32_t BUSCTL
Definition: M4521.h:3721

RTC_T::INTEN
__IO uint32_t INTEN
Definition: M4521.h:7651

WDT_T::ALTCTL
__IO uint32_t ALTCTL
Definition: M4521.h:13571

SYS_T::GPC_MFPH
__IO uint32_t GPC_MFPH
Definition: M4521.h:10329

PDMA_T::INTSTS
__IO uint32_t INTSTS
Definition: M4521.h:4336

UART_T::TOUT
__IO uint32_t TOUT
Definition: M4521.h:11895

USBH_T::HcFmRemaining
__I uint32_t HcFmRemaining
Definition: M4521.h:13230

UART_T::IRDA
__IO uint32_t IRDA
Definition: M4521.h:11897

RTC_T::TIME
__IO uint32_t TIME
Definition: M4521.h:7644

USBH_T::HcMiscControl
__IO uint32_t HcMiscControl
Definition: M4521.h:13240

PDMA_T::INTEN
__IO uint32_t INTEN
Definition: M4521.h:4335

CLK_T::CLKSEL2
__IO uint32_t CLKSEL2
Definition: M4521.h:1423

USBH_T::HcFmNumber
__I uint32_t HcFmNumber
Definition: M4521.h:13231

FMC_T::MPSTS
__I uint32_t MPSTS
Definition: M4521.h:2354

I2C_T::ADDRMSK3
__IO uint32_t ADDRMSK3
Definition: M4521.h:3717

USBH_T::HcInterruptStatus
__IO uint32_t HcInterruptStatus
Definition: M4521.h:13219

WWDT_T::CTL
__IO uint32_t CTL
Definition: M4521.h:13706

PWM_T::MSK
__IO uint32_t MSK
Definition: M4521.h:5848

PWM_T::CTL1
__IO uint32_t CTL1
Definition: M4521.h:5820

PWM_T::PHS0_1
__IO uint32_t PHS0_1
Definition: M4521.h:5839

USBH_T::HcRhStatus
__IO uint32_t HcRhStatus
Definition: M4521.h:13236

PWM_T::LOAD
__IO uint32_t LOAD
Definition: M4521.h:5829

RTC_T::CAL
__IO uint32_t CAL
Definition: M4521.h:7645

SYS_T::GPC_MFPL
__IO uint32_t GPC_MFPL
Definition: M4521.h:10328

GPIO_T::INTSRC
__IO uint32_t INTSRC
Definition: M4521.h:2664

CRC_T::CTL
__IO uint32_t CTL
Definition: M4521.h:1812

PDMA_T::TOC2_3
__IO uint32_t TOC2_3
Definition: M4521.h:4346

PWM_T::PDMACAP4_5
__I uint32_t PDMACAP4_5
Definition: M4521.h:5892

PDMA_T::REQSEL0_3
__IO uint32_t REQSEL0_3
Definition: M4521.h:4350

GPIO_T::DRVCTL
__IO uint32_t DRVCTL
Definition: M4521.h:2667

USBD_T::INTSTS
__IO uint32_t INTSTS
Definition: M4521.h:12514

RTC_T::TICK
__IO uint32_t TICK
Definition: M4521.h:7653

SC_T::RXTOUT
__IO uint32_t RXTOUT
Definition: M4521.h:8500

CLK_T::CDLOWB
__IO uint32_t CDLOWB
Definition: M4521.h:1437

USBH_T::HcPeriodicStart
__IO uint32_t HcPeriodicStart
Definition: M4521.h:13232

UART_T::INTSTS
__IO uint32_t INTSTS
Definition: M4521.h:11894

I2C_T::PKTSIZE
__IO uint32_t PKTSIZE
Definition: M4521.h:3724

RTC_T::WEEKDAY
__IO uint32_t WEEKDAY
Definition: M4521.h:7647

PWM_T::CAPIEN
__IO uint32_t CAPIEN
Definition: M4521.h:5894

SYS_T::GPD_MFPH
__IO uint32_t GPD_MFPH
Definition: M4521.h:10331

EADC_T::SWTRG
__O uint32_t SWTRG
Definition: M4521.h:728

PWM_T::POEN
__IO uint32_t POEN
Definition: M4521.h:5855

WDT_T::CTL
__IO uint32_t CTL
Definition: M4521.h:13570

DSCT_T::CTL
__IO uint32_t CTL
Definition: M4521.h:3996

SC_T::TMRDAT1_2
__I uint32_t TMRDAT1_2
Definition: M4521.h:8511

PDMA_T::CHCTL
__IO uint32_t CHCTL
Definition: M4521.h:4329

PWM_T::PDMACTL
__IO uint32_t PDMACTL
Definition: M4521.h:5889

I2C_T::STATUS
__I uint32_t STATUS
Definition: M4521.h:3708

SYS_T::IPRST0
__IO uint32_t IPRST0
Definition: M4521.h:10314

SC_T::EGT
__IO uint32_t EGT
Definition: M4521.h:8499

PWM_T::STATUS
__IO uint32_t STATUS
Definition: M4521.h:5872

PWM_T::FCAPDAT4
__I uint32_t FCAPDAT4
Definition: M4521.h:5886

USBH_T::HcInterruptEnable
__IO uint32_t HcInterruptEnable
Definition: M4521.h:13220

PWM_T::FTCMPDAT0_1
__IO uint32_t FTCMPDAT0_1
Definition: M4521.h:5865

PWM_T::CAPCTL
__IO uint32_t CAPCTL
Definition: M4521.h:5875

GPIO_T::SMTEN
__IO uint32_t SMTEN
Definition: M4521.h:2665

FMC_T::ISPCTL
__IO uint32_t ISPCTL
Definition: M4521.h:2339

USBH_T::HcRhDescriptorA
__IO uint32_t HcRhDescriptorA
Definition: M4521.h:13234

PWM_T::FAILBRK
__IO uint32_t FAILBRK
Definition: M4521.h:5850

vu8
volatile unsigned char vu8
Definition: M4521.h:13936

PWM_T::BRKCTL0_1
__IO uint32_t BRKCTL0_1
Definition: M4521.h:5851

PWM_T::EADCTS0
__IO uint32_t EADCTS0
Definition: M4521.h:5863

SYS_T::GPF_MFPL
__IO uint32_t GPF_MFPL
Definition: M4521.h:10334

CLK_T::CLKSEL3
__IO uint32_t CLKSEL3
Definition: M4521.h:1424

CLK_T::PLLCTL
__IO uint32_t PLLCTL
Definition: M4521.h:1428

I2C_T::WKSTS
__IO uint32_t WKSTS
Definition: M4521.h:3720

SYS_T::GPB_MFPL
__IO uint32_t GPB_MFPL
Definition: M4521.h:10326

PWM_T::BRKCTL4_5
__IO uint32_t BRKCTL4_5
Definition: M4521.h:5853

USBD_T::ATTR
__IO uint32_t ATTR
Definition: M4521.h:12517

PWM_T::PDMACAP0_1
__I uint32_t PDMACAP0_1
Definition: M4521.h:5890

USBH_T::HcCommandStatus
__IO uint32_t HcCommandStatus
Definition: M4521.h:13218

SYS_T::IPRST1
__IO uint32_t IPRST1
Definition: M4521.h:10315

DSCT_T::DA
__IO uint32_t DA
Definition: M4521.h:3998

UART_T::LINE
__IO uint32_t LINE
Definition: M4521.h:11890

I2C_T::WKCTL
__IO uint32_t WKCTL
Definition: M4521.h:3719

PWM_T::RCAPDAT0
__I uint32_t RCAPDAT0
Definition: M4521.h:5877

USBH_T::HcControlHeadED
__IO uint32_t HcControlHeadED
Definition: M4521.h:13224

PWM_T::PHS4_5
__IO uint32_t PHS4_5
Definition: M4521.h:5841

PWM_T::SWSYNC
__IO uint32_t SWSYNC
Definition: M4521.h:5822

i2c.h
M4521 I2C Driver Header File.

pdma.h
M4521 PDMA driver header file.

pwm.h
M4521 PWM driver header file.

rtc.h
M4521 RTC driver header file.

sc.h
M4521 Smartcard (SC) driver header file.

scuart.h

spi.h
M4521 SPI driver header file.

CLK_T
Definition: M4521.h:957

CRC_T
Definition: M4521.h:1738

DSCT_T
Definition: M4521.h:3916

EADC_T
Definition: M4521.h:177

EBI_T
Definition: M4521.h:1872

FMC_T
Definition: M4521.h:2099

GPIO_DBCTL_T
Definition: M4521.h:2675

GPIO_T
Definition: M4521.h:2472

I2C_T
Definition: M4521.h:3339

PDMA_T
Definition: M4521.h:4007

PWM_T
Definition: M4521.h:4525

RTC_T
Definition: M4521.h:7327

SC_T
Definition: M4521.h:7895

SPI_T
Definition: M4521.h:8846

SYS_INT_T
Definition: M4521.h:10865

SYS_T
Definition: M4521.h:9636

TIMER_T
Definition: M4521.h:11089

UART_T
Definition: M4521.h:11366

USBD_EP_T
USBD endpoints register.
Definition: M4521.h:12206

USBD_T
Definition: M4521.h:12287

USBH_T
Definition: M4521.h:12702

WDT_T
Definition: M4521.h:13484

WWDT_T
Definition: M4521.h:13627

sys.h
M4521 SYS Header File.

system_M4521.h

timer.h
M4521 Timer driver header file.

uart.h
M4521 UART driver header file.

usbd.h
M4521 USB driver header file.

wdt.h
M4521 WDT driver header file.

wwdt.h
M4521 WWDT driver header file.