; generated by Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\uart.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\uart.d --cpu=Cortex-M0 --apcs=interwork -Otime --diag_suppress=9931 -I..\..\..\..\Library\CMSIS\Include -I..\..\..\..\Library\Device\Nuvoton\M0A21\Include -I..\..\..\..\Library\StdDriver\inc -I..\ -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -D__MICROLIB -D__UVISION_VERSION=538 --omf_browse=.\obj\uart.crf ..\..\..\..\Library\StdDriver\src\uart.c]
                          THUMB

                          AREA ||i.UART_ClearIntFlag||, CODE, READONLY, ALIGN=2

                  UART_ClearIntFlag PROC
;;;41     
;;;42     void UART_ClearIntFlag(UART_T *uart , uint32_t u32InterruptFlag)
000000  01ca              LSLS     r2,r1,#7
;;;43     {
000002  d502              BPL      |L1.10|
;;;44     
;;;45     
;;;46         if (u32InterruptFlag & UART_INTSTS_SWBEINT_Msk)   /* Clear Bit Error Detection Interrupt */
;;;47         {
;;;48             uart->INTSTS = UART_INTSTS_SWBEIF_Msk;
000004  2201              MOVS     r2,#1
000006  0412              LSLS     r2,r2,#16
000008  61c2              STR      r2,[r0,#0x1c]
                  |L1.10|
;;;49         }
;;;50     
;;;51         if (u32InterruptFlag & UART_INTSTS_RLSINT_Msk)   /* Clear Receive Line Status Interrupt */
00000a  054a              LSLS     r2,r1,#21
00000c  d503              BPL      |L1.22|
;;;52         {
;;;53             uart->FIFOSTS = UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_PEF_Msk;
00000e  2270              MOVS     r2,#0x70
000010  6182              STR      r2,[r0,#0x18]
;;;54             uart->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk;
000012  2208              MOVS     r2,#8
000014  6182              STR      r2,[r0,#0x18]
                  |L1.22|
;;;55         }
;;;56     
;;;57         if (u32InterruptFlag & UART_INTSTS_MODEMINT_Msk)   /* Clear Modem Status Interrupt */
000016  050a              LSLS     r2,r1,#20
000018  d503              BPL      |L1.34|
;;;58         {
;;;59             uart->MODEMSTS |= UART_MODEMSTS_CTSDETF_Msk;
00001a  6942              LDR      r2,[r0,#0x14]
00001c  2301              MOVS     r3,#1
00001e  431a              ORRS     r2,r2,r3
000020  6142              STR      r2,[r0,#0x14]
                  |L1.34|
;;;60         }
;;;61     
;;;62         if (u32InterruptFlag & UART_INTSTS_BUFERRINT_Msk)   /* Clear Buffer Error Interrupt */
000022  048a              LSLS     r2,r1,#18
000024  d501              BPL      |L1.42|
;;;63         {
;;;64             uart->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk | UART_FIFOSTS_TXOVIF_Msk;
000026  4a08              LDR      r2,|L1.72|
000028  6182              STR      r2,[r0,#0x18]
                  |L1.42|
;;;65         }
;;;66     
;;;67         if (u32InterruptFlag & UART_INTSTS_WKINT_Msk)   /* Clear Wake-up Interrupt */
00002a  044a              LSLS     r2,r1,#17
00002c  d504              BPL      |L1.56|
;;;68         {
;;;69             uart->LINWKCTL = UART_LINWKCTL_LINWKF_Msk;
00002e  2201              MOVS     r2,#1
000030  0752              LSLS     r2,r2,#29
000032  6502              STR      r2,[r0,#0x50]
;;;70             uart->WKSTS = UART_WKSTS_CTSWKF_Msk  | UART_WKSTS_DATWKF_Msk  |
000034  221f              MOVS     r2,#0x1f
000036  6442              STR      r2,[r0,#0x44]
                  |L1.56|
;;;71                           UART_WKSTS_RFRTWKF_Msk | UART_WKSTS_RS485WKF_Msk |
;;;72                           UART_WKSTS_TOUTWKF_Msk;
;;;73         }
;;;74     
;;;75         if(u32InterruptFlag & UART_INTSTS_LININT_Msk)       /* Clear LIN Bus Interrupt */
000038  0409              LSLS     r1,r1,#16
00003a  d503              BPL      |L1.68|
;;;76         {
;;;77             uart->INTSTS = UART_INTSTS_LINIF_Msk;
00003c  2180              MOVS     r1,#0x80
00003e  61c1              STR      r1,[r0,#0x1c]
;;;78             uart->LINSTS = UART_LINSTS_BITEF_Msk    | UART_LINSTS_BRKDETF_Msk  |
000040  4902              LDR      r1,|L1.76|
000042  6381              STR      r1,[r0,#0x38]
                  |L1.68|
;;;79                            UART_LINSTS_RTOUTF_Msk | UART_INTSTS_LINIF_Msk |        
;;;80                            UART_LINSTS_SLVSYNCF_Msk | UART_LINSTS_SLVIDPEF_Msk |
;;;81                            UART_LINSTS_SLVHEF_Msk   | UART_LINSTS_SLVHDETF_Msk ;
;;;82         }
;;;83     
;;;84     }
000044  4770              BX       lr
;;;85     
                          ENDP

000046  0000              DCW      0x0000
                  |L1.72|
                          DCD      0x01000001
                  |L1.76|
                          DCD      0x000003af

                          AREA ||i.UART_Close||, CODE, READONLY, ALIGN=1

                  UART_Close PROC
;;;95      */
;;;96     void UART_Close(UART_T *uart)
000000  2100              MOVS     r1,#0
;;;97     {
;;;98         uart->INTEN = 0ul;
000002  6041              STR      r1,[r0,#4]
;;;99     }
000004  4770              BX       lr
;;;100    
                          ENDP


                          AREA ||i.UART_DisableFlowCtrl||, CODE, READONLY, ALIGN=1

                  UART_DisableFlowCtrl PROC
;;;110     */
;;;111    void UART_DisableFlowCtrl(UART_T *uart)
000000  6841              LDR      r1,[r0,#4]
;;;112    {
;;;113        uart->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
000002  2203              MOVS     r2,#3
000004  0312              LSLS     r2,r2,#12
000006  4391              BICS     r1,r1,r2
000008  6041              STR      r1,[r0,#4]
;;;114    }
00000a  4770              BX       lr
;;;115    
                          ENDP


                          AREA ||i.UART_DisableInt||, CODE, READONLY, ALIGN=1

                  UART_DisableInt PROC
;;;135     */
;;;136    void UART_DisableInt(UART_T  *uart, uint32_t u32InterruptFlag)
000000  6842              LDR      r2,[r0,#4]
;;;137    {
;;;138        /* Disable UART specified interrupt */
;;;139        UART_DISABLE_INT(uart, u32InterruptFlag);
000002  438a              BICS     r2,r2,r1
000004  6042              STR      r2,[r0,#4]
;;;140    
;;;141    }
000006  4770              BX       lr
;;;142    
                          ENDP


                          AREA ||i.UART_EnableFlowCtrl||, CODE, READONLY, ALIGN=1

                  UART_EnableFlowCtrl PROC
;;;152     */
;;;153    void UART_EnableFlowCtrl(UART_T *uart)
000000  6901              LDR      r1,[r0,#0x10]
;;;154    {
;;;155        /* Set RTS pin output is low level active */
;;;156        uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
000002  2201              MOVS     r2,#1
000004  0252              LSLS     r2,r2,#9
000006  4311              ORRS     r1,r1,r2
000008  6101              STR      r1,[r0,#0x10]
;;;157    
;;;158        /* Set CTS pin input is low level active */
;;;159        uart->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
00000a  6941              LDR      r1,[r0,#0x14]
00000c  1052              ASRS     r2,r2,#1
00000e  4311              ORRS     r1,r1,r2
000010  6141              STR      r1,[r0,#0x14]
;;;160    
;;;161        /* Set RTS and CTS auto flow control enable */
;;;162        uart->INTEN |= UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk;
000012  6841              LDR      r1,[r0,#4]
000014  2203              MOVS     r2,#3
000016  0312              LSLS     r2,r2,#12
000018  4311              ORRS     r1,r1,r2
00001a  6041              STR      r1,[r0,#4]
;;;163    }
00001c  4770              BX       lr
;;;164    
                          ENDP


                          AREA ||i.UART_EnableInt||, CODE, READONLY, ALIGN=1

                  UART_EnableInt PROC
;;;184     */
;;;185    void UART_EnableInt(UART_T  *uart, uint32_t u32InterruptFlag)
000000  6842              LDR      r2,[r0,#4]
;;;186    {
;;;187        /* Enable UART specified interrupt */
;;;188        UART_ENABLE_INT(uart, u32InterruptFlag);
000002  430a              ORRS     r2,r2,r1
000004  6042              STR      r2,[r0,#4]
;;;189    
;;;190    }
000006  4770              BX       lr
;;;191    
                          ENDP


                          AREA ||i.UART_Open||, CODE, READONLY, ALIGN=2

                  UART_Open PROC
;;;202     */
;;;203    void UART_Open(UART_T *uart, uint32_t u32baudrate)
000000  b5f3              PUSH     {r0,r1,r4-r7,lr}
;;;204    {
000002  4604              MOV      r4,r0
;;;205        uint32_t u32UartClkSrcSel = 0ul, u32UartClkDivNum = 0ul;
;;;206        uint32_t u32ClkTbl[6ul] = {__HXT, 0ul, __LXT, __HIRC, 0ul, __LIRC};
000004  482a              LDR      r0,|L7.176|
000006  b087              SUB      sp,sp,#0x1c           ;204
000008  c88e              LDM      r0!,{r1-r3,r7}
00000a  9703              STR      r7,[sp,#0xc]
00000c  9302              STR      r3,[sp,#8]
00000e  9201              STR      r2,[sp,#4]
000010  9100              STR      r1,[sp,#0]
000012  6841              LDR      r1,[r0,#4]  ; <Data1>
000014  6800              LDR      r0,[r0,#0]  ; <Data1>
;;;207        uint32_t u32Baud_Div = 0ul;
;;;208    
;;;209    
;;;210        if (uart == (UART_T *)UART0)
000016  9105              STR      r1,[sp,#0x14]
000018  2500              MOVS     r5,#0                 ;205
00001a  9004              STR      r0,[sp,#0x10]
00001c  4925              LDR      r1,|L7.180|
;;;211        {
;;;212            /* Get UART clock source selection */
;;;213            u32UartClkSrcSel = ((uint32_t)(CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk)) >> CLK_CLKSEL1_UART0SEL_Pos;
00001e  4826              LDR      r0,|L7.184|
000020  462e              MOV      r6,r5                 ;205
000022  428c              CMP      r4,r1                 ;210
000024  d106              BNE      |L7.52|
000026  6942              LDR      r2,[r0,#0x14]
;;;214            /* Get UART clock divider number */
;;;215            u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos;
000028  6a00              LDR      r0,[r0,#0x20]
;;;216        }
;;;217        else if (uart == (UART_T *)UART1)
;;;218        {
;;;219            /* Get UART clock source selection */
;;;220            u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos;
;;;221            /* Get UART clock divider number */
;;;222            u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos;
;;;223        }
;;;224    
;;;225        /* Select UART function */
;;;226        uart->FUNCSEL = UART_FUNCSEL_UART;
;;;227    
;;;228        /* Set UART line configuration */
;;;229        uart->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;
;;;230    
;;;231        /* Set UART Rx and RTS trigger level */
;;;232        uart->FIFO &= ~(UART_FIFO_RFITL_Msk | UART_FIFO_RTSTRGLV_Msk);
;;;233    
;;;234        /* Get PCLK clock frequency if UART clock source selection is PCLK */
;;;235        if (u32UartClkSrcSel == 4ul)
;;;236        {
;;;237            /* UART Port as UART0 */
;;;238            if (uart == (UART_T *)UART0)
;;;239            {
;;;240                u32ClkTbl[u32UartClkSrcSel] =  CLK_GetPCLK0Freq();
;;;241            }
;;;242            else     /* UART Port as UART1*/
;;;243            {
;;;244                u32ClkTbl[u32UartClkSrcSel] =  CLK_GetPCLK1Freq();
;;;245            }
;;;246    
;;;247        }
;;;248    
;;;249        /* Set UART baud rate */
;;;250        if (u32baudrate != 0ul)
;;;251        {
;;;252            u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate);
;;;253    
;;;254            if (u32Baud_Div > 0xFFFFul)
;;;255            {
;;;256                uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate));
;;;257            }
;;;258            else
;;;259            {
;;;260                uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
;;;261            }
;;;262        }
;;;263    }
00002a  0152              LSLS     r2,r2,#5
00002c  0f55              LSRS     r5,r2,#29
00002e  0500              LSLS     r0,r0,#20
000030  0f06              LSRS     r6,r0,#28
000032  e008              B        |L7.70|
                  |L7.52|
000034  4a21              LDR      r2,|L7.188|
000036  4294              CMP      r4,r2                 ;217
000038  d105              BNE      |L7.70|
00003a  6942              LDR      r2,[r0,#0x14]         ;220
00003c  6a00              LDR      r0,[r0,#0x20]         ;222
00003e  0052              LSLS     r2,r2,#1
000040  0f55              LSRS     r5,r2,#29
000042  0400              LSLS     r0,r0,#16             ;222
000044  0f06              LSRS     r6,r0,#28             ;222
                  |L7.70|
000046  2000              MOVS     r0,#0                 ;226
000048  6320              STR      r0,[r4,#0x30]         ;226
00004a  2003              MOVS     r0,#3                 ;229
00004c  60e0              STR      r0,[r4,#0xc]          ;229
00004e  68a0              LDR      r0,[r4,#8]            ;232
000050  4a1b              LDR      r2,|L7.192|
000052  4010              ANDS     r0,r0,r2              ;232
000054  60a0              STR      r0,[r4,#8]            ;232
000056  466f              MOV      r7,sp                 ;206
000058  2d04              CMP      r5,#4                 ;235
00005a  d107              BNE      |L7.108|
00005c  428c              CMP      r4,r1                 ;238
00005e  d102              BNE      |L7.102|
000060  f7fffffe          BL       CLK_GetPCLK0Freq
000064  e001              B        |L7.106|
                  |L7.102|
000066  f7fffffe          BL       CLK_GetPCLK1Freq
                  |L7.106|
00006a  9004              STR      r0,[sp,#0x10]         ;240
                  |L7.108|
00006c  9808              LDR      r0,[sp,#0x20]         ;250
00006e  2800              CMP      r0,#0                 ;250
000070  d01c              BEQ      |L7.172|
000072  00a8              LSLS     r0,r5,#2              ;252
000074  5838              LDR      r0,[r7,r0]            ;252
000076  1c71              ADDS     r1,r6,#1              ;252
000078  f7fffffe          BL       __aeabi_uidivmod
00007c  9908              LDR      r1,[sp,#0x20]         ;252
00007e  4605              MOV      r5,r0                 ;252
000080  0849              LSRS     r1,r1,#1              ;252
000082  1840              ADDS     r0,r0,r1              ;252
000084  9908              LDR      r1,[sp,#0x20]         ;252
000086  f7fffffe          BL       __aeabi_uidivmod
00008a  490e              LDR      r1,|L7.196|
00008c  1e80              SUBS     r0,r0,#2              ;254
00008e  4288              CMP      r0,r1                 ;254
000090  d908              BLS      |L7.164|
000092  9908              LDR      r1,[sp,#0x20]         ;256
000094  00c9              LSLS     r1,r1,#3              ;256
000096  1868              ADDS     r0,r5,r1              ;256
000098  9908              LDR      r1,[sp,#0x20]         ;256
00009a  f7fffffe          BL       __aeabi_uidivmod
00009e  0900              LSRS     r0,r0,#4              ;256
0000a0  1e80              SUBS     r0,r0,#2              ;256
0000a2  e002              B        |L7.170|
                  |L7.164|
0000a4  2103              MOVS     r1,#3                 ;260
0000a6  0709              LSLS     r1,r1,#28             ;260
0000a8  4308              ORRS     r0,r0,r1              ;260
                  |L7.170|
0000aa  6260              STR      r0,[r4,#0x24]         ;260
                  |L7.172|
0000ac  b009              ADD      sp,sp,#0x24
0000ae  bdf0              POP      {r4-r7,pc}
;;;264    
                          ENDP

                  |L7.176|
                          DCD      ||.constdata||
                  |L7.180|
                          DCD      0x40070000
                  |L7.184|
                          DCD      0x40000200
                  |L7.188|
                          DCD      0x40071000
                  |L7.192|
                          DCD      0xfff0ff0f
                  |L7.196|
                          DCD      0x0000ffff

                          AREA ||i.UART_Read||, CODE, READONLY, ALIGN=1

                  UART_Read PROC
;;;276     */
;;;277    uint32_t UART_Read(UART_T *uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes)
000000  b4f0              PUSH     {r4-r7}
;;;278    {
;;;279        uint32_t  u32Count, u32delayno;
;;;280        uint32_t  u32Exit = 0ul;
000002  2700              MOVS     r7,#0
000004  4604              MOV      r4,r0                 ;278
;;;281    
;;;282        for (u32Count = 0ul; u32Count < u32ReadBytes; u32Count++)
000006  4638              MOV      r0,r7
000008  2a00              CMP      r2,#0
00000a  d912              BLS      |L8.50|
;;;283        {
;;;284            u32delayno = 0ul;
;;;285    
;;;286            while (uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)   /* Check RX empty => failed */
;;;287            {
;;;288                u32delayno++;
;;;289    
;;;290                if (u32delayno >= 0x40000000ul)
00000c  2601              MOVS     r6,#1
00000e  07b6              LSLS     r6,r6,#30
                  |L8.16|
000010  69a5              LDR      r5,[r4,#0x18]         ;286
000012  2300              MOVS     r3,#0                 ;284
000014  046d              LSLS     r5,r5,#17             ;286
000016  d505              BPL      |L8.36|
                  |L8.24|
000018  1c5b              ADDS     r3,r3,#1              ;286
00001a  42b3              CMP      r3,r6
00001c  d209              BCS      |L8.50|
00001e  69a5              LDR      r5,[r4,#0x18]         ;286
000020  046d              LSLS     r5,r5,#17             ;286
000022  d4f9              BMI      |L8.24|
                  |L8.36|
;;;291                {
;;;292                    u32Exit = 1ul;
;;;293                    break;
;;;294                }
;;;295            }
;;;296    
;;;297            if (u32Exit == 1ul)
000024  2f00              CMP      r7,#0
000026  d104              BNE      |L8.50|
;;;298            {
;;;299                break;
;;;300            }
;;;301            else
;;;302            {
;;;303                pu8RxBuf[u32Count] = (uint8_t)uart->DAT; /* Get Data from UART RX  */
000028  6823              LDR      r3,[r4,#0]
00002a  540b              STRB     r3,[r1,r0]
00002c  1c40              ADDS     r0,r0,#1
00002e  4290              CMP      r0,r2                 ;282
000030  d3ee              BCC      |L8.16|
                  |L8.50|
;;;304            }
;;;305        }
;;;306    
;;;307        return u32Count;
;;;308    
;;;309    }
000032  bcf0              POP      {r4-r7}
000034  4770              BX       lr
;;;310    
                          ENDP


                          AREA ||i.UART_SelectIrDAMode||, CODE, READONLY, ALIGN=2

                  UART_SelectIrDAMode PROC
;;;426     */
;;;427    void UART_SelectIrDAMode(UART_T *uart, uint32_t u32Buadrate, uint32_t u32Direction)
000000  b5f7              PUSH     {r0-r2,r4-r7,lr}
;;;428    {
000002  4604              MOV      r4,r0
;;;429        uint32_t u32UartClkSrcSel = 0ul, u32UartClkDivNum = 0ul;
;;;430        uint32_t u32ClkTbl[6ul] = {__HXT, 0ul, __LXT, __HIRC, 0ul, __LIRC};
000004  482a              LDR      r0,|L9.176|
000006  b086              SUB      sp,sp,#0x18           ;428
000008  4601              MOV      r1,r0
00000a  3130              ADDS     r1,r1,#0x30
00000c  c98e              LDM      r1,{r1-r3,r7}
00000e  9703              STR      r7,[sp,#0xc]
000010  9302              STR      r3,[sp,#8]
000012  9201              STR      r2,[sp,#4]
000014  9100              STR      r1,[sp,#0]
000016  6c41              LDR      r1,[r0,#0x44]  ; <Data5>
000018  2500              MOVS     r5,#0                 ;429
00001a  6c00              LDR      r0,[r0,#0x40]  ; <Data5>
;;;431        uint32_t u32Baud_Div;
;;;432    
;;;433        /* Select IrDA function mode */
;;;434        uart->FUNCSEL = UART_FUNCSEL_IrDA;
00001c  2702              MOVS     r7,#2
00001e  9105              STR      r1,[sp,#0x14]
000020  9004              STR      r0,[sp,#0x10]
000022  462e              MOV      r6,r5                 ;429
000024  6327              STR      r7,[r4,#0x30]
;;;435    
;;;436    
;;;437        if (uart == UART0)
000026  4923              LDR      r1,|L9.180|
;;;438        {
;;;439            /* Get UART clock source selection */
;;;440            u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos;
000028  4823              LDR      r0,|L9.184|
00002a  428c              CMP      r4,r1                 ;437
00002c  d106              BNE      |L9.60|
00002e  6942              LDR      r2,[r0,#0x14]
;;;441            /* Get UART clock divider number */
;;;442            u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos;
000030  6a00              LDR      r0,[r0,#0x20]
;;;443        }
;;;444        else if (uart == UART1)
;;;445        {
;;;446            /* Get UART clock source selection */
;;;447            u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos;
;;;448            /* Get UART clock divider number */
;;;449            u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos;
;;;450        }
;;;451    
;;;452    
;;;453        /* Get PCLK clock frequency if UART clock source selection is PCLK */
;;;454        if (u32UartClkSrcSel == 4ul)
;;;455        {
;;;456            if (uart == (UART_T *)UART0)
;;;457            {
;;;458                u32ClkTbl[u32UartClkSrcSel] =  CLK_GetPCLK0Freq();
;;;459            }
;;;460            else     /* UART Port as UART1*/
;;;461            {
;;;462                u32ClkTbl[u32UartClkSrcSel] =  CLK_GetPCLK1Freq();
;;;463            }
;;;464        }
;;;465    
;;;466    
;;;467        /* Set UART IrDA baud rate in mode 0 */
;;;468        if (u32Buadrate != 0ul)
;;;469        {
;;;470            u32Baud_Div = UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32Buadrate);
;;;471    
;;;472            if (u32Baud_Div < 0xFFFFul)
;;;473            {
;;;474                uart->BAUD = (UART_BAUD_MODE0 | u32Baud_Div);
;;;475            }
;;;476            else
;;;477            {
;;;478            }
;;;479        }
;;;480    
;;;481        /* Configure IrDA relative settings */
;;;482        if (u32Direction == UART_IRDA_RXEN)
;;;483        {
;;;484            uart->IRDA |= UART_IRDA_RXINV_Msk;     /*Rx signal is inverse*/
;;;485            uart->IRDA &= ~UART_IRDA_TXEN_Msk;
;;;486        }
;;;487        else
;;;488        {
;;;489            uart->IRDA &= ~UART_IRDA_TXINV_Msk;    /*Tx signal is not inverse*/
;;;490            uart->IRDA |= UART_IRDA_TXEN_Msk;
;;;491        }
;;;492    
;;;493    }
000032  0152              LSLS     r2,r2,#5
000034  0f55              LSRS     r5,r2,#29
000036  0500              LSLS     r0,r0,#20
000038  0f06              LSRS     r6,r0,#28
00003a  e008              B        |L9.78|
                  |L9.60|
00003c  4a1f              LDR      r2,|L9.188|
00003e  4294              CMP      r4,r2                 ;444
000040  d10f              BNE      |L9.98|
000042  6942              LDR      r2,[r0,#0x14]         ;447
000044  6a00              LDR      r0,[r0,#0x20]         ;449
000046  0052              LSLS     r2,r2,#1
000048  0f55              LSRS     r5,r2,#29
00004a  0400              LSLS     r0,r0,#16             ;449
00004c  0f06              LSRS     r6,r0,#28             ;449
                  |L9.78|
00004e  2d04              CMP      r5,#4                 ;454
000050  d107              BNE      |L9.98|
000052  428c              CMP      r4,r1                 ;456
000054  d102              BNE      |L9.92|
000056  f7fffffe          BL       CLK_GetPCLK0Freq
00005a  e001              B        |L9.96|
                  |L9.92|
00005c  f7fffffe          BL       CLK_GetPCLK1Freq
                  |L9.96|
000060  9004              STR      r0,[sp,#0x10]         ;458
                  |L9.98|
000062  9807              LDR      r0,[sp,#0x1c]         ;468
000064  2800              CMP      r0,#0                 ;468
000066  d011              BEQ      |L9.140|
000068  00a9              LSLS     r1,r5,#2              ;470
00006a  4668              MOV      r0,sp                 ;470
00006c  5840              LDR      r0,[r0,r1]            ;470
00006e  1c71              ADDS     r1,r6,#1              ;470
000070  f7fffffe          BL       __aeabi_uidivmod
000074  9907              LDR      r1,[sp,#0x1c]         ;470
000076  00c9              LSLS     r1,r1,#3              ;470
000078  1840              ADDS     r0,r0,r1              ;470
00007a  9907              LDR      r1,[sp,#0x1c]         ;470
00007c  f7fffffe          BL       __aeabi_uidivmod
000080  0900              LSRS     r0,r0,#4              ;470
000082  490f              LDR      r1,|L9.192|
000084  1e80              SUBS     r0,r0,#2              ;472
000086  4288              CMP      r0,r1                 ;472
000088  d200              BCS      |L9.140|
00008a  6260              STR      r0,[r4,#0x24]         ;474
                  |L9.140|
00008c  9808              LDR      r0,[sp,#0x20]         ;482
00008e  2800              CMP      r0,#0                 ;482
000090  6aa0              LDR      r0,[r4,#0x28]         ;489
000092  d007              BEQ      |L9.164|
000094  2120              MOVS     r1,#0x20              ;489
000096  4388              BICS     r0,r0,r1              ;489
000098  62a0              STR      r0,[r4,#0x28]         ;489
00009a  6aa0              LDR      r0,[r4,#0x28]         ;490
00009c  4338              ORRS     r0,r0,r7              ;490
                  |L9.158|
00009e  62a0              STR      r0,[r4,#0x28]         ;485
0000a0  b009              ADD      sp,sp,#0x24
0000a2  bdf0              POP      {r4-r7,pc}
                  |L9.164|
0000a4  2140              MOVS     r1,#0x40              ;484
0000a6  4308              ORRS     r0,r0,r1              ;484
0000a8  62a0              STR      r0,[r4,#0x28]         ;484
0000aa  6aa0              LDR      r0,[r4,#0x28]         ;485
0000ac  43b8              BICS     r0,r0,r7              ;485
0000ae  e7f6              B        |L9.158|
;;;494    
                          ENDP

                  |L9.176|
                          DCD      ||.constdata||
                  |L9.180|
                          DCD      0x40070000
                  |L9.184|
                          DCD      0x40000200
                  |L9.188|
                          DCD      0x40071000
                  |L9.192|
                          DCD      0x0000ffff

                          AREA ||i.UART_SelectLINMode||, CODE, READONLY, ALIGN=1

                  UART_SelectLINMode PROC
;;;533     */
;;;534    void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength)
000000  b410              PUSH     {r4}
;;;535    {
;;;536        /* Select LIN function mode */
;;;537        uart->FUNCSEL = UART_FUNCSEL_LIN;
000002  2301              MOVS     r3,#1
000004  6303              STR      r3,[r0,#0x30]
;;;538    
;;;539        /* Select LIN function setting : Tx enable, Rx enable and break field length */
;;;540        uart->ALTCTL &= ~(UART_ALTCTL_LINTXEN_Msk | UART_ALTCTL_LINRXEN_Msk | UART_ALTCTL_BRKFL_Msk);
000006  6ac3              LDR      r3,[r0,#0x2c]
000008  24cf              MOVS     r4,#0xcf
00000a  43a3              BICS     r3,r3,r4
00000c  62c3              STR      r3,[r0,#0x2c]
;;;541        uart->ALTCTL |= (u32Mode | (u32BreakLength << UART_ALTCTL_BRKFL_Pos));
00000e  6ac3              LDR      r3,[r0,#0x2c]
000010  4311              ORRS     r1,r1,r2
000012  430b              ORRS     r3,r3,r1
000014  62c3              STR      r3,[r0,#0x2c]
;;;542    }
000016  bc10              POP      {r4}
000018  4770              BX       lr
;;;543    
                          ENDP


                          AREA ||i.UART_SelectRS485Mode||, CODE, READONLY, ALIGN=2

                  UART_SelectRS485Mode PROC
;;;509     */
;;;510    void UART_SelectRS485Mode(UART_T *uart, uint32_t u32Mode, uint32_t u32Addr)
000000  b410              PUSH     {r4}
;;;511    {
;;;512        /* Select UART RS485 function mode */
;;;513        uart->FUNCSEL = UART_FUNCSEL_RS485;
000002  2303              MOVS     r3,#3
000004  6303              STR      r3,[r0,#0x30]
;;;514    
;;;515        /* Set RS485 configuration */
;;;516        uart->ALTCTL &= ~(UART_ALTCTL_RS485NMM_Msk | UART_ALTCTL_RS485AUD_Msk | UART_ALTCTL_RS485AAD_Msk | UART_ALTCTL_ADDRMV_Msk);
000006  6ac3              LDR      r3,[r0,#0x2c]
000008  4c04              LDR      r4,|L11.28|
00000a  4023              ANDS     r3,r3,r4
00000c  62c3              STR      r3,[r0,#0x2c]
;;;517        uart->ALTCTL |= (u32Mode | (u32Addr << UART_ALTCTL_ADDRMV_Pos));
00000e  6ac3              LDR      r3,[r0,#0x2c]
000010  0612              LSLS     r2,r2,#24
000012  430a              ORRS     r2,r2,r1
000014  4313              ORRS     r3,r3,r2
000016  62c3              STR      r3,[r0,#0x2c]
;;;518    }
000018  bc10              POP      {r4}
00001a  4770              BX       lr
;;;519    
                          ENDP

                  |L11.28|
                          DCD      0x00fff8ff

                          AREA ||i.UART_SelectSingleWireMode||, CODE, READONLY, ALIGN=1

                  UART_SelectSingleWireMode PROC
;;;596     */
;;;597    void UART_SelectSingleWireMode(UART_T *uart)
000000  6b01              LDR      r1,[r0,#0x30]
;;;598    {
;;;599    
;;;600        /* Select UART SingleWire function mode */
;;;601        uart->FUNCSEL = ((uart->FUNCSEL & (~UART_FUNCSEL_FUNCSEL_Msk)) | UART_FUNCSEL_SINGLE_WIRE);
000002  08c9              LSRS     r1,r1,#3
000004  00c9              LSLS     r1,r1,#3
000006  1d09              ADDS     r1,r1,#4
000008  6301              STR      r1,[r0,#0x30]
;;;602    
;;;603    }
00000a  4770              BX       lr
;;;604    
                          ENDP


                          AREA ||i.UART_SetLine_Config||, CODE, READONLY, ALIGN=2

                  UART_SetLine_Config PROC
;;;337     */
;;;338    void UART_SetLine_Config(UART_T *uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t  u32stop_bits)
000000  b5ff              PUSH     {r0-r7,lr}
;;;339    {
;;;340        uint32_t u32UartClkSrcSel = 0ul, u32UartClkDivNum = 0ul;
;;;341        uint32_t u32ClkTbl[6ul] = {__HXT, 0ul, __LXT, __HIRC, 0, __LIRC};
000002  4a2b              LDR      r2,|L13.176|
000004  4604              MOV      r4,r0                 ;339
000006  4610              MOV      r0,r2
000008  3018              ADDS     r0,r0,#0x18
00000a  c88b              LDM      r0,{r0,r1,r3,r7}
00000c  b087              SUB      sp,sp,#0x1c           ;339
00000e  9703              STR      r7,[sp,#0xc]
000010  9302              STR      r3,[sp,#8]
000012  9101              STR      r1,[sp,#4]
000014  9000              STR      r0,[sp,#0]
000016  6ad1              LDR      r1,[r2,#0x2c]  ; <Data4>
000018  6a90              LDR      r0,[r2,#0x28]  ; <Data4>
;;;342        uint32_t u32Baud_Div = 0ul;
;;;343    
;;;344    
;;;345        if (uart == (UART_T *)UART0)
00001a  9105              STR      r1,[sp,#0x14]
00001c  2500              MOVS     r5,#0                 ;340
00001e  9004              STR      r0,[sp,#0x10]
000020  4924              LDR      r1,|L13.180|
;;;346        {
;;;347            /* Get UART clock source selection */
;;;348            u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART0SEL_Msk) >> CLK_CLKSEL1_UART0SEL_Pos;
000022  4825              LDR      r0,|L13.184|
000024  462e              MOV      r6,r5                 ;340
000026  466f              MOV      r7,sp                 ;341
000028  428c              CMP      r4,r1                 ;345
00002a  d106              BNE      |L13.58|
00002c  6942              LDR      r2,[r0,#0x14]
;;;349            /* Get UART clock divider number */
;;;350            u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART0DIV_Msk) >> CLK_CLKDIV0_UART0DIV_Pos;
00002e  6a00              LDR      r0,[r0,#0x20]
;;;351        }
;;;352        else if (uart == (UART_T *)UART1)
;;;353        {
;;;354            /* Get UART clock source selection */
;;;355            u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos;
;;;356            /* Get UART clock divider number */
;;;357            u32UartClkDivNum = (CLK->CLKDIV0 & CLK_CLKDIV0_UART1DIV_Msk) >> CLK_CLKDIV0_UART1DIV_Pos;
;;;358        }
;;;359    
;;;360        /* Get PCLK clock frequency if UART clock source selection is PCLK */
;;;361        if (u32UartClkSrcSel == 4ul)
;;;362        {
;;;363            if (uart == (UART_T *)UART0)
;;;364            {
;;;365                u32ClkTbl[u32UartClkSrcSel] =  CLK_GetPCLK0Freq();
;;;366            }
;;;367            else     /* UART Port as UART1*/
;;;368            {
;;;369                u32ClkTbl[u32UartClkSrcSel] =  CLK_GetPCLK1Freq();
;;;370            }
;;;371        }
;;;372    
;;;373    
;;;374        /* Set UART baud rate */
;;;375        if (u32baudrate != 0ul)
;;;376        {
;;;377            u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate);
;;;378    
;;;379            if (u32Baud_Div > 0xFFFFul)
;;;380            {
;;;381                uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate));
;;;382            }
;;;383            else
;;;384            {
;;;385                uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
;;;386            }
;;;387        }
;;;388    
;;;389        /* Set UART line configuration */
;;;390        uart->LINE = u32data_width | u32parity | u32stop_bits;
;;;391    }
000030  0152              LSLS     r2,r2,#5
000032  0f55              LSRS     r5,r2,#29
000034  0500              LSLS     r0,r0,#20
000036  0f06              LSRS     r6,r0,#28
000038  e008              B        |L13.76|
                  |L13.58|
00003a  4a20              LDR      r2,|L13.188|
00003c  4294              CMP      r4,r2                 ;352
00003e  d10f              BNE      |L13.96|
000040  6942              LDR      r2,[r0,#0x14]         ;355
000042  6a00              LDR      r0,[r0,#0x20]         ;357
000044  0052              LSLS     r2,r2,#1
000046  0f55              LSRS     r5,r2,#29
000048  0400              LSLS     r0,r0,#16             ;357
00004a  0f06              LSRS     r6,r0,#28             ;357
                  |L13.76|
00004c  2d04              CMP      r5,#4                 ;361
00004e  d107              BNE      |L13.96|
000050  428c              CMP      r4,r1                 ;363
000052  d102              BNE      |L13.90|
000054  f7fffffe          BL       CLK_GetPCLK0Freq
000058  e001              B        |L13.94|
                  |L13.90|
00005a  f7fffffe          BL       CLK_GetPCLK1Freq
                  |L13.94|
00005e  9004              STR      r0,[sp,#0x10]         ;365
                  |L13.96|
000060  9808              LDR      r0,[sp,#0x20]         ;375
000062  2800              CMP      r0,#0                 ;375
000064  d01c              BEQ      |L13.160|
000066  00a9              LSLS     r1,r5,#2              ;377
000068  5878              LDR      r0,[r7,r1]            ;377
00006a  1c71              ADDS     r1,r6,#1              ;377
00006c  f7fffffe          BL       __aeabi_uidivmod
000070  9908              LDR      r1,[sp,#0x20]         ;377
000072  4605              MOV      r5,r0                 ;377
000074  0849              LSRS     r1,r1,#1              ;377
000076  1840              ADDS     r0,r0,r1              ;377
000078  9908              LDR      r1,[sp,#0x20]         ;377
00007a  f7fffffe          BL       __aeabi_uidivmod
00007e  4910              LDR      r1,|L13.192|
000080  1e80              SUBS     r0,r0,#2              ;379
000082  4288              CMP      r0,r1                 ;379
000084  d908              BLS      |L13.152|
000086  9908              LDR      r1,[sp,#0x20]         ;381
000088  00c9              LSLS     r1,r1,#3              ;381
00008a  1868              ADDS     r0,r5,r1              ;381
00008c  9908              LDR      r1,[sp,#0x20]         ;381
00008e  f7fffffe          BL       __aeabi_uidivmod
000092  0900              LSRS     r0,r0,#4              ;381
000094  1e80              SUBS     r0,r0,#2              ;381
000096  e002              B        |L13.158|
                  |L13.152|
000098  2103              MOVS     r1,#3                 ;385
00009a  0709              LSLS     r1,r1,#28             ;385
00009c  4308              ORRS     r0,r0,r1              ;385
                  |L13.158|
00009e  6260              STR      r0,[r4,#0x24]         ;381
                  |L13.160|
0000a0  990a              LDR      r1,[sp,#0x28]         ;390
0000a2  9809              LDR      r0,[sp,#0x24]         ;390
0000a4  4308              ORRS     r0,r0,r1              ;390
0000a6  9910              LDR      r1,[sp,#0x40]         ;390
0000a8  4308              ORRS     r0,r0,r1              ;390
0000aa  60e0              STR      r0,[r4,#0xc]          ;390
0000ac  b00b              ADD      sp,sp,#0x2c
0000ae  bdf0              POP      {r4-r7,pc}
;;;392    
                          ENDP

                  |L13.176|
                          DCD      ||.constdata||
                  |L13.180|
                          DCD      0x40070000
                  |L13.184|
                          DCD      0x40000200
                  |L13.188|
                          DCD      0x40071000
                  |L13.192|
                          DCD      0x0000ffff

                          AREA ||i.UART_SetTimeoutCnt||, CODE, READONLY, ALIGN=1

                  UART_SetTimeoutCnt PROC
;;;403     */
;;;404    void UART_SetTimeoutCnt(UART_T *uart, uint32_t u32TOC)
000000  6a02              LDR      r2,[r0,#0x20]
;;;405    {
;;;406        /* Set time-out interrupt comparator */
;;;407        uart->TOUT = (uart->TOUT & ~UART_TOUT_TOIC_Msk) | (u32TOC);
000002  0a12              LSRS     r2,r2,#8
000004  0212              LSLS     r2,r2,#8
000006  430a              ORRS     r2,r2,r1
000008  6202              STR      r2,[r0,#0x20]
;;;408    
;;;409        /* Set time-out counter enable */
;;;410        uart->INTEN |= UART_INTEN_TOCNTEN_Msk;
00000a  6841              LDR      r1,[r0,#4]
00000c  2201              MOVS     r2,#1
00000e  02d2              LSLS     r2,r2,#11
000010  4311              ORRS     r1,r1,r2
000012  6041              STR      r1,[r0,#4]
;;;411    }
000014  4770              BX       lr
;;;412    
                          ENDP


                          AREA ||i.UART_Write||, CODE, READONLY, ALIGN=1

                  UART_Write PROC
;;;554     */
;;;555    uint32_t UART_Write(UART_T *uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes)
000000  b4f0              PUSH     {r4-r7}
;;;556    {
;;;557        uint32_t  u32Count, u32delayno;
;;;558        uint32_t  u32Exit = 0ul;
000002  2700              MOVS     r7,#0
000004  4604              MOV      r4,r0                 ;556
;;;559    
;;;560        for (u32Count = 0ul; u32Count != u32WriteBytes; u32Count++)
000006  4638              MOV      r0,r7
000008  2a00              CMP      r2,#0
00000a  d012              BEQ      |L15.50|
;;;561        {
;;;562            u32delayno = 0ul;
;;;563    
;;;564            while (uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)   /* Check Tx Full */
;;;565            {
;;;566                u32delayno++;
;;;567    
;;;568                if (u32delayno >= 0x40000000ul)
00000c  2601              MOVS     r6,#1
00000e  07b6              LSLS     r6,r6,#30
                  |L15.16|
000010  69a5              LDR      r5,[r4,#0x18]         ;564
000012  2300              MOVS     r3,#0                 ;562
000014  022d              LSLS     r5,r5,#8              ;564
000016  d505              BPL      |L15.36|
                  |L15.24|
000018  1c5b              ADDS     r3,r3,#1              ;564
00001a  42b3              CMP      r3,r6
00001c  d209              BCS      |L15.50|
00001e  69a5              LDR      r5,[r4,#0x18]         ;564
000020  022d              LSLS     r5,r5,#8              ;564
000022  d4f9              BMI      |L15.24|
                  |L15.36|
;;;569                {
;;;570                    u32Exit = 1ul;
;;;571                    break;
;;;572                }
;;;573            }
;;;574    
;;;575            if (u32Exit == 1ul)
000024  2f00              CMP      r7,#0
000026  d104              BNE      |L15.50|
;;;576            {
;;;577                break;
;;;578            }
;;;579            else
;;;580            {
;;;581                uart->DAT = pu8TxBuf[u32Count];    /* Send UART Data from buffer */
000028  5c0b              LDRB     r3,[r1,r0]
00002a  6023              STR      r3,[r4,#0]
00002c  1c40              ADDS     r0,r0,#1
00002e  4290              CMP      r0,r2                 ;560
000030  d1ee              BNE      |L15.16|
                  |L15.50|
;;;582            }
;;;583        }
;;;584    
;;;585        return u32Count;
;;;586    
;;;587    }
000032  bcf0              POP      {r4-r7}
000034  4770              BX       lr
;;;588    /**
                          ENDP


                          AREA ||.constdata||, DATA, READONLY, ALIGN=2

                          DCD      0x00b71b00
                          DCD      0x00000000
                          DCD      0x00008000
                          DCD      0x02dc6c00
                          DCD      0x00000000
                          DCD      0x00009600
                          DCD      0x00b71b00
                          DCD      0x00000000
                          DCD      0x00008000
                          DCD      0x02dc6c00
                          DCD      0x00000000
                          DCD      0x00009600
                          DCD      0x00b71b00
                          DCD      0x00000000
                          DCD      0x00008000
                          DCD      0x02dc6c00
                          DCD      0x00000000
                          DCD      0x00009600

;*** Start embedded assembler ***

#line 1 "..\\..\\..\\..\\Library\\StdDriver\\src\\uart.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___6_uart_c_f12f5b44____REV16|
#line 464 "..\\..\\..\\..\\Library\\CMSIS\\Include\\cmsis_armcc.h"
|__asm___6_uart_c_f12f5b44____REV16| PROC
#line 465

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___6_uart_c_f12f5b44____REVSH|
#line 479
|__asm___6_uart_c_f12f5b44____REVSH| PROC
#line 480

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
