; generated by Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\timer.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\timer.d --cpu=Cortex-M0 --apcs=interwork -Otime --diag_suppress=9931 -I..\..\..\..\Library\CMSIS\Include -I..\..\..\..\Library\Device\Nuvoton\M0A21\Include -I..\..\..\..\Library\StdDriver\inc -I..\ -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -D__MICROLIB -D__UVISION_VERSION=538 --omf_browse=.\obj\timer.crf ..\..\..\..\Library\StdDriver\src\timer.c]
                          THUMB

                          AREA ||i.TIMER_Close||, CODE, READONLY, ALIGN=1

                  TIMER_Close PROC
;;;76       */
;;;77     void TIMER_Close(TIMER_T *timer)
000000  2100              MOVS     r1,#0
;;;78     {
;;;79         timer->CTL = 0;
000002  6001              STR      r1,[r0,#0]
;;;80         timer->EXTCTL = 0;
000004  6141              STR      r1,[r0,#0x14]
;;;81     }
000006  4770              BX       lr
;;;82     
                          ENDP


                          AREA ||i.TIMER_Delay||, CODE, READONLY, ALIGN=2

                  TIMER_Delay PROC
;;;96       */
;;;97     int32_t TIMER_Delay(TIMER_T *timer, uint32_t u32Usec)
000000  b5f8              PUSH     {r3-r7,lr}
;;;98     {
000002  460d              MOV      r5,r1
000004  4604              MOV      r4,r0
;;;99         uint32_t u32Clk = TIMER_GetModuleClock(timer);
000006  f7fffffe          BL       TIMER_GetModuleClock
;;;100        uint32_t u32Prescale = 0UL, u32Delay;
00000a  2600              MOVS     r6,#0
00000c  4607              MOV      r7,r0                 ;99
;;;101        uint32_t u32Cmpr, u32Cntr, u32NsecPerTick, i = 0UL;
;;;102    
;;;103        /* Clear current timer configuration */
;;;104        timer->CTL = 0;
00000e  6026              STR      r6,[r4,#0]
;;;105        timer->EXTCTL = 0;
000010  6166              STR      r6,[r4,#0x14]
;;;106    
;;;107        if(u32Clk <= 1000000)   /* min delay is 1000 us if timer clock source is <= 1 MHz */
000012  492b              LDR      r1,|L2.192|
000014  4288              CMP      r0,r1
000016  d808              BHI      |L2.42|
;;;108        {
;;;109            if(u32Usec < 1000)
000018  207d              MOVS     r0,#0x7d
00001a  00c0              LSLS     r0,r0,#3
00001c  4285              CMP      r5,r0
00001e  d201              BCS      |L2.36|
;;;110                u32Usec = 1000;
000020  4605              MOV      r5,r0
000022  e009              B        |L2.56|
                  |L2.36|
;;;111            if(u32Usec > 1000000)
000024  428d              CMP      r5,r1
000026  d806              BHI      |L2.54|
000028  e006              B        |L2.56|
                  |L2.42|
;;;112                u32Usec = 1000000;
;;;113        }
;;;114        else
;;;115        {
;;;116            if(u32Usec < 100)
00002a  2d64              CMP      r5,#0x64
00002c  d201              BCS      |L2.50|
;;;117                u32Usec = 100;
00002e  2564              MOVS     r5,#0x64
000030  e002              B        |L2.56|
                  |L2.50|
;;;118            if(u32Usec > 1000000)
000032  428d              CMP      r5,r1
000034  d900              BLS      |L2.56|
                  |L2.54|
;;;119                u32Usec = 1000000;
000036  460d              MOV      r5,r1
                  |L2.56|
;;;120        }
;;;121    
;;;122        if(u32Clk <= 1000000)
000038  428f              CMP      r7,r1
00003a  d809              BHI      |L2.80|
;;;123        {
;;;124            u32Prescale = 0;
;;;125            u32NsecPerTick = 1000000000 / u32Clk;
00003c  4639              MOV      r1,r7
00003e  4821              LDR      r0,|L2.196|
000040  f7fffffe          BL       __aeabi_uidivmod
000044  4601              MOV      r1,r0
;;;126            u32Cmpr = (u32Usec * 1000) / u32NsecPerTick;
000046  227d              MOVS     r2,#0x7d
000048  4628              MOV      r0,r5
00004a  00d2              LSLS     r2,r2,#3
00004c  4350              MULS     r0,r2,r0
00004e  e006              B        |L2.94|
                  |L2.80|
;;;127        }
;;;128        else
;;;129        {
;;;130            u32Cmpr = u32Usec * (u32Clk / 1000000);
000050  4638              MOV      r0,r7
000052  f7fffffe          BL       __aeabi_uidivmod
000056  4368              MULS     r0,r5,r0
;;;131            u32Prescale = (u32Cmpr >> 24);  /* for 24 bits CMPDAT */
000058  0e06              LSRS     r6,r0,#24
;;;132            if (u32Prescale > 0)
00005a  d002              BEQ      |L2.98|
;;;133                u32Cmpr = u32Cmpr / (u32Prescale + 1);
00005c  1c71              ADDS     r1,r6,#1
                  |L2.94|
00005e  f7fffffe          BL       __aeabi_uidivmod
                  |L2.98|
;;;134        }
;;;135    
;;;136        timer->CMP = u32Cmpr;
000062  6060              STR      r0,[r4,#4]
;;;137        timer->CTL = TIMER_CTL_CNTEN_Msk | TIMER_ONESHOT_MODE | u32Prescale;
000064  2001              MOVS     r0,#1
000066  0780              LSLS     r0,r0,#30
000068  4330              ORRS     r0,r0,r6
00006a  6020              STR      r0,[r4,#0]
;;;138    
;;;139        /* When system clock is faster than timer clock, it is possible timer active bit cannot set
;;;140           in time while we check it. And the while loop below return immediately, so put a tiny
;;;141           delay larger than 1 ECLK here allowing timer start counting and raise active flag. */
;;;142        for(u32Delay = (SystemCoreClock / u32Clk) + 1UL; u32Delay > 0UL; u32Delay--)
00006c  4d16              LDR      r5,|L2.200|
00006e  4639              MOV      r1,r7
000070  6828              LDR      r0,[r5,#0]  ; SystemCoreClock
000072  f7fffffe          BL       __aeabi_uidivmod
000076  1c40              ADDS     r0,r0,#1
000078  d002              BEQ      |L2.128|
                  |L2.122|
;;;143        {
;;;144            __NOP();
00007a  bf00              NOP      
00007c  1e40              SUBS     r0,r0,#1
00007e  d1fc              BNE      |L2.122|
                  |L2.128|
;;;145        }
;;;146    
;;;147        /* Add a bail out counter here in case timer clock source is disabled accidentally.
;;;148           Prescale counter reset every ECLK * (prescale value + 1).
;;;149           The u32Delay here is to make sure timer counter value changed when prescale counter reset */
;;;150        u32Delay = (SystemCoreClock / TIMER_GetModuleClock(timer)) * (u32Prescale + 1);
000080  4620              MOV      r0,r4
000082  f7fffffe          BL       TIMER_GetModuleClock
000086  4601              MOV      r1,r0
000088  6828              LDR      r0,[r5,#0]  ; SystemCoreClock
00008a  f7fffffe          BL       __aeabi_uidivmod
00008e  1c76              ADDS     r6,r6,#1
000090  4370              MULS     r0,r6,r0
;;;151        u32Cntr = timer->CNT;
000092  68e1              LDR      r1,[r4,#0xc]
000094  4603              MOV      r3,r0                 ;150
;;;152        i = 0;
;;;153        while(timer->CTL & TIMER_CTL_ACTSTS_Msk)
000096  6822              LDR      r2,[r4,#0]
000098  2000              MOVS     r0,#0                 ;152
00009a  0192              LSLS     r2,r2,#6
00009c  d50e              BPL      |L2.188|
                  |L2.158|
;;;154        {
;;;155            /* Bailed out if timer stop counting e.g. Some interrupt handler close timer clock source. */
;;;156            if(u32Cntr == timer->CNT)
00009e  68e2              LDR      r2,[r4,#0xc]
0000a0  428a              CMP      r2,r1
0000a2  d106              BNE      |L2.178|
;;;157            {
;;;158                if(i++ > u32Delay)
0000a4  4602              MOV      r2,r0
0000a6  1c40              ADDS     r0,r0,#1
0000a8  429a              CMP      r2,r3
0000aa  d904              BLS      |L2.182|
;;;159                {
;;;160                    return TIMER_TIMEOUT_ERR;
0000ac  2000              MOVS     r0,#0
0000ae  43c0              MVNS     r0,r0
;;;161                }
;;;162            }
;;;163            else
;;;164            {
;;;165                i = 0;
;;;166                u32Cntr = timer->CNT;
;;;167            }
;;;168        }
;;;169        return 0;
;;;170    }
0000b0  bdf8              POP      {r3-r7,pc}
                  |L2.178|
0000b2  68e1              LDR      r1,[r4,#0xc]          ;166
0000b4  2000              MOVS     r0,#0                 ;165
                  |L2.182|
0000b6  6822              LDR      r2,[r4,#0]            ;153
0000b8  0192              LSLS     r2,r2,#6              ;153
0000ba  d4f0              BMI      |L2.158|
                  |L2.188|
0000bc  2000              MOVS     r0,#0                 ;169
0000be  bdf8              POP      {r3-r7,pc}
;;;171    
                          ENDP

                  |L2.192|
                          DCD      0x000f4240
                  |L2.196|
                          DCD      0x3b9aca00
                  |L2.200|
                          DCD      SystemCoreClock

                          AREA ||i.TIMER_DisableCapture||, CODE, READONLY, ALIGN=1

                  TIMER_DisableCapture PROC
;;;207      */
;;;208    void TIMER_DisableCapture(TIMER_T *timer)
000000  6941              LDR      r1,[r0,#0x14]
;;;209    {
;;;210        timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk;
000002  2208              MOVS     r2,#8
000004  4391              BICS     r1,r1,r2
000006  6141              STR      r1,[r0,#0x14]
;;;211    }
000008  4770              BX       lr
;;;212    
                          ENDP


                          AREA ||i.TIMER_DisableEventCounter||, CODE, READONLY, ALIGN=1

                  TIMER_DisableEventCounter PROC
;;;241      */
;;;242    void TIMER_DisableEventCounter(TIMER_T *timer)
000000  6801              LDR      r1,[r0,#0]
;;;243    {
;;;244        timer->CTL &= ~TIMER_CTL_EXTCNTEN_Msk;
000002  2201              MOVS     r2,#1
000004  0612              LSLS     r2,r2,#24
000006  4391              BICS     r1,r1,r2
000008  6001              STR      r1,[r0,#0]
;;;245    }
00000a  4770              BX       lr
;;;246    
                          ENDP


                          AREA ||i.TIMER_DisableFreqCounter||, CODE, READONLY, ALIGN=1

                  TIMER_DisableFreqCounter PROC
;;;317      */
;;;318    void TIMER_DisableFreqCounter(TIMER_T *timer)
000000  6801              LDR      r1,[r0,#0]
;;;319    {
;;;320        timer->CTL &= ~TIMER_CTL_INTRGEN_Msk;
000002  2201              MOVS     r2,#1
000004  0292              LSLS     r2,r2,#10
000006  4391              BICS     r1,r1,r2
000008  6001              STR      r1,[r0,#0]
;;;321    }
00000a  4770              BX       lr
;;;322    
                          ENDP


                          AREA ||i.TIMER_EnableCapture||, CODE, READONLY, ALIGN=2

                  TIMER_EnableCapture PROC
;;;192      */
;;;193    void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge)
000000  b410              PUSH     {r4}
;;;194    {
;;;195        timer->EXTCTL = (timer->EXTCTL & ~(TIMER_EXTCTL_CAPFUNCS_Msk | TIMER_EXTCTL_CAPEDGE_Msk)) |
000002  6943              LDR      r3,[r0,#0x14]
000004  4c04              LDR      r4,|L6.24|
000006  4023              ANDS     r3,r3,r4
000008  430b              ORRS     r3,r3,r1
00000a  4313              ORRS     r3,r3,r2
00000c  2108              MOVS     r1,#8
00000e  430b              ORRS     r3,r3,r1
000010  6143              STR      r3,[r0,#0x14]
;;;196                        u32CapMode | u32Edge | TIMER_EXTCTL_CAPEN_Msk;
;;;197    }
000012  bc10              POP      {r4}
000014  4770              BX       lr
;;;198    
                          ENDP

000016  0000              DCW      0x0000
                  |L6.24|
                          DCD      0xffff8fef

                          AREA ||i.TIMER_EnableEventCounter||, CODE, READONLY, ALIGN=1

                  TIMER_EnableEventCounter PROC
;;;226      */
;;;227    void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge)
000000  6942              LDR      r2,[r0,#0x14]
;;;228    {
;;;229        timer->EXTCTL = (timer->EXTCTL & ~TIMER_EXTCTL_CNTPHASE_Msk) | u32Edge;
000002  0852              LSRS     r2,r2,#1
000004  0052              LSLS     r2,r2,#1
000006  430a              ORRS     r2,r2,r1
000008  6142              STR      r2,[r0,#0x14]
;;;230        timer->CTL |= TIMER_CTL_EXTCNTEN_Msk;
00000a  6801              LDR      r1,[r0,#0]
00000c  2201              MOVS     r2,#1
00000e  0612              LSLS     r2,r2,#24
000010  4311              ORRS     r1,r1,r2
000012  6001              STR      r1,[r0,#0]
;;;231    }
000014  4770              BX       lr
;;;232    
                          ENDP


                          AREA ||i.TIMER_EnableFreqCounter||, CODE, READONLY, ALIGN=2

                  TIMER_EnableFreqCounter PROC
;;;297      */
;;;298    void TIMER_EnableFreqCounter(TIMER_T *timer, uint32_t u32DropCount, uint32_t u32Timeout, uint32_t u32EnableInt)
000000  4908              LDR      r1,|L8.36|
;;;299    {
;;;300        TIMER_T *t;    /* store the timer base to configure compare value */
;;;301    
;;;302        t = (timer == TIMER0) ? TIMER1 : TIMER3;
000002  4288              CMP      r0,r1
000004  d101              BNE      |L8.10|
000006  4908              LDR      r1,|L8.40|
000008  e000              B        |L8.12|
                  |L8.10|
00000a  4908              LDR      r1,|L8.44|
                  |L8.12|
;;;303    
;;;304        t->CMP = 0xFFFFFF;
00000c  4a08              LDR      r2,|L8.48|
00000e  604a              STR      r2,[r1,#4]
;;;305        t->EXTCTL = u32EnableInt ? TIMER_EXTCTL_CAPIEN_Msk : 0;
000010  2b00              CMP      r3,#0
000012  d001              BEQ      |L8.24|
000014  2220              MOVS     r2,#0x20
000016  e000              B        |L8.26|
                  |L8.24|
000018  2200              MOVS     r2,#0
                  |L8.26|
00001a  614a              STR      r2,[r1,#0x14]
;;;306        timer->CTL = TIMER_CTL_INTRGEN_Msk | TIMER_CTL_CNTEN_Msk;
00001c  4905              LDR      r1,|L8.52|
00001e  6001              STR      r1,[r0,#0]
;;;307    
;;;308        return;
;;;309    }
000020  4770              BX       lr
;;;310    
                          ENDP

000022  0000              DCW      0x0000
                  |L8.36|
                          DCD      0x40050000
                  |L8.40|
                          DCD      0x40050020
                  |L8.44|
                          DCD      0x40051020
                  |L8.48|
                          DCD      0x00ffffff
                  |L8.52|
                          DCD      0x40000400

                          AREA ||i.TIMER_GetModuleClock||, CODE, READONLY, ALIGN=2

                  TIMER_GetModuleClock PROC
;;;256      */
;;;257    uint32_t TIMER_GetModuleClock(TIMER_T *timer)
000000  b530              PUSH     {r4,r5,lr}
;;;258    {
;;;259        uint32_t u32Src;
;;;260        const uint32_t au32Clk[] = {__HXT, __LXT, 0, 0, 0, __LIRC, 0, __HIRC};
000002  4919              LDR      r1,|L9.104|
000004  b089              SUB      sp,sp,#0x24           ;258
000006  c93c              LDM      r1!,{r2-r5}
000008  9503              STR      r5,[sp,#0xc]
00000a  9402              STR      r4,[sp,#8]
00000c  9301              STR      r3,[sp,#4]
00000e  9200              STR      r2,[sp,#0]
000010  c91e              LDM      r1,{r1-r4}
000012  ad04              ADD      r5,sp,#0x10
000014  c51e              STM      r5!,{r1-r4}
;;;261    
;;;262        if(timer == TIMER0)
000016  4a15              LDR      r2,|L9.108|
;;;263            u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0SEL_Msk) >> CLK_CLKSEL1_TMR0SEL_Pos;
000018  4915              LDR      r1,|L9.112|
;;;264        else if(timer == TIMER1)
00001a  4b16              LDR      r3,|L9.116|
00001c  4290              CMP      r0,r2                 ;262
00001e  d102              BNE      |L9.38|
000020  6949              LDR      r1,[r1,#0x14]         ;263
;;;265            u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1SEL_Msk) >> CLK_CLKSEL1_TMR1SEL_Pos;
;;;266        else if(timer == TIMER2)
;;;267            u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR2SEL_Msk) >> CLK_CLKSEL1_TMR2SEL_Pos;
;;;268        else  /* Timer 3 */
;;;269            u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR3SEL_Msk) >> CLK_CLKSEL1_TMR3SEL_Pos;
;;;270    
;;;271        if(u32Src == 2)
;;;272        {
;;;273            if ((timer == TIMER0) || (timer == TIMER1))
;;;274                return CLK_GetPCLK0Freq();
;;;275            else
;;;276                return CLK_GetPCLK1Freq();
;;;277        }
;;;278    
;;;279        return (au32Clk[u32Src]);
;;;280    }
000022  0a09              LSRS     r1,r1,#8
000024  e003              B        |L9.46|
                  |L9.38|
000026  4298              CMP      r0,r3                 ;264
000028  d10a              BNE      |L9.64|
00002a  6949              LDR      r1,[r1,#0x14]         ;265
00002c  0b09              LSRS     r1,r1,#12
                  |L9.46|
00002e  0749              LSLS     r1,r1,#29
000030  0f49              LSRS     r1,r1,#29
000032  2902              CMP      r1,#2                 ;271
000034  d00c              BEQ      |L9.80|
000036  0088              LSLS     r0,r1,#2              ;279
000038  4669              MOV      r1,sp                 ;279
00003a  5808              LDR      r0,[r1,r0]            ;279
00003c  b009              ADD      sp,sp,#0x24
00003e  bd30              POP      {r4,r5,pc}
                  |L9.64|
000040  4c0d              LDR      r4,|L9.120|
000042  6949              LDR      r1,[r1,#0x14]         ;269
000044  42a0              CMP      r0,r4                 ;266
000046  d101              BNE      |L9.76|
000048  0c09              LSRS     r1,r1,#16
00004a  e7f0              B        |L9.46|
                  |L9.76|
00004c  0d09              LSRS     r1,r1,#20
00004e  e7ee              B        |L9.46|
                  |L9.80|
000050  4290              CMP      r0,r2                 ;273
000052  d001              BEQ      |L9.88|
000054  4298              CMP      r0,r3                 ;273
000056  d103              BNE      |L9.96|
                  |L9.88|
000058  f7fffffe          BL       CLK_GetPCLK0Freq
00005c  b009              ADD      sp,sp,#0x24
00005e  bd30              POP      {r4,r5,pc}
                  |L9.96|
000060  f7fffffe          BL       CLK_GetPCLK1Freq
000064  b009              ADD      sp,sp,#0x24
000066  bd30              POP      {r4,r5,pc}
;;;281    
                          ENDP

                  |L9.104|
                          DCD      ||.constdata||
                  |L9.108|
                          DCD      0x40050000
                  |L9.112|
                          DCD      0x40000200
                  |L9.116|
                          DCD      0x40050020
                  |L9.120|
                          DCD      0x40051000

                          AREA ||i.TIMER_Open||, CODE, READONLY, ALIGN=1

                  TIMER_Open PROC
;;;43       */
;;;44     uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq)
000000  b5f8              PUSH     {r3-r7,lr}
;;;45     {
000002  4617              MOV      r7,r2
000004  460e              MOV      r6,r1
000006  4605              MOV      r5,r0
;;;46         uint32_t u32Clk = TIMER_GetModuleClock(timer);
000008  f7fffffe          BL       TIMER_GetModuleClock
;;;47         uint32_t u32Cmpr = 0, u32Prescale = 0;
;;;48     
;;;49         /* Fastest possible timer working freq is (u32Clk / 2). While cmpr = 2, pre-scale = 0. */
;;;50         if(u32Freq >= (u32Clk >> 1))
00000c  9000              STR      r0,[sp,#0]
00000e  2400              MOVS     r4,#0                 ;47
000010  0840              LSRS     r0,r0,#1
000012  42b8              CMP      r0,r7
000014  d801              BHI      |L10.26|
;;;51         {
;;;52             u32Cmpr = 2;
000016  2002              MOVS     r0,#2
000018  e008              B        |L10.44|
                  |L10.26|
;;;53         }
;;;54         else
;;;55         {
;;;56             u32Cmpr = u32Clk / u32Freq;
00001a  4639              MOV      r1,r7
00001c  9800              LDR      r0,[sp,#0]
00001e  f7fffffe          BL       __aeabi_uidivmod
;;;57             u32Prescale = (u32Cmpr >> 24);  /* for 24 bits CMPDAT */
000022  0e04              LSRS     r4,r0,#24
;;;58             if (u32Prescale > 0)
000024  d002              BEQ      |L10.44|
;;;59                 u32Cmpr = u32Cmpr / (u32Prescale + 1);
000026  1c61              ADDS     r1,r4,#1
000028  f7fffffe          BL       __aeabi_uidivmod
                  |L10.44|
;;;60         }
;;;61     
;;;62         timer->CTL = u32Mode | u32Prescale;
00002c  4326              ORRS     r6,r6,r4
00002e  602e              STR      r6,[r5,#0]
;;;63         timer->CMP = u32Cmpr;
000030  6068              STR      r0,[r5,#4]
000032  1c64              ADDS     r4,r4,#1
;;;64     
;;;65         return(u32Clk / (u32Cmpr * (u32Prescale + 1)));
000034  4360              MULS     r0,r4,r0
000036  4601              MOV      r1,r0
000038  9800              LDR      r0,[sp,#0]
00003a  f7fffffe          BL       __aeabi_uidivmod
;;;66     }
00003e  bdf8              POP      {r3-r7,pc}
;;;67     
                          ENDP


                          AREA ||i.TIMER_SetTriggerSource||, CODE, READONLY, ALIGN=1

                  TIMER_SetTriggerSource PROC
;;;332      */
;;;333    void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src)
000000  6802              LDR      r2,[r0,#0]
;;;334    {
;;;335        timer->CTL = (timer->CTL & ~TIMER_CTL_TRGSSEL_Msk) | u32Src;
000002  2301              MOVS     r3,#1
000004  049b              LSLS     r3,r3,#18
000006  439a              BICS     r2,r2,r3
000008  430a              ORRS     r2,r2,r1
00000a  6002              STR      r2,[r0,#0]
;;;336    }
00000c  4770              BX       lr
;;;337    
                          ENDP


                          AREA ||i.TIMER_SetTriggerTarget||, CODE, READONLY, ALIGN=2

                  TIMER_SetTriggerTarget PROC
;;;349      */
;;;350    void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask)
000000  6802              LDR      r2,[r0,#0]
;;;351    {
;;;352        timer->CTL = (timer->CTL & ~(TIMER_CTL_TRGPWM_Msk | TIMER_CTL_TRGDAC_Msk | TIMER_CTL_TRGADC_Msk | TIMER_CTL_TRGPDMA_Msk)) | (u32Mask);
000002  4b02              LDR      r3,|L12.12|
000004  401a              ANDS     r2,r2,r3
000006  430a              ORRS     r2,r2,r1
000008  6002              STR      r2,[r0,#0]
;;;353    }
00000a  4770              BX       lr
;;;354    
                          ENDP

                  |L12.12|
                          DCD      0xffc7feff

                          AREA ||.constdata||, DATA, READONLY, ALIGN=2

                          DCD      0x00b71b00
                          DCD      0x00008000
                          DCD      0x00000000
                          DCD      0x00000000
                          DCD      0x00000000
                          DCD      0x00009600
                          DCD      0x00000000
                          DCD      0x02dc6c00

;*** Start embedded assembler ***

#line 1 "..\\..\\..\\..\\Library\\StdDriver\\src\\timer.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___7_timer_c_5bec749a____REV16|
#line 464 "..\\..\\..\\..\\Library\\CMSIS\\Include\\cmsis_armcc.h"
|__asm___7_timer_c_5bec749a____REV16| PROC
#line 465

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___7_timer_c_5bec749a____REVSH|
#line 479
|__asm___7_timer_c_5bec749a____REVSH| PROC
#line 480

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
