; generated by Component: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]
; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\obj\clk.o --asm_dir=.\lst\ --list_dir=.\lst\ --depend=.\obj\clk.d --cpu=Cortex-M0 --apcs=interwork -Otime --diag_suppress=9931 -I..\..\..\..\Library\CMSIS\Include -I..\..\..\..\Library\Device\Nuvoton\M0A21\Include -I..\..\..\..\Library\StdDriver\inc -I..\ -IC:\Keil_v5\ARM\RV31\INC -IC:\Keil_v5\ARM\CMSIS\Include -D__MICROLIB -D__UVISION_VERSION=538 --omf_browse=.\obj\clk.crf ..\..\..\..\Library\StdDriver\src\clk.c]
                          THUMB

                          AREA ||i.CLK_DisableCKO||, CODE, READONLY, ALIGN=2

                  CLK_DisableCKO PROC
;;;33       */
;;;34     void CLK_DisableCKO(void)
000000  4802              LDR      r0,|L1.12|
;;;35     {
;;;36         /* Disable CKO clock source */
;;;37         CLK->APBCLK0 &= (~CLK_APBCLK0_CLKOCKEN_Msk);
000002  6881              LDR      r1,[r0,#8]
000004  2240              MOVS     r2,#0x40
000006  4391              BICS     r1,r1,r2
000008  6081              STR      r1,[r0,#8]
;;;38     }
00000a  4770              BX       lr
;;;39     
                          ENDP

                  |L1.12|
                          DCD      0x40000200

                          AREA ||i.CLK_DisableModuleClock||, CODE, READONLY, ALIGN=2

                  CLK_DisableModuleClock PROC
;;;457      */
;;;458    void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
000000  4b0b              LDR      r3,|L2.48|
;;;459    {
000002  b083              SUB      sp,sp,#0xc
;;;460        uint32_t u32ClkTbl[3] = {0x0, 0x4, 0x8};    /* AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */
000004  6b1a              LDR      r2,[r3,#0x30]  ; <Data4>
000006  6ad9              LDR      r1,[r3,#0x2c]  ; <Data4>
000008  6b5b              LDR      r3,[r3,#0x34]  ; <Data4>
;;;461    
;;;462        *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK + (u32ClkTbl[MODULE_APBCLK(u32ModuleIdx)]))  &= ~(1 << MODULE_IP_EN_Pos(u32ModuleIdx));
00000a  9100              STR      r1,[sp,#0]
00000c  9201              STR      r2,[sp,#4]
00000e  0f81              LSRS     r1,r0,#30
000010  008a              LSLS     r2,r1,#2
000012  9302              STR      r3,[sp,#8]
000014  4669              MOV      r1,sp
000016  588a              LDR      r2,[r1,r2]
000018  4906              LDR      r1,|L2.52|
00001a  1851              ADDS     r1,r2,r1
00001c  684a              LDR      r2,[r1,#4]
00001e  06c3              LSLS     r3,r0,#27
000020  0edb              LSRS     r3,r3,#27
000022  2001              MOVS     r0,#1
000024  4098              LSLS     r0,r0,r3
000026  4382              BICS     r2,r2,r0
000028  604a              STR      r2,[r1,#4]
;;;463    }
00002a  b003              ADD      sp,sp,#0xc
00002c  4770              BX       lr
;;;464    
                          ENDP

00002e  0000              DCW      0x0000
                  |L2.48|
                          DCD      ||.constdata||
                  |L2.52|
                          DCD      0x40000200

                          AREA ||i.CLK_DisableSysTick||, CODE, READONLY, ALIGN=2

                  CLK_DisableSysTick PROC
;;;539      */
;;;540    void CLK_DisableSysTick(void)
000000  4901              LDR      r1,|L3.8|
;;;541    {
;;;542        /* Set System Tick counter disabled */
;;;543        SysTick->CTRL = 0;
000002  2000              MOVS     r0,#0
000004  6108              STR      r0,[r1,#0x10]
;;;544    }
000006  4770              BX       lr
;;;545    
                          ENDP

                  |L3.8|
                          DCD      0xe000e000

                          AREA ||i.CLK_DisableXtalRC||, CODE, READONLY, ALIGN=2

                  CLK_DisableXtalRC PROC
;;;393      */
;;;394    void CLK_DisableXtalRC(uint32_t u32ClkMask)
000000  4902              LDR      r1,|L4.12|
;;;395    {
;;;396        CLK->PWRCTL &= ~u32ClkMask;
000002  680a              LDR      r2,[r1,#0]
000004  4382              BICS     r2,r2,r0
000006  600a              STR      r2,[r1,#0]
;;;397    }
000008  4770              BX       lr
;;;398    
                          ENDP

00000a  0000              DCW      0x0000
                  |L4.12|
                          DCD      0x40000200

                          AREA ||i.CLK_EnableCKO||, CODE, READONLY, ALIGN=2

                  CLK_EnableCKO PROC
;;;59       */
;;;60     void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
000000  0152              LSLS     r2,r2,#5
;;;61     {
;;;62         /* CKO = clock source / 2^(u32ClkDiv + 1) */
;;;63         CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | u32ClkDiv | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos);
000002  430a              ORRS     r2,r2,r1
000004  2110              MOVS     r1,#0x10
000006  430a              ORRS     r2,r2,r1
000008  4906              LDR      r1,|L5.36|
00000a  620a              STR      r2,[r1,#0x20]
;;;64     
;;;65         /* Enable CKO clock source */
;;;66         CLK->APBCLK0 |= CLK_APBCLK0_CLKOCKEN_Msk;
00000c  4906              LDR      r1,|L5.40|
00000e  688a              LDR      r2,[r1,#8]
000010  2340              MOVS     r3,#0x40
000012  431a              ORRS     r2,r2,r3
000014  608a              STR      r2,[r1,#8]
;;;67     
;;;68         /* Select CKO clock source */
;;;69         CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_CLKOSEL_Msk)) | (u32ClkSrc);
000016  694a              LDR      r2,[r1,#0x14]
000018  2370              MOVS     r3,#0x70
00001a  439a              BICS     r2,r2,r3
00001c  4302              ORRS     r2,r2,r0
00001e  614a              STR      r2,[r1,#0x14]
;;;70     }
000020  4770              BX       lr
;;;71     
                          ENDP

000022  0000              DCW      0x0000
                  |L5.36|
                          DCD      0x40000240
                  |L5.40|
                          DCD      0x40000200

                          AREA ||i.CLK_EnableModuleClock||, CODE, READONLY, ALIGN=2

                  CLK_EnableModuleClock PROC
;;;424      */
;;;425    void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
000000  4b0b              LDR      r3,|L6.48|
;;;426    {
000002  b083              SUB      sp,sp,#0xc
;;;427        uint32_t u32ClkTbl[3] = {0x0, 0x4, 0x8};    /* AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */
000004  6a5a              LDR      r2,[r3,#0x24]  ; <Data3>
000006  6a19              LDR      r1,[r3,#0x20]  ; <Data3>
000008  6a9b              LDR      r3,[r3,#0x28]  ; <Data3>
;;;428    
;;;429        *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK + (u32ClkTbl[MODULE_APBCLK(u32ModuleIdx)]))  |= 1 << MODULE_IP_EN_Pos(u32ModuleIdx);
00000a  9100              STR      r1,[sp,#0]
00000c  9201              STR      r2,[sp,#4]
00000e  0f81              LSRS     r1,r0,#30
000010  008a              LSLS     r2,r1,#2
000012  9302              STR      r3,[sp,#8]
000014  4669              MOV      r1,sp
000016  588a              LDR      r2,[r1,r2]
000018  4906              LDR      r1,|L6.52|
00001a  1851              ADDS     r1,r2,r1
00001c  684a              LDR      r2,[r1,#4]
00001e  06c3              LSLS     r3,r0,#27
000020  0edb              LSRS     r3,r3,#27
000022  2001              MOVS     r0,#1
000024  4098              LSLS     r0,r0,r3
000026  4302              ORRS     r2,r2,r0
000028  604a              STR      r2,[r1,#4]
;;;430    }
00002a  b003              ADD      sp,sp,#0xc
00002c  4770              BX       lr
;;;431    
                          ENDP

00002e  0000              DCW      0x0000
                  |L6.48|
                          DCD      ||.constdata||
                  |L6.52|
                          DCD      0x40000200

                          AREA ||i.CLK_EnableSysTick||, CODE, READONLY, ALIGN=2

                  CLK_EnableSysTick PROC
;;;512      */
;;;513    void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
000000  b470              PUSH     {r4-r6}
;;;514    {
;;;515        /* Set System Tick counter disabled */
;;;516        SysTick->CTRL = 0;
000002  4a0c              LDR      r2,|L7.52|
000004  2400              MOVS     r4,#0
000006  6114              STR      r4,[r2,#0x10]
;;;517    
;;;518        /* Set System Tick clock source */
;;;519        if(u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK)
000008  2804              CMP      r0,#4
00000a  d00d              BEQ      |L7.40|
;;;520            SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
;;;521        else
;;;522            CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
00000c  4d0a              LDR      r5,|L7.56|
00000e  692b              LDR      r3,[r5,#0x10]
000010  2638              MOVS     r6,#0x38
000012  43b3              BICS     r3,r3,r6
000014  4303              ORRS     r3,r3,r0
000016  612b              STR      r3,[r5,#0x10]
                  |L7.24|
;;;523    
;;;524        /* Set System Tick reload value */
;;;525        SysTick->LOAD = u32Count;
000018  6151              STR      r1,[r2,#0x14]
;;;526    
;;;527        /* Clear System Tick current value and counter flag */
;;;528        SysTick->VAL = 0;
00001a  6194              STR      r4,[r2,#0x18]
;;;529    
;;;530        /* Set System Tick interrupt enabled and counter enabled */
;;;531        SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;
00001c  6910              LDR      r0,[r2,#0x10]
00001e  2103              MOVS     r1,#3
000020  4308              ORRS     r0,r0,r1
000022  6110              STR      r0,[r2,#0x10]
;;;532    }
000024  bc70              POP      {r4-r6}
000026  4770              BX       lr
                  |L7.40|
000028  6910              LDR      r0,[r2,#0x10]         ;520
00002a  2304              MOVS     r3,#4                 ;520
00002c  4318              ORRS     r0,r0,r3              ;520
00002e  6110              STR      r0,[r2,#0x10]         ;520
000030  e7f2              B        |L7.24|
;;;533    
                          ENDP

000032  0000              DCW      0x0000
                  |L7.52|
                          DCD      0xe000e000
                  |L7.56|
                          DCD      0x40000200

                          AREA ||i.CLK_EnableXtalRC||, CODE, READONLY, ALIGN=2

                  CLK_EnableXtalRC PROC
;;;377      */
;;;378    void CLK_EnableXtalRC(uint32_t u32ClkMask)
000000  4902              LDR      r1,|L8.12|
;;;379    {
;;;380        CLK->PWRCTL |= u32ClkMask;
000002  680a              LDR      r2,[r1,#0]
000004  4302              ORRS     r2,r2,r0
000006  600a              STR      r2,[r1,#0]
;;;381    }
000008  4770              BX       lr
;;;382    
                          ENDP

00000a  0000              DCW      0x0000
                  |L8.12|
                          DCD      0x40000200

                          AREA ||i.CLK_GetCPUFreq||, CODE, READONLY, ALIGN=2

                  CLK_GetCPUFreq PROC
;;;203      */
;;;204    uint32_t CLK_GetCPUFreq(void)
000000  b510              PUSH     {r4,lr}
;;;205    {
;;;206        SystemCoreClockUpdate();
000002  f7fffffe          BL       SystemCoreClockUpdate
;;;207        return SystemCoreClock;
000006  4801              LDR      r0,|L9.12|
000008  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
;;;208    }
00000a  bd10              POP      {r4,pc}
;;;209    
                          ENDP

                  |L9.12|
                          DCD      SystemCoreClock

                          AREA ||i.CLK_GetHCLKFreq||, CODE, READONLY, ALIGN=2

                  CLK_GetHCLKFreq PROC
;;;191      */
;;;192    uint32_t CLK_GetHCLKFreq(void)
000000  b510              PUSH     {r4,lr}
;;;193    {
;;;194        SystemCoreClockUpdate();
000002  f7fffffe          BL       SystemCoreClockUpdate
;;;195        return SystemCoreClock;
000006  4801              LDR      r0,|L10.12|
000008  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
;;;196    }
00000a  bd10              POP      {r4,pc}
;;;197    
                          ENDP

                  |L10.12|
                          DCD      SystemCoreClock

                          AREA ||i.CLK_GetHXTFreq||, CODE, READONLY, ALIGN=2

                  CLK_GetHXTFreq PROC
;;;133      */
;;;134    uint32_t CLK_GetHXTFreq(void)
000000  4802              LDR      r0,|L11.12|
;;;135    {
;;;136        if(CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk)
000002  6800              LDR      r0,[r0,#0]
000004  07c0              LSLS     r0,r0,#31
000006  d000              BEQ      |L11.10|
;;;137            return __HXT;
000008  4801              LDR      r0,|L11.16|
                  |L11.10|
;;;138        else
;;;139            return 0;
;;;140    }
00000a  4770              BX       lr
;;;141    
                          ENDP

                  |L11.12|
                          DCD      0x40000200
                  |L11.16|
                          DCD      0x00b71b00

                          AREA ||i.CLK_GetLXTFreq||, CODE, READONLY, ALIGN=2

                  CLK_GetLXTFreq PROC
;;;147      */
;;;148    uint32_t CLK_GetLXTFreq(void)
000000  4804              LDR      r0,|L12.20|
;;;149    {
;;;150        if(CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk)
000002  6800              LDR      r0,[r0,#0]
000004  0780              LSLS     r0,r0,#30
000006  d502              BPL      |L12.14|
;;;151            return __LXT;
000008  2001              MOVS     r0,#1
00000a  03c0              LSLS     r0,r0,#15
;;;152        else
;;;153            return 0;
;;;154    }
00000c  4770              BX       lr
                  |L12.14|
00000e  2000              MOVS     r0,#0                 ;153
000010  4770              BX       lr
;;;155    
                          ENDP

000012  0000              DCW      0x0000
                  |L12.20|
                          DCD      0x40000200

                          AREA ||i.CLK_GetPCLK0Freq||, CODE, READONLY, ALIGN=2

                  CLK_GetPCLK0Freq PROC
;;;161      */
;;;162    uint32_t CLK_GetPCLK0Freq(void)
000000  b510              PUSH     {r4,lr}
;;;163    {
;;;164        uint32_t PCLK0Div;
;;;165    
;;;166        SystemCoreClockUpdate();
000002  f7fffffe          BL       SystemCoreClockUpdate
;;;167        PCLK0Div = (CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) >> CLK_PCLKDIV_APB0DIV_Pos;
000006  4804              LDR      r0,|L13.24|
000008  6b40              LDR      r0,[r0,#0x34]
00000a  0741              LSLS     r1,r0,#29
;;;168        return (SystemCoreClock >> PCLK0Div);
00000c  4803              LDR      r0,|L13.28|
00000e  0f49              LSRS     r1,r1,#29             ;167
000010  6800              LDR      r0,[r0,#0]  ; SystemCoreClock
000012  40c8              LSRS     r0,r0,r1
;;;169    }
000014  bd10              POP      {r4,pc}
;;;170    
                          ENDP

000016  0000              DCW      0x0000
                  |L13.24|
                          DCD      0x40000200
                  |L13.28|
                          DCD      SystemCoreClock

                          AREA ||i.CLK_GetPCLK1Freq||, CODE, READONLY, ALIGN=2

                  CLK_GetPCLK1Freq PROC
;;;176      */
;;;177    uint32_t CLK_GetPCLK1Freq(void)
000000  b510              PUSH     {r4,lr}
;;;178    {
;;;179        uint32_t PCLK1Div;
;;;180    
;;;181        SystemCoreClockUpdate();
000002  f7fffffe          BL       SystemCoreClockUpdate
;;;182        PCLK1Div = (CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) >> CLK_PCLKDIV_APB1DIV_Pos;
000006  4804              LDR      r0,|L14.24|
000008  6b40              LDR      r0,[r0,#0x34]
;;;183        return (SystemCoreClock >> PCLK1Div);
;;;184    }
00000a  0640              LSLS     r0,r0,#25
00000c  0f41              LSRS     r1,r0,#29
00000e  4803              LDR      r0,|L14.28|
000010  6800              LDR      r0,[r0,#0]            ;183  ; SystemCoreClock
000012  40c8              LSRS     r0,r0,r1              ;183
000014  bd10              POP      {r4,pc}
;;;185    
                          ENDP

000016  0000              DCW      0x0000
                  |L14.24|
                          DCD      0x40000200
                  |L14.28|
                          DCD      SystemCoreClock

                          AREA ||i.CLK_Idle||, CODE, READONLY, ALIGN=2

                  CLK_Idle PROC
;;;115      */
;;;116    void CLK_Idle(void)
000000  4805              LDR      r0,|L15.24|
;;;117    {
;;;118        /* Set the processor uses sleep as its low power mode */
;;;119        SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
000002  6901              LDR      r1,[r0,#0x10]
000004  2204              MOVS     r2,#4
000006  4391              BICS     r1,r1,r2
000008  6101              STR      r1,[r0,#0x10]
;;;120    
;;;121        /* Set chip in idle mode because of WFI command */
;;;122        CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk;
00000a  4804              LDR      r0,|L15.28|
00000c  6801              LDR      r1,[r0,#0]
00000e  2280              MOVS     r2,#0x80
000010  4391              BICS     r1,r1,r2
000012  6001              STR      r1,[r0,#0]
;;;123    
;;;124        /* Chip enter idle mode after CPU run WFI instruction */
;;;125        __WFI();
000014  bf30              WFI      
;;;126    }
000016  4770              BX       lr
;;;127    
                          ENDP

                  |L15.24|
                          DCD      0xe000ed00
                  |L15.28|
                          DCD      0x40000200

                          AREA ||i.CLK_PowerDown||, CODE, READONLY, ALIGN=2

                  CLK_PowerDown PROC
;;;79       */
;;;80     void CLK_PowerDown(void)
000000  b081              SUB      sp,sp,#4
;;;81     {
;;;82         volatile uint32_t u32SysTickTICKINT = 0;    /* Backup Systick interrupt enable bit */
000002  2000              MOVS     r0,#0
;;;83     
;;;84         /* Check HIRC/MIRC auto trim function disable */
;;;85         if(SYS->HIRCTRIMCTL & SYS_HIRCTRIMCTL_FREQSEL_Msk)
000004  9000              STR      r0,[sp,#0]
000006  480f              LDR      r0,|L16.68|
000008  6b00              LDR      r0,[r0,#0x30]
00000a  0780              LSLS     r0,r0,#30
00000c  d118              BNE      |L16.64|
;;;86         {
;;;87             return;
;;;88         }
;;;89     
;;;90         /* Set the processor uses deep sleep as its low power mode */
;;;91         SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
00000e  480e              LDR      r0,|L16.72|
000010  6901              LDR      r1,[r0,#0x10]
000012  2204              MOVS     r2,#4
000014  4311              ORRS     r1,r1,r2
000016  6101              STR      r1,[r0,#0x10]
;;;92     
;;;93         /* Set system Power-down enabled */
;;;94         CLK->PWRCTL |= CLK_PWRCTL_PDEN_Msk;
000018  480c              LDR      r0,|L16.76|
00001a  6801              LDR      r1,[r0,#0]
00001c  2280              MOVS     r2,#0x80
00001e  4311              ORRS     r1,r1,r2
000020  6001              STR      r1,[r0,#0]
;;;95     
;;;96         /* Backup systick interrupt setting */
;;;97         u32SysTickTICKINT = SysTick->CTRL & SysTick_CTRL_TICKINT_Msk;
000022  480b              LDR      r0,|L16.80|
000024  6902              LDR      r2,[r0,#0x10]
000026  2102              MOVS     r1,#2
000028  400a              ANDS     r2,r2,r1
;;;98     
;;;99         /* Disable systick interrupt */
;;;100        SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
00002a  9200              STR      r2,[sp,#0]
00002c  6902              LDR      r2,[r0,#0x10]
00002e  438a              BICS     r2,r2,r1
000030  6102              STR      r2,[r0,#0x10]
;;;101    
;;;102        /* Chip enter Power-down mode after CPU run WFI instruction */
;;;103        __WFI();
000032  bf30              WFI      
;;;104    
;;;105        /* Restore systick interrupt setting */
;;;106        if(u32SysTickTICKINT) SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
000034  9a00              LDR      r2,[sp,#0]
000036  2a00              CMP      r2,#0
000038  d002              BEQ      |L16.64|
00003a  6902              LDR      r2,[r0,#0x10]
00003c  430a              ORRS     r2,r2,r1
00003e  6102              STR      r2,[r0,#0x10]
                  |L16.64|
;;;107    }
000040  b001              ADD      sp,sp,#4
000042  4770              BX       lr
;;;108    
                          ENDP

                  |L16.68|
                          DCD      0x400000c0
                  |L16.72|
                          DCD      0xe000ed00
                  |L16.76|
                          DCD      0x40000200
                  |L16.80|
                          DCD      0xe000e000

                          AREA ||i.CLK_SetCoreClock||, CODE, READONLY, ALIGN=2

                  CLK_SetCoreClock PROC
;;;217      */
;;;218    uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
000000  b470              PUSH     {r4-r6}
;;;219    {
;;;220        /* Switch HCLK clock source to HIRC clock */
;;;221        CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
000002  4a12              LDR      r2,|L17.76|
000004  6810              LDR      r0,[r2,#0]
000006  2104              MOVS     r1,#4
000008  4308              ORRS     r0,r0,r1
00000a  6010              STR      r0,[r2,#0]
;;;222        CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
00000c  2110              MOVS     r1,#0x10
00000e  4c11              LDR      r4,|L17.84|
000010  2300              MOVS     r3,#0
000012  6023              STR      r3,[r4,#0]  ; g_CLK_i32ErrCode
000014  4b10              LDR      r3,|L17.88|
000016  480e              LDR      r0,|L17.80|
000018  691d              LDR      r5,[r3,#0x10]
00001a  460e              MOV      r6,r1
00001c  43ae              BICS     r6,r6,r5
00001e  d005              BEQ      |L17.44|
                  |L17.32|
000020  1e40              SUBS     r0,r0,#1              ;219
000022  d00e              BEQ      |L17.66|
000024  691e              LDR      r6,[r3,#0x10]         ;219
000026  460d              MOV      r5,r1                 ;219
000028  43b5              BICS     r5,r5,r6              ;219
00002a  d1f9              BNE      |L17.32|
                  |L17.44|
;;;223        CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk;
00002c  6910              LDR      r0,[r2,#0x10]
00002e  2107              MOVS     r1,#7
000030  4308              ORRS     r0,r0,r1
000032  6110              STR      r0,[r2,#0x10]
;;;224        CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk);
000034  6a10              LDR      r0,[r2,#0x20]
000036  0900              LSRS     r0,r0,#4
000038  0100              LSLS     r0,r0,#4
00003a  6210              STR      r0,[r2,#0x20]
;;;225    
;;;226        /* Return actually HCLK frequency is HIRC frequency divide 1 */
;;;227        return (__HIRC);
;;;228    }
00003c  bc70              POP      {r4-r6}
00003e  4807              LDR      r0,|L17.92|
000040  4770              BX       lr
                  |L17.66|
000042  2000              MOVS     r0,#0
000044  43c0              MVNS     r0,r0
000046  6020              STR      r0,[r4,#0]  ; g_CLK_i32ErrCode
000048  e7f0              B        |L17.44|
;;;229    
                          ENDP

00004a  0000              DCW      0x0000
                  |L17.76|
                          DCD      0x40000200
                  |L17.80|
                          DCD      0x000fbf40
                  |L17.84|
                          DCD      ||.data||
                  |L17.88|
                          DCD      0x40000240
                  |L17.92|
                          DCD      0x02dc6c00

                          AREA ||i.CLK_SetHCLK||, CODE, READONLY, ALIGN=2

                  CLK_SetHCLK PROC
;;;242      */
;;;243    void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
000000  b5f8              PUSH     {r3-r7,lr}
;;;244    {
000002  4686              MOV      lr,r0
;;;245        uint32_t u32HIRCSTB;
;;;246    
;;;247        /* Read HIRC clock source stable flag */
;;;248        u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
000004  481a              LDR      r0,|L18.112|
000006  468c              MOV      r12,r1                ;244
000008  6904              LDR      r4,[r0,#0x10]
;;;249    
;;;250        /* Switch to HIRC for Safe. Avoid HCLK too high when applying new divider. */
;;;251        CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
00000a  4d1a              LDR      r5,|L18.116|
00000c  2110              MOVS     r1,#0x10              ;248
00000e  682a              LDR      r2,[r5,#0]
000010  400c              ANDS     r4,r4,r1              ;248
000012  2304              MOVS     r3,#4
000014  431a              ORRS     r2,r2,r3
000016  602a              STR      r2,[r5,#0]
000018  4e18              LDR      r6,|L18.124|
00001a  2700              MOVS     r7,#0
00001c  6037              STR      r7,[r6,#0]  ; g_CLK_i32ErrCode
00001e  4a16              LDR      r2,|L18.120|
000020  6907              LDR      r7,[r0,#0x10]
;;;252        CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
000022  460b              MOV      r3,r1
000024  43b9              BICS     r1,r1,r7
000026  d006              BEQ      |L18.54|
000028  4601              MOV      r1,r0                 ;248
                  |L18.42|
00002a  1e52              SUBS     r2,r2,#1              ;248
00002c  d01c              BEQ      |L18.104|
00002e  6908              LDR      r0,[r1,#0x10]         ;248
000030  461f              MOV      r7,r3                 ;248
000032  4387              BICS     r7,r7,r0              ;248
000034  d1f9              BNE      |L18.42|
                  |L18.54|
;;;253        CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | CLK_CLKSEL0_HCLKSEL_HIRC;
000036  6928              LDR      r0,[r5,#0x10]
000038  2107              MOVS     r1,#7
00003a  4308              ORRS     r0,r0,r1
00003c  6128              STR      r0,[r5,#0x10]
;;;254    
;;;255        /* Apply new Divider */
;;;256        CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv;
00003e  6a28              LDR      r0,[r5,#0x20]
000040  4661              MOV      r1,r12
000042  0900              LSRS     r0,r0,#4
000044  0100              LSLS     r0,r0,#4
000046  4308              ORRS     r0,r0,r1
000048  6228              STR      r0,[r5,#0x20]
;;;257    
;;;258        /* Switch HCLK to new HCLK source */
;;;259        CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc;
00004a  6928              LDR      r0,[r5,#0x10]
00004c  4671              MOV      r1,lr
00004e  08c0              LSRS     r0,r0,#3
000050  00c0              LSLS     r0,r0,#3
000052  4308              ORRS     r0,r0,r1
000054  6128              STR      r0,[r5,#0x10]
;;;260    
;;;261        /* Update System Core Clock */
;;;262        SystemCoreClockUpdate();
000056  f7fffffe          BL       SystemCoreClockUpdate
;;;263    
;;;264        /* Disable HIRC if HIRC is disabled before switching HCLK source */
;;;265        if(u32HIRCSTB == 0)
00005a  2c00              CMP      r4,#0
00005c  d103              BNE      |L18.102|
;;;266            CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
00005e  6828              LDR      r0,[r5,#0]
000060  2104              MOVS     r1,#4
000062  4388              BICS     r0,r0,r1
000064  6028              STR      r0,[r5,#0]
                  |L18.102|
;;;267    }
000066  bdf8              POP      {r3-r7,pc}
                  |L18.104|
000068  2000              MOVS     r0,#0
00006a  43c0              MVNS     r0,r0
00006c  6030              STR      r0,[r6,#0]  ; g_CLK_i32ErrCode
00006e  e7e2              B        |L18.54|
;;;268    
                          ENDP

                  |L18.112|
                          DCD      0x40000240
                  |L18.116|
                          DCD      0x40000200
                  |L18.120|
                          DCD      0x000fbf40
                  |L18.124|
                          DCD      ||.data||

                          AREA ||i.CLK_SetModuleClock||, CODE, READONLY, ALIGN=2

                  CLK_SetModuleClock PROC
;;;326      */
;;;327    void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
000000  b4f0              PUSH     {r4-r7}
;;;328    {
;;;329        uint32_t u32sel = 0, u32div = 0;
;;;330        uint32_t u32SelTbl[4] = {0x0, 0x4, 0x8, 0xC};   /* CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */
000002  4b19              LDR      r3,|L19.104|
000004  b088              SUB      sp,sp,#0x20           ;328
000006  cbf0              LDM      r3!,{r4-r7}
000008  9703              STR      r7,[sp,#0xc]
00000a  9602              STR      r6,[sp,#8]
00000c  9501              STR      r5,[sp,#4]
00000e  9400              STR      r4,[sp,#0]
000010  cb78              LDM      r3,{r3-r6}
000012  af04              ADD      r7,sp,#0x10
000014  c778              STM      r7!,{r3-r6}
;;;331        uint32_t u32DivTbl[4] = {0x0, 0x0, 0x0, 0x10};  /* CLKDIV offset on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV3, 0x3:CLKDIV4 */
;;;332    
;;;333        if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk)
000016  0a84              LSRS     r4,r0,#10
000018  0623              LSLS     r3,r4,#24
00001a  0e1b              LSRS     r3,r3,#24
00001c  d00e              BEQ      |L19.60|
;;;334        {
;;;335            /* Get clock divider control register address */
;;;336            u32div = (uint32_t)&CLK->CLKDIV0 + (u32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]);
00001e  0303              LSLS     r3,r0,#12
000020  0f9b              LSRS     r3,r3,#30
000022  009b              LSLS     r3,r3,#2
000024  ad04              ADD      r5,sp,#0x10
000026  58eb              LDR      r3,[r5,r3]
000028  4d10              LDR      r5,|L19.108|
00002a  195b              ADDS     r3,r3,r5
;;;337            /* Apply new divider */
;;;338            M32(u32div) = (M32(u32div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv;
00002c  b2e5              UXTB     r5,r4
00002e  0584              LSLS     r4,r0,#22
000030  0ee4              LSRS     r4,r4,#27
000032  40a5              LSLS     r5,r5,r4
000034  681c              LDR      r4,[r3,#0]
000036  43ac              BICS     r4,r4,r5
000038  4314              ORRS     r4,r4,r2
00003a  601c              STR      r4,[r3,#0]
                  |L19.60|
;;;339        }
;;;340    
;;;341        if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk)
00003c  0e42              LSRS     r2,r0,#25
00003e  0752              LSLS     r2,r2,#29
000040  d00f              BEQ      |L19.98|
;;;342        {
;;;343            /* Get clock select control register address */
;;;344            u32sel = (uint32_t)&CLK->CLKSEL0 + (u32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]);
000042  0082              LSLS     r2,r0,#2
000044  0f92              LSRS     r2,r2,#30
000046  0092              LSLS     r2,r2,#2
000048  466b              MOV      r3,sp
00004a  589a              LDR      r2,[r3,r2]
00004c  4b08              LDR      r3,|L19.112|
00004e  18d2              ADDS     r2,r2,r3
;;;345            /* Set new clock selection setting */
;;;346            M32(u32sel) = (M32(u32sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc;
000050  0103              LSLS     r3,r0,#4
000052  0f5b              LSRS     r3,r3,#29
000054  01c0              LSLS     r0,r0,#7
000056  0ec0              LSRS     r0,r0,#27
000058  4083              LSLS     r3,r3,r0
00005a  6810              LDR      r0,[r2,#0]
00005c  4398              BICS     r0,r0,r3
00005e  4308              ORRS     r0,r0,r1
000060  6010              STR      r0,[r2,#0]
                  |L19.98|
;;;347        }
;;;348    }
000062  b008              ADD      sp,sp,#0x20
000064  bcf0              POP      {r4-r7}
000066  4770              BX       lr
;;;349    
                          ENDP

                  |L19.104|
                          DCD      ||.constdata||
                  |L19.108|
                          DCD      0x40000220
                  |L19.112|
                          DCD      0x40000210

                          AREA ||i.CLK_SetSysTickClockSrc||, CODE, READONLY, ALIGN=2

                  CLK_SetSysTickClockSrc PROC
;;;361      */
;;;362    void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
000000  4a03              LDR      r2,|L20.16|
;;;363    {
;;;364        CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
000002  6911              LDR      r1,[r2,#0x10]
000004  2338              MOVS     r3,#0x38
000006  4399              BICS     r1,r1,r3
000008  4301              ORRS     r1,r1,r0
00000a  6111              STR      r1,[r2,#0x10]
;;;365    }
00000c  4770              BX       lr
;;;366    
                          ENDP

00000e  0000              DCW      0x0000
                  |L20.16|
                          DCD      0x40000200

                          AREA ||i.CLK_WaitClockReady||, CODE, READONLY, ALIGN=2

                  CLK_WaitClockReady PROC
;;;477      */
;;;478    uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
000000  b470              PUSH     {r4-r6}
;;;479    {
000002  4605              MOV      r5,r0
;;;480        uint32_t u32TimeOutCnt = 1032000;
;;;481        uint32_t u32Ret = 1U;
000004  2201              MOVS     r2,#1
;;;482    
;;;483        g_CLK_i32ErrCode = 0;
000006  4c0c              LDR      r4,|L21.56|
000008  2000              MOVS     r0,#0
;;;484        while((CLK->STATUS & u32ClkMask) != u32ClkMask)
00000a  4b0c              LDR      r3,|L21.60|
00000c  6020              STR      r0,[r4,#0]  ; g_CLK_i32ErrCode
00000e  4909              LDR      r1,|L21.52|
000010  6918              LDR      r0,[r3,#0x10]
000012  462e              MOV      r6,r5
000014  4386              BICS     r6,r6,r0
000016  d005              BEQ      |L21.36|
                  |L21.24|
000018  1e49              SUBS     r1,r1,#1              ;479
;;;485        {
;;;486            if(--u32TimeOutCnt == 0)
00001a  d006              BEQ      |L21.42|
00001c  691e              LDR      r6,[r3,#0x10]         ;484
00001e  4628              MOV      r0,r5                 ;484
000020  43b0              BICS     r0,r0,r6              ;484
000022  d1f9              BNE      |L21.24|
                  |L21.36|
;;;487            {
;;;488                u32Ret = 0U;
;;;489                break;
;;;490            }
;;;491        }
;;;492    
;;;493        if(u32TimeOutCnt == 0)
;;;494            g_CLK_i32ErrCode = CLK_TIMEOUT_ERR;
;;;495    
;;;496        return u32Ret;
;;;497    }
000024  bc70              POP      {r4-r6}
000026  4610              MOV      r0,r2                 ;496
000028  4770              BX       lr
                  |L21.42|
00002a  2200              MOVS     r2,#0                 ;488
00002c  1e50              SUBS     r0,r2,#1              ;494
00002e  6020              STR      r0,[r4,#0]            ;489  ; g_CLK_i32ErrCode
000030  e7f8              B        |L21.36|
;;;498    
                          ENDP

000032  0000              DCW      0x0000
                  |L21.52|
                          DCD      0x000fbf40
                  |L21.56|
                          DCD      ||.data||
                  |L21.60|
                          DCD      0x40000240

                          AREA ||.constdata||, DATA, READONLY, ALIGN=2

                          DCD      0x00000000
                          DCD      0x00000004
                          DCD      0x00000008
                          DCD      0x0000000c
                          DCD      0x00000000
                          DCD      0x00000000
                          DCD      0x00000000
                          DCD      0x00000010
                          DCD      0x00000000
                          DCD      0x00000004
                          DCD      0x00000008
                          DCD      0x00000000
                          DCD      0x00000004
                          DCD      0x00000008

                          AREA ||.data||, DATA, ALIGN=2

                  g_CLK_i32ErrCode
                          DCD      0x00000000

;*** Start embedded assembler ***

#line 1 "..\\..\\..\\..\\Library\\StdDriver\\src\\clk.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___5_clk_c_9a445bc2____REV16|
#line 464 "..\\..\\..\\..\\Library\\CMSIS\\Include\\cmsis_armcc.h"
|__asm___5_clk_c_9a445bc2____REV16| PROC
#line 465

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___5_clk_c_9a445bc2____REVSH|
#line 479
|__asm___5_clk_c_9a445bc2____REVSH| PROC
#line 480

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
