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N32905U1DN

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The N32905U1DN is built on the ARM926EJ-S CPU core and integrated with JPEG codec, CMOS sensor interface, 32-channel SPU (Sound Processing Unit) , ADC, DAC, for meeting various kinds of application needs while saving the BOM cost.  The combination of ARM926 @ 200MHz, synchronous DRAM, 2D BitBLT accelerator, CMOS image sensor interface, LCD panel interface, USB 1.1 Host & USB2.0 HS Device makes the N32905U1DN the best choice for LCD ELA devices.

Maximum resolution for the N32905U1DN is VGA (640x480) @ TFT LCD panel. The 2D BitBLT accelerator accelerates the graphic compution to make the rendering smooth and off-load CPU to save power consumption.

The N32905U1DN is well-positioned in terms of cost/performance for the applications which bitmap graphics is extensively used or CMOS Image Sensor (CIS) interface is required.

The N32905U1DN is for application under Linux OS and leverage the driver availability of emerging functionalities like Wi-Fi, browser, etc. On the other hand, the open source code environment also give the product development more flexible.

To meet the different requirement of the overall system BOM cost, the different size of DRAM is stacked with N3290x main SoC into one package, that is, multi-chip package (MCP) . The 16Mbitx16 SDRAM is stacked inside the N32905U1DN MCP to ensure higher performance and minimize the system design efforts, like EMI & noise coupling. Total BOM cost could be reduced by employing 2-layer PCB along with the elimination of damping resistors, EMI prevention components, etc. Advantages including, but not limited to, less PCB space, shorter lead time, and higher / reliable production yield.

Data Sheet

  • Flyer and Brochure

  •   Name Published date Online certificate
  • 2017新唐科技NuMicro微控制器新產品與應用研討會_基於Arm Mbed之物聯網全面解決方案&NuMicro創新方案 Fri Dec 01 11:18:00 CST 2017
  • Data Sheet

  • File name Version Update Download
  • N3290x Data Sheet revision A5.1 5.1  Wed Mar 05 13:39:18 CST 2014
  • Development Tool

  • File name Version Update Download
  • NuMaker_NuWicam V1.0  Mon Oct 03 17:22:07 CST 2016
  • Online Training

  •   Name Published date Online certificate
  • 2017新唐科技NuMicro微控制器新產品與應用研討會_基於Arm Mbed之物聯網全面解決方案&NuMicro創新方案 Fri Dec 01 11:18:00 CST 2017

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Part No. Check Disty Raw NAND I/F, ECC bits NAND Flash, No. of ECC bits CPU Max Speed I Cache D Cache SRAM Stacked SDRAM (bit) SPI Flash I/F SD / SDIO 1.1 Host (12 Mbps) USB 2.0 Host (480 Mbps) Device (FS / HS) 2D GFX JPEG Codec Video Codec RGB Color (bits) Max. Resolution SAR ADC 24-bit Σ-Δ ADC ADC for MIC Input Touch Panel (Wire) Stereo DAC (bits) JTAG Ethernet 10/100 MAC CMOS Sensor1 GPIO (Max) UART I2C SPI RTC PWM TV Output I2S Core Voltage (V) I/O Voltage (V) Package Status I/O I2S/ AC97 ADC Operating Temp. Range (°C ) SDRAM NOR Flash SPI Flash, No. of I/O Pins ATAPI USB 2.0 HS Device 2D Graphics TFT LCD Speed (Samples per second) Touch Screen Controller LVD/LVR External Bus Interface KPI PS2 PCI Master
N32905U1DN Check Disty None 15   926 200 MHz 8K 8K 8K 16Mx16 DDR Y 3(one hardware host controller) 1   HS   Y MJPEG Codec(Motion JPEG Codec, VGA 30fps) 18 VGA(640x480) Y   Y 4 16 Y   Y(CCIR601 / CCIR656 I/F, 2M pixel) 64 2 Y 2(Only one hardware SPI controller to support two SPI device with two chip selection signals) Y 4   Y 1.8 3.3 LQFP-128 (MCP) Mass Production                                    

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