33#define ADC_CH_0_MASK (1UL << 0)
34#define ADC_CH_1_MASK (1UL << 1)
35#define ADC_CH_2_MASK (1UL << 2)
36#define ADC_CH_3_MASK (1UL << 3)
37#define ADC_CH_4_MASK (1UL << 4)
38#define ADC_CH_5_MASK (1UL << 5)
39#define ADC_CH_6_MASK (1UL << 6)
40#define ADC_CH_7_MASK (1UL << 7)
41#define ADC_CH_8_MASK (1UL << 8)
42#define ADC_CH_9_MASK (1UL << 9)
43#define ADC_CH_10_MASK (1UL << 10)
44#define ADC_CH_11_MASK (1UL << 11)
45#define ADC_CH_BG_MASK (1UL << 16)
46#define ADC_CH_TS_MASK (1UL << 17)
47#define ADC_CMP_LESS_THAN (0UL)
48#define ADC_CMP_GREATER_OR_EQUAL_TO (ADC_CMP0_CMPCOND_Msk)
49#define ADC_TRIGGER_BY_EXT_PIN (0UL)
50#define ADC_TRIGGER_BY_PWM (ADC_CTL_HWTRGSEL_Msk)
51#define ADC_LOW_LEVEL_TRIGGER (0UL << ADC_CTL_HWTRGCOND_Pos)
52#define ADC_HIGH_LEVEL_TRIGGER (1UL << ADC_CTL_HWTRGCOND_Pos)
53#define ADC_FALLING_EDGE_TRIGGER (2UL << ADC_CTL_HWTRGCOND_Pos)
54#define ADC_RISING_EDGE_TRIGGER (3UL << ADC_CTL_HWTRGCOND_Pos)
55#define ADC_ADF_INT (ADC_STATUS0_ADIF_Msk)
56#define ADC_CMP0_INT (ADC_STATUS0_ADCMPF0_Msk)
57#define ADC_CMP1_INT (ADC_STATUS0_ADCMPF1_Msk)
58#define ADC_INPUT_MODE_SINGLE_END (0UL << ADC_CTL_DIFFEN_Pos)
59#define ADC_INPUT_MODE_DIFFERENTIAL (1UL << ADC_CTL_DIFFEN_Pos)
60#define ADC_OPERATION_MODE_SINGLE (0UL << ADC_CTL_OPMODE_Pos)
61#define ADC_OPERATION_MODE_SINGLE_CYCLE (2UL << ADC_CTL_OPMODE_Pos)
62#define ADC_OPERATION_MODE_CONTINUOUS (3UL << ADC_CTL_OPMODE_Pos)
63#define ADC_DMODE_OUT_FORMAT_UNSIGNED (0UL << ADC_CTL_DMOF_Pos)
64#define ADC_DMODE_OUT_FORMAT_2COMPLEMENT (1UL << ADC_CTL_DMOF_Pos)
80#define ADC_GET_CONVERSION_DATA(adc, u32ChNum) ( ADC->DAT[u32ChNum] & ADC_DAT0_RESULT_Msk)
92#define ADC_GET_INT_FLAG(adc, u32Mask) (ADC->STATUS0 & (u32Mask))
104#define ADC_CLR_INT_FLAG(adc, u32Mask) (ADC->STATUS0 = (ADC->STATUS0 & ~(ADC_STATUS0_ADIF_Msk | \
105 ADC_STATUS0_ADCMPF0_Msk | \
106 ADC_STATUS0_ADCMPF1_Msk)) | (u32Mask))
116#define ADC_IS_BUSY(adc) (ADC->STATUS0 & ADC_STATUS0_BUSY_Msk ? 1 : 0)
127#define ADC_IS_DATA_OVERRUN(adc, u32ChNum) (ADC->STATUS1 & ( 1 << (ADC_STATUS1_OV_Pos + u32ChNum)) ? 1 : 0)
138#define ADC_IS_DATA_VALID(adc, u32ChNum) (ADC->STATUS1 & ( 1 << (ADC_STATUS1_VALID_Pos + u32ChNum)) ? 1 : 0)
146#define ADC_POWER_DOWN(adc) (ADC->CTL &= ~ADC_CTL_ADCEN_Msk)
154#define ADC_POWER_ON(adc) (ADC->CTL |= ADC_CTL_ADCEN_Msk)
171#define ADC_ENABLE_CMP0(adc, \
175 u32MatchCount) (ADC->CMP[0] = ((u32ChNum) << ADC_CMP0_CMPCH_Pos) | \
177 ((u32Data) << ADC_CMP0_CMPDAT_Pos) | \
178 (((u32MatchCount) - 1) << ADC_CMP0_CMPMCNT_Pos) |\
179 ADC_CMP0_ADCMPEN_Msk)
186#define ADC_DISABLE_CMP0(adc) (ADC->CMP[0] = 0)
203#define ADC_ENABLE_CMP1(adc, \
207 u32MatchCount) (ADC->CMP[1] = ((u32ChNum) << ADC_CMP1_CMPCH_Pos) | \
209 ((u32Data) << ADC_CMP1_CMPDAT_Pos) | \
210 ((u32MatchCount - 1) << ADC_CMP1_CMPMCNT_Pos) |\
211 ADC_CMP1_ADCMPEN_Msk)
218#define ADC_DISABLE_CMP1(adc) (ADC->CMP[1] = 0)
227#define ADC_SET_INPUT_CHANNEL(adc, u32Mask) (ADC->CHEN = (ADC->CHEN & ~ADC_CHEN_CHEN_Msk) | (u32Mask))
235#define ADC_START_CONV(adc) (ADC->CTL |= ADC_CTL_SWTRG_Msk)
243#define ADC_STOP_CONV(adc) (ADC->CTL &= ~ADC_CTL_SWTRG_Msk)
254#define ADC_SET_DMOF(adc, u32Format) (ADC->CTL = (ADC->CTL & ~ADC_CTL_DMOF_Msk) | u32Format)
262#define ADC_ENABLE_PDMA(adc) (ADC->CTL |= ADC_CTL_PDMAEN_Msk)
270#define ADC_DISABLE_PDMA(adc) (ADC->CTL &= ~ADC_CTL_PDMAEN_Msk)
278#define ADC_GET_PDMA_DATA(adc) ( ADC->CURDAT & ADC_CURDAT_CURDAT_Msk)
281 uint32_t u32InputMode,
void ADC_EnableHWTrigger(ADC_T *adc, uint32_t u32Source, uint32_t u32Param)
Configure the hardware trigger condition and enable hardware trigger.
void ADC_Close(ADC_T *adc)
Disable ADC module.
void ADC_Open(ADC_T *adc, uint32_t u32InputMode, uint32_t u32OpMode, uint32_t u32ChMask)
This API configures ADC module to be ready for convert the input from selected channel.
void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask)
Disable the interrupt(s) selected by u32Mask parameter.
void ADC_DisableHWTrigger(ADC_T *adc)
Disable hardware trigger ADC function.
void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask)
Enable the interrupt(s) selected by u32Mask parameter.