37 CLK->APBCLK0 &= (~CLK_APBCLK0_CLKOCKEN_Msk);
58void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
67 CLK->CLKSEL1 = (
CLK->CLKSEL1 & (~CLK_CLKSEL1_CLKOSEL_Msk)) | u32ClkSrc;
77 SCB->SCR = SCB_SCR_SLEEPDEEP_Msk;
90 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
168 uint32_t u32Freq =0, u32PLLSrc;
169 uint32_t u32NO,u32NF,u32NR,u32PllReg;
171 u32PllReg =
CLK->PLLCTL;
200 u32Freq = (((u32PLLSrc >> 2) * u32NF) / (u32NR * u32NO) << 2);
212 uint32_t u32ClkSrc,u32NR, u32NF,u32Register;
239 u32NF = u32Hclk / 1000000;
240 u32NR = u32ClkSrc / 1000000;
241 while( u32NR>(0xF+2) || u32NF>(0xFF+2) )
246 CLK->PLLCTL = u32Register | ((u32NR - 2)<<9) | (u32NF - 2) ;
271 CLK->CLKDIV0 = (
CLK->CLKDIV0 & ~CLK_CLKDIV0_HCLKDIV_Msk) | u32ClkDiv;
272 CLK->CLKSEL0 = (
CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLKSEL_Msk) | u32ClkSrc;
458 uint32_t u32tmp=0,u32sel=0,u32div=0;
463 u32tmp = *(
volatile uint32_t *)(u32div);
465 *(
volatile uint32_t *)(u32div) = u32tmp;
471 u32tmp = *(
volatile uint32_t *)(u32sel);
473 *(
volatile uint32_t *)(u32sel) = u32tmp;
488 CLK->PWRCTL |= u32ClkMask;
502 CLK->PWRCTL &= ~u32ClkMask;
657 uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32CLK_SRC;
658 uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR;
674 u32PllSrcClk =
__HXT;
705 u32PllFreq = u32PllFreq << 1;
710 u32PllFreq = u32PllFreq << 2;
719 u32Min = (uint32_t) - 1;
722 for(; u32NR <= 33; u32NR++)
724 u32Tmp = u32PllSrcClk / u32NR;
725 if((u32Tmp > 1600000) && (u32Tmp < 16000000))
727 for(u32NF = 2; u32NF <= 513; u32NF++)
729 u32Tmp2 = u32Tmp * u32NF;
730 if((u32Tmp2 >= 200000000) && (u32Tmp2 <= 500000000))
732 u32Tmp3 = (u32Tmp2 > u32PllFreq) ? u32Tmp2 - u32PllFreq : u32PllFreq - u32Tmp2;
749 CLK->PLLCTL = u32CLK_SRC | (u32NO << 14) | ((u32MinNR - 2) << 9) | (u32MinNF - 2);
755 return u32PllSrcClk / ((u32NO + 1) * u32MinNR) * u32MinNF;
761 CLK->PLLCTL = CLK_PLLCTL_84MHz_HXT;
792 CLK->CLKSEL0 = (
CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc ;
810 SysTick->VAL = (0x00);
811 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
814 while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0)
816 if(--u32TimeOutCnt == 0)
825 if(u32TimeOutCnt == 0)
850 uint32_t u32Ret = 1U;
854 while((
CLK->STATUS & u32ClkMask) != u32ClkMask)
856 if(--u32TimeOutCnt == 0)
863 if(u32TimeOutCnt == 0)
890 SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
892 CLK->CLKSEL0 = (
CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
895 SysTick->LOAD = u32Count;
901 SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;
NUC472/NUC442 peripheral access layer header file. This file contains all the peripheral register's d...
#define CLK_PWRCTL_LXTEN_Msk
#define CLK_PLLCTL_INDIV_Pos
#define CLK_PLLCTL_FBDIV_Msk
#define CLK_PLLCTL_PLLSRC_Msk
#define CLK_STATUS_PLLSTB_Msk
#define CLK_PWRCTL_PDEN_Msk
#define CLK_CLKOCTL_CLKOEN_Msk
#define CLK_PLLCTL_INDIV_Msk
#define CLK_APBCLK0_CLKOCKEN_Msk
#define CLK_CLKSEL0_HCLKSEL_Msk
#define CLK_PLLCTL_PD_Msk
#define CLK_PWRCTL_HIRCEN_Msk
#define CLK_PLLCTL_PLLSRC_Pos
#define CLK_PWRCTL_PDWKDLY_Msk
#define CLK_PLLCTL_OUTDV_Pos
#define CLK_CLKSEL0_PCLKSEL_Msk
#define CLK_PWRCTL_HXTEN_Msk
#define CLK_PLLCTL_OUTDV_Msk
#define CLK_STATUS_HXTSTB_Msk
#define CLK_PLLCTL_OE_Msk
#define CLK_STATUS_HIRCSTB_Msk
#define CLK_CLKOCTL_DIV1EN_Pos
#define CLK_CLKSEL0_STCLKSEL_HCLK
#define CLK_PLLCTL_PLLSRC_HXT
#define CLK_PLLCTL_50MHz_HIRC
#define MODULE_CLKSEL_Msk(x)
#define CLK_CLKDIV0_HCLK(x)
#define CLK_CLKSEL0_HCLKSEL_PLL
#define CLK_PLLCTL_PLLSRC_HIRC
#define MODULE_CLKSEL_Pos(x)
#define MODULE_CLKDIV_Pos(x)
#define MODULE_IP_EN_Pos(x)
#define MODULE_CLKDIV_Msk(x)
void CLK_Idle(void)
Enter to Idle mode.
uint32_t CLK_GetPCLKFreq(void)
This function get PCLK frequency. The frequency unit is Hz.
void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
This function set SysTick clock source.
uint32_t CLK_GetHCLKFreq(void)
Get HCLK frequency.
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
This function set PLL frequency.
void CLK_DisableCKO(void)
Disable frequency output function.
void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
This function enable module clock.
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
This function enable frequency divider module clock, enable frequency divider clock function and conf...
void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
This function disable module clock.
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
This function check selected clock source status.
uint32_t CLK_GetLXTFreq(void)
Get external low speed crystal clock frequency.
void CLK_PowerDown(void)
Enter to Power-down mode.
void CLK_DisablePLL(void)
This function disable PLL.
uint32_t CLK_GetCPUFreq(void)
Get CPU frequency.
int32_t CLK_SysTickDelay(uint32_t us)
This function execute delay function.
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set HCLK clock source and HCLK clock divider.
void CLK_DisableXtalRC(uint32_t u32ClkMask)
This function disable clock source.
void CLK_DisableSysTick(void)
Disable System Tick counter.
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set selected module clock source and module clock divider.
void CLK_EnableXtalRC(uint32_t u32ClkMask)
This function enable clock source.
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
Enable System Tick counter.
uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
Set HCLK frequency.
uint32_t CLK_GetPLLClockFreq(void)
This function get PLL frequency. The frequency unit is Hz.
uint32_t CLK_GetHXTFreq(void)
Get external high speed crystal clock frequency.
void SystemCoreClockUpdate(void)
Updates the SystemCoreClock with current core Clock retrieved from CPU registers.