20#define OHCI_BASE OHCI_BASE_ADDR
21#define HC_REVISION (OHCI_BASE+0x00)
22#define HC_CONTROL (OHCI_BASE+0x04)
23#define HC_CMD_STATUS (OHCI_BASE+0x08)
24#define HC_INT_STATUS (OHCI_BASE+0x0C)
25#define HC_INT_ENABLE (OHCI_BASE+0x10)
26#define HC_INT_DISABLE (OHCI_BASE+0x14)
27#define HC_HCCA (OHCI_BASE+0x18)
28#define HC_PERIOD_CURED (OHCI_BASE+0x1C)
29#define HC_CTRL_HEADED (OHCI_BASE+0x20)
30#define HC_CTRL_CURED (OHCI_BASE+0x24)
31#define HC_BULK_HEADED (OHCI_BASE+0x28)
32#define HC_BULK_CURED (OHCI_BASE+0x2C)
33#define HC_DONE_HEAD (OHCI_BASE+0x30)
34#define HC_FM_INTERVAL (OHCI_BASE+0x34)
35#define HC_FM_REMAINING (OHCI_BASE+0x38)
36#define HC_FM_NUMBER (OHCI_BASE+0x3C)
37#define HC_PERIOD_START (OHCI_BASE+0x40)
38#define HC_LS_THRESHOLD (OHCI_BASE+0x44)
39#define HC_RH_DESCRIPTORA (OHCI_BASE+0x48)
40#define HC_RH_DESCRIPTORB (OHCI_BASE+0x4C)
41#define HC_RH_STATUS (OHCI_BASE+0x50)
42#define HC_RH_PORT_STATUS1 (OHCI_BASE+0x54)
43#define HC_RH_PORT_STATUS2 (OHCI_BASE+0x58)
44#define HC_RH_OP_MODE (OHCI_BASE+0x204)
53#define ED_URB_DEL 0x08
56typedef struct ohci_ed_t
63 struct ohci_ed_t *ed_prev;
71 struct ohci_ed_t *ed_rm_list;
77#define TD_CC 0xF0000000
78#define TD_CC_GET(td_p) ((td_p >>28) & 0x0F)
79#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0FFFFFFF) | (((cc) & 0x0F) << 28)
80#define TD_EC 0x0C000000
82#define TD_T_DATA0 0x02000000
83#define TD_T_DATA1 0x03000000
84#define TD_T_TOGGLE 0x00000000
85#define TD_R 0x00040000
86#define TD_DI 0x00E00000
87#define TD_DI_SET(X) (((X) & 0x07)<< 21)
88#define TD_DP 0x00180000
89#define TD_DP_SETUP 0x00000000
90#define TD_DP_IN 0x00100000
91#define TD_DP_OUT 0x00080000
93#define TD_ISO 0x00010000
94#define TD_DEL 0x00020000
97#define TD_CC_NOERROR 0x00
99#define TD_CC_BITSTUFFING 0x02
100#define TD_CC_DATATOGGLEM 0x03
101#define TD_CC_STALL 0x04
102#define TD_DEVNOTRESP 0x05
103#define TD_PIDCHECKFAIL 0x06
104#define TD_UNEXPECTEDPID 0x07
105#define TD_DATAOVERRUN 0x08
106#define TD_DATAUNDERRUN 0x09
107#define TD_BUFFEROVERRUN 0x0C
108#define TD_BUFFERUNDERRUN 0x0D
109#define TD_NOTACCESSED 0x0E
114typedef struct ohci_td_t
124 struct ohci_td_t *next_dl_td;
130#define OHCI_ED_SKIP (1 << 14)
140typedef struct ohci_hcca
142 uint32_t int_table[NUM_INTS];
153#define MAX_ROOT_PORTS 2
165 uint32_t HcCommandStatus;
166 uint32_t HcInterruptStatus;
167 uint32_t HcInterruptEnable;
168 uint32_t HcInterruptDisable;
171 uint32_t HcPeriodCurrentED;
172 uint32_t HcControlHeadED;
173 uint32_t HcControlCurrentED;
174 uint32_t HcBulkHeadED;
175 uint32_t HcBulkCurrentED;
178 uint32_t HcFmInterval;
179 uint32_t HcFrameRemaining;
181 uint32_t HcPeriodicStart;
182 uint32_t HcLSThreshold;
184 struct ohci_roothub_regs
189 uint32_t portstatus[MAX_ROOT_PORTS];
192typedef struct ohci_regs OHCI_REGS_T;
200#define OHCI_CTRL_CBSR (3 << 0)
201#define OHCI_CTRL_PLE (1 << 2)
202#define OHCI_CTRL_IE (1 << 3)
203#define OHCI_CTRL_CLE (1 << 4)
204#define OHCI_CTRL_BLE (1 << 5)
205#define OHCI_CTRL_HCFS (3 << 6)
206#define OHCI_CTRL_IR (1 << 8)
207#define OHCI_CTRL_RWC (1 << 9)
208#define OHCI_CTRL_RWE (1 << 10)
211#define OHCI_USB_RESET (0 << 6)
212#define OHCI_USB_RESUME (1 << 6)
213#define OHCI_USB_OPER (2 << 6)
214#define OHCI_USB_SUSPEND (3 << 6)
219#define OHCI_HCR (1 << 0)
220#define OHCI_CLF (1 << 1)
221#define OHCI_BLF (1 << 2)
222#define OHCI_OCR (1 << 3)
223#define OHCI_SOC (3 << 16)
231#define OHCI_INTR_SO (1 << 0)
232#define OHCI_INTR_WDH (1 << 1)
233#define OHCI_INTR_SF (1 << 2)
234#define OHCI_INTR_RD (1 << 3)
235#define OHCI_INTR_UE (1 << 4)
236#define OHCI_INTR_FNO (1 << 5)
237#define OHCI_INTR_RHSC (1 << 6)
238#define OHCI_INTR_OC (1 << 30)
239#define OHCI_INTR_MIE 0x80000000
243typedef struct virt_root_hub
257#define RH_INTERFACE 0x0100
258#define RH_ENDPOINT 0x0200
259#define RH_OTHER 0x0300
260#define RH_CLASS 0x2000
261#define RH_VENDOR 0x4000
264#define RH_GET_STATUS 0x8000
265#define RH_CLEAR_FEATURE 0x0001
266#define RH_SET_FEATURE 0x0003
267#define RH_SET_ADDRESS 0x0005
268#define RH_GET_DESCRIPTOR 0x8006
269#define RH_SET_DESCRIPTOR 0x0007
270#define RH_GET_CONFIGURATION 0x8008
271#define RH_SET_CONFIGURATION 0x0009
272#define RH_GET_STATE 0x8002
273#define RH_GET_INTERFACE 0x800A
274#define RH_SET_INTERFACE 0x000B
275#define RH_SYNC_FRAME 0x800C
277#define RH_SET_EP 0x0020
281#define RH_PORT_CONNECTION 0x00
282#define RH_PORT_ENABLE 0x01
283#define RH_PORT_SUSPEND 0x02
284#define RH_PORT_OVER_CURRENT 0x03
285#define RH_PORT_RESET 0x04
286#define RH_PORT_POWER 0x08
287#define RH_PORT_LOW_SPEED 0x09
289#define RH_C_PORT_CONNECTION 0x10
290#define RH_C_PORT_ENABLE 0x11
291#define RH_C_PORT_SUSPEND 0x12
292#define RH_C_PORT_OVER_CURRENT 0x13
293#define RH_C_PORT_RESET 0x14
296#define RH_C_HUB_LOCAL_POWER 0x00
297#define RH_C_HUB_OVER_CURRENT 0x01
299#define RH_DEVICE_REMOTE_WAKEUP 0x00
300#define RH_ENDPOINT_STALL 0x01
310#define RH_PS_CCS 0x00000001
311#define RH_PS_PES 0x00000002
312#define RH_PS_PSS 0x00000004
313#define RH_PS_POCI 0x00000008
314#define RH_PS_PRS 0x00000010
315#define RH_PS_PPS 0x00000100
316#define RH_PS_LSDA 0x00000200
317#define RH_PS_CSC 0x00010000
318#define RH_PS_PESC 0x00020000
319#define RH_PS_PSSC 0x00040000
320#define RH_PS_OCIC 0x00080000
321#define RH_PS_PRSC 0x00100000
324#define RH_HS_LPS 0x00000001
325#define RH_HS_OCI 0x00000002
326#define RH_HS_DRWE 0x00008000
327#define RH_HS_LPSC 0x00010000
328#define RH_HS_OCIC 0x00020000
329#define RH_HS_CRWE 0x80000000
332#define RH_B_DR 0x0000FFFF
333#define RH_B_PPCM 0xFFFF0000
336#define RH_A_NDP (0xFF)
337#define RH_A_PSM (1 << 8)
338#define RH_A_NPS (1 << 9)
339#define RH_A_DT (1 << 10)
340#define RH_A_OCPM (1 << 11)
341#define RH_A_NOCP (1 << 12)
342#define RH_A_POTPGT (0xFF000000)
345#define min(a,b) (((a)<(b))?(a):(b))
370 int ohci_int_load[32];
373 ED_T *ed_controltail;
386typedef struct ohci_device
395#define usb_to_ohci(usb) ((OHCI_DEVICE_T *)(usb)->hcpriv)
HIDDEN_SYMBOLS struct usb_device USB_DEV_T