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N32926U1DN

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The N32926U1DN is specially designed for accelerating video/audio streaming performance, when H.264 codec and MJPEG codec are mainly used for constructing the arts used in video streaming and the hardware AAC accelerator and the sound processor are used for the corresponding audio streaming in the cloud multimedia streaming applications. The embedded video codec engines and audio compression/decompression accelerator to enhance performance while off-loading the CPU to save power consumption.

The N32926U1DN is built on the ARM926EJ-S CPU core and integrated with video decoder (H.264) , Ethernet MAC, JPEG codec, CMOS sensor interface, 32-channel SPU (Sound Processing Unit) , ADC, DAC, & TV encoder, for meeting various kinds of application needs while saving the BOM cost. The combination of ARM926 @ 240MHz, DDR2, H.264 codec and AAC accelerator, SDIO host controller & USB2.0 HS Host/Device makes the N32926U1DN the best choice for video/audio streaming devices.

The N32926U1DN could be also ported under Linux OS to leverage the driver availability of emerging functionalities, like Wi-Fi, browser, etc. On the other hand, the open source code environment also gives the product development more flexibility. Nuvoton’s continuous optimizations at Linux provide customers with a cost-effective video/audio streaming solution. Moreover, the 3rd parties USB and SDIO Wi-Fi modules are introduced to best utilize in the Wi-Fi streaming application with devices like smart phones, tablets, notebooks, or smart TV etc.

Maximum resolution for the N32926U1DN is D1 (720x480) @ TV output & 1024x768 @ TFT LCD panel. With increasing popularity of the video streaming resolutions, the H.264 is the best fit for the limited bandwidth application that requires smaller data rate for high-resolution video. The N32926U1DN is well designed in terms of cost/performance for the video/audio streaming market where Wi-Fi, Ethernet or proprietary RF is extensively used. For 2.4GHz proprietary applications, the hardware CRC generator and checking engines will off-load CPU loading to save the power consumption. Moreover, the hardware channel coding engine including scrambler, inter-leaver, Reed-Solomon outer codec and convolutional inner codec engines are used for more reliable wireless video/audio data streaming in the crowd 2.4GHz ISM band environment.

To reduce system complexity while cutting the BOM cost, the N32926U1DN also comes with a 128-pin MCP (Multi-Chip Package) in LQFP. The 32Mbitx16 DDR2 is stacked inside the MCP to ensure higher performance and minimize the system design efforts, like EMI, noise coupling. Total BOM cost could be cut by employing 2-layer PCB along with the elimination of damping resistors, EMI prevention components, & with less board space.

Data Sheet

  • Flyer and Brochure

  •   Name Published date Online certificate
  • 2017新唐科技NuMicro微控制器新產品與應用研討會_基於Arm Mbed之物聯網全面解決方案&NuMicro創新方案 2017/12/01
  • Data Sheet

  • File name Version Update Download
  • N3292x Data Sheet - A3 (web) 3.0  2014/03/05
  • Online Training

  •   Name Published date Online certificate
  • 2017新唐科技NuMicro微控制器新產品與應用研討會_基於Arm Mbed之物聯網全面解決方案&NuMicro創新方案 2017/12/01

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Part No. Check Disty Raw NAND I/F, ECC bits NAND Flash, No. of ECC bits CPU Max Speed I Cache D Cache SRAM Stacked SDRAM (bit) SPI Flash I/F SD / SDIO 1.1 Host (12 Mbps) USB 2.0 Host (480 Mbps) Device (FS / HS) 2D GFX JPEG Codec Video Codec RGB Color (bits) Max. Resolution SAR ADC 24-bit Σ-Δ ADC ADC for MIC Input Touch Panel (Wire) Stereo DAC (bits) JTAG Ethernet 10/100 MAC CMOS Sensor1 GPIO (Max) UART I2C SPI RTC PWM TV Output I2S Core Voltage (V) I/O Voltage (V) Package Status I/O I2S/ AC97 ADC Operating Temp. Range (°C ) SDRAM NOR Flash SPI Flash, No. of I/O Pins ATAPI USB 2.0 HS Device 2D Graphics TFT LCD Speed (Samples per second) Touch Screen Controller LVD/LVR External Bus Interface KPI PS2 PCI Master
N32926U1DN Check Disty 24   926 240 MHz 8K 8K 8K 32Mx16 DDR2 Y 3(two hardware host controllers) 1 1 HS   Y H.264 Codec MJPEG Codec 24 XGA(1024 x 768) Y(supports 12-bit SARADC)   Y(support optional channel for audio line-in) 4/5 16 Y Y Y(CCIR601 / CCIR656 I/F, 3M pixel) 80 2 1 2(Only one hardware SPI controller to support two SPI device with two chip selection signals) Y 4 Y Y 1.2 3.3 LQFP-128 (MCP) Mass Production                                    

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