1. ARM CORTEX™-M0 CORE Q1: Interrupt cycle from interrupt happens to the first instruction of ISR?
A1: Total 24 cycles.
Q2: What is the HCLK?
A2: It is the clock of AHB bus.
Q3: What is the APB arbiter?
A3: To judge the priority of APB peripherals.
Q4: What are the AHB , APB and AHB-Lite?
A4: AHB means the Advanced High-Performance Bus, APB means the Advanced Peripheral Bus, and AHB-Lite is a subset of the full AHB specification. For further details, please visit the ARM® website http://infocenter.arm.com/help/index.jsp.
Q5: How to clarify the hard fault exception?
A5: Please add the code as below and set the breakpoint at __NOP. User can step run to clarify the hardfault issue after exiting HardFault_Handler.
void HardFault_Handler(void)
{
__NOP();
} |
Q6: What is instruction cycle of Cortex™-M0 ?
A6: Please refer the Cortex™ -M0 Technical Reference Manual from the ARM® website
http://infocenter.arm.com/help/index.jsp.
Q7: Does the chip have a unique CPUID? How to do if the user wants to use an unique ID to encrypt his chip?
A7: No, user can write a number in chip's given address of APROM.
Q8: What is NVIC? How many levels of priority it supports?
A8: NVIC is the Nested Vectored Interrupt Controller, and it supports 4 levels of priority.
2. SYSTEM MANAGERQ1: Does NuMicro™ family series support the external SRAM through the I/O pins?
A1: Partially supported. Please check the selection guide of NuMicro™ family to check which devices can support the external bus interface (EBI).
Q2: How to enter the sleep (idle mode) and deep sleep mode (power down mode)?
A2: Please follow the commands as below to enter the sleep and deep sleep mode.
| Sleep mode |
Deep Sleep mode |
UNLOCKREG();
SCB->SCR = 4;
SYSCLK->PWRCON.WINT_EN = 0;
SYSCLK->PWRCON.PD_WAIT_CPU = 1;
SYSCLK->PWRCON.PWR_DOWN = 0;
LOCKREG();
__WFI(); |
UNLOCKREG();
SCB->SCR = 4;
SYSCLK->PWRCON.WINT_EN = 0;
SYSCLK->PWRCON.PD_WAIT_CPU = 1;
SYSCLK->PWRCON.PWR_DOWN = 1;
LOCKREG();
__WFI(); |
Q3: How to wake up the CPU from sleep mode?
A3: CPU can be waked up from sleep mode by all interrupt sources.
Q4: How to wake up the CPU from deep sleep mode?
A4: CPU can be waked up from deep sleep mode only by the interrupt source s as below:
GPIO, USB, UART (/C TS pin) , WDT, CAN, ACMP, BOD and RTC.
Q5: How to set the registers of peripheral?
A5: Please enable the peripheral clock at first and then set the related registers of peripheral.
Q6: What are the wake-up time for the external 12 MHz crystal and the internal 22 MHz RC at VDD =2.5V?
A6: The wake-up time is 2ms for external 12 MHz crystal and 40us for internal 22 MHz RC.
3. CLOCK CONTROLLER
Q1: Does NuMicro™ family provide the clock output pin to monitor the internal clock? A1: Yes, it does. But it depends on the part number.
Q2: Does NuMicro™ family provide the flag to monitor the internal clock is stable or not?A2: Yes, but only for the new chip, please refer the related Technical Reference Manual for further details.
Q3: Does the internal 22 MHz RC can be set as the clock source of PLL to generate the 48 MHz for the USB controller?A3: Not recommended, because the internal 22 MHz RC precision will generate the difference for the 48 MHz output of PLL.
Q4: How to set USB = 48 MHz, HCLK = 32 MHz for CPU and SPICLK = 16 MHz for SPI Master?A4:
- Enable PLL and set PLL output = 96 MHz
- USB = PLL output / 2 = 48 MHz
- HCLK = PLL output / 3 = 32 MHz
- SPICLK = HCLK / 2 = 16 MHz
Q5: Which peripherals have the independent clock sources can be selected?A5: Watchdog Timer, ADC converter, Timer, UART, CAN, PWM and I2S.
Q6: Which clocks can still work in deep sleep mode (power down mode)?A6: The external 32 KHz crystal and the internal 10 KHz RC.
4. USB DEVICE CONTROLLER
Q1: Does all NuMicro™ family chips provide the USB functions?A1: No, only NUC100 series provide the USB functions, but M051 series doesn't provide the USB functions.
Q2: Does it always use the interrupt for USB HID?A2: Yes.
Q3: How to disable the USB 1.5 Kohm pull high resistor?A3: Disable the control bit in USB register.
Q4: What sample codes of USB can be provided by Nuvoton?A4: HID, HID Transfer, UAC (USB Audio Class), UVC, Virtual COM Port, UDC (USB Device Control), HID IO.
Q5: What are the transfer types of USB?A5: Control, Interrupt, Bulk, Isochronous.
Q6: How much endpoints can be provided for the USB device in NUC100 series?A6: It provides 6 endpoints for the USB device.
Q7: What kinds of USB that NUC100 series provide?A7: It just provides the USB Device (USB2.0 full speed), but Nuvoton will create the new chips that include the USB Host and USB Device (USB2.0 high speed) in future.
Q8: Does NuMicro ™ family chip pass the USB certification? A8: Yes, please visit the Nuvoton NuMicro™ family website www.nuvoton.com/NuMicro
Q9: Does Nuvoton can provide the VID and PID for customers?A9: No, the customers need to apply for the VID and PID for your USB applications by yourself.
5. GENERAL PURPOSE I/O
Q1: How many external interrupt sources does the NuMicro™ family chip can support?A1: All of the GPIO can generate the external interrupt.
Q2: What is the machine cycle number for the GPIO toggling?A2: There are about 11 machine cycles for medium density of NUC100 series, but about 7 machine cycles for low density of NUC100 series and M051 series.
Q3: What is the default state of GPIO after reset?A3: It is in Quasi-bidirectional mode with weakly pull high (>100K).
Q4: Are all of GPIO the multifunction pins?A4: No, but most part of GPIO are the multifunction pins. Please refer the Pin Description in the datasheet or TRM of the chip.
Q5: Do all of GPIO pins can be set as the sources to wake up chip? A5: Yes, all of GPIO pins can be set as the sources to wake up the chip.
6. 12C SERIAL INTERFACE CONTROLLER (MASTER/SLAVE)
Q1: Is one byte for I2C address? Why the I2C timing address of 24C06 EEPROM is one byte?A1: User confuses the I2C slave address and EEPROM address.
Q2: How to handle the I2C bus hung up in slave mode?
A2: Please reset the I2C peripheral by software.
Q3: What is the value for the pull-high resistor on the I2C bus?A3: Please add 4.7 kohm pull-high resistor on the I2C bus.
7. PWM GENERATOR AND CAPTURE TIMER
Q1: What are PWM and its main function?A1: PWM means the pulse-width modulation, and it is used to generate the square waveform output.
Q2: How many channels of PWM does NuMicro™ family chip can provide?
A2: There are up to eight channels of PWM in a NuMicro™ family chip, but how many channels that depends on the part number.
Q3: What are the key points of PWM generator?
A3: The key points we concern about PWM are the frequency and duty of output waveform.
Q4: Which are the clock sources of PWM generator?
A4: The clock sources of PWM generator are the system clock HCLK, the internal 22 MHz RC, the external 12 MHz and 32 KHz (NUC100 series only) crystals.
Q5: What are the resolutions of Prescaler, Timer and Divider in the PWM generator?
A5: They are the 8-bit Prescaler, 16-bit down-counting Timer, and 1, 1/2, 1/4, 1/8, 1/16 Divider.
Q6: How to create the frequency and duty of PWM waveform?
A6: The PWM frequency = the PWM clock source / ( ( P rescale r +1) * Divider * (CNR+1))and the duty ratio = (CMR+1) / (CNR+1). (CNR: 16-bit Counter Register, CMR: 16-bit Comparator Register).
Q7: What is the complementary PWM pair and which PWM channels can be combined to the complementary PWM pair?
A7: Complementary PWM pair means a pair of PWM channels that output two complementary PWM waveforms. For example, PWM channel 0 (PWM0) and channel 1 (PWM1) can be combined to the first pair of complementary PWM, PWM channel 2 (PWM2) and channel 3 (PWM3) can be combined to the second pair of complementary PWM, etc.
Q8: What are the Dead Zone generator and its features?
A8: They are built for power device protection especially for the motor driver system to avoid both of the top and bottom MOSFET be turn on simultaneously . This function generates a programmable time gap to delay the rising edges of the output waveforms on the complementary PWM pair.
Q9: When does the PWM interrupt event flag (PWMIFx) will be set by the hardware and how to clear it?
A9: The PWM interrupt event flag (PWMIFx) will be set by the hardware at the ending of each PWM cycle, it also indicates the 16-bit down-counting PWM-Timer reaches zero. This flag needs the software to write 1 back to clear it.
Q10: What is the main function of Capture channel input?
A10: The Capture channel shares the same hardware with PWM generator, and it is used to measure the high and/or low pulse width of the input waveform.
Q11: How many channels of Capture does NuMicro™ family chip can provide?
A11: Because the Capture channel shares the same hardware with PWM generator, so there are up to eight channels of Capture in a NuMicro™ family chip, but how many channels that depends on the part number.
Q12: What is the key point of Capture input?
A12: The key point of Capture input is the pulse width of input waveform that be measured, user needs to pay attention to choose the clock source of Capture due to this will affects the precision and how long is the pulse width of measurement.
Q13: When does the Capture interrupt event flag (CAPIFx) will be set by the hardware and how to clear it?
A13: In the CFL_IE = 1 (Capture Falling Latch Interrupt Enable) and/or CRL_IE = 1 (Capture Rising Latch Interrupt Enable) conditions, the Capture interrupt event flag (CAPIFx) will be set by the hardware on the edge transition (falling and/or rising) of input waveform. This flag needs the software to write 1 back to clear it.
Q14: Does the PWM controller support the duty high or duty low?
A14: No, it at least one cycle pulse width of high or low during the whole PWM cycle.
Q15: Why two different PWM Timers (ex, PWM0 and PWM1) take effect at each other when user sets registers in one of these two PWM Timers using the driver library?
A15: This is because these two PWM Timers use the same Prescaler. To set register of one PWM Timer, it will take effect at the other when user programs the code using the driver library.
Q16: What is the maximum frequency of Capture input can be measured when the system clock is 50 MHz?
A16: About 200 KHz for the frequency of Capture input.
Q17: When the CNR register can be auto-reload into down counter for Capture?A17: When the Capture interrupt event flag (CAPIFx) is be set by hardware, the value of CNR register will be loaded into the down counter.
8. REAL TIME CLCOK (RTC)
Q1: Which series chip supports the RTC controller in NuMicro™ family?A1: Only NUC100 series chip supports the RTC controller, but M051 series chip does not support it.
Q2: Wh ich is clock source of RTC controller?
A2: The clock source of RTC controller is the external 32 KHz crystal.
Q3 Does RTC controller can use the internal 10 KHz RC as its clock source?
A3: No, the clock source of RTC only comes from the external 32 KHz crystal.
Q4: Does RTC controller need to use the independent power input?
A4: No, the power of RTC controller shares with the power of whole chip. Once user powers off the chip, the RTC will be incorrect when power on the chip again.
Q5: Does RTC operate at Deep Sleep Mode?
A5: Yes, it can wake up the whole chip from Deep Sleep Mode.
Q6: Does RTC support tick mode and wake up the CPU?A6: Yes, RTC support tick interrupt to wake up CPU.
9. SERIAL PERIPHERAL INTERFACE (SPI) CONTROLLER
Q1: How many sets of SPI controller in NuMicro™ family?A1: There are u p to four sets of SPI controller in a chip of NuMicro™ family, but it depends on the part number.
Q2: Does the SPI controller support the general 4-wire SPI interface?
A2: Yes, it supports the general 4-wire SPI interface, including the Serial Clock (SPICLK), Slave Select (SPISS), Master Output/Slave Input (MOSI) and Master Input/Slave Output (MISO).
Q3: Does the SPI controller support the general SPI Mode 0 ~ 3 ?
A3: It is easy to configure the SPI registers for the idle polarity of serial clock, the clock edges to transmit data and receive data to match the general SPI Mode 0 ~ 3.
Q4: Does the SPI controller support the Master and Slave mode?
A4: Yes, it supports Master and Slave mode.
Q5: How many slave-select output pins of each SPI controller provides in Master mode?
A5: It provides two slave-select output pins for each SPI controller in Master mode.
Q6: Which is the clock source of SPI controller?
A6: The clock source of SPI controller is the system clock HCLK.
Q7: How to generate the SPI serial clock in Master mode?
A7: The serial clock output SPICLK = HCLK/(1+DIVIDER[15:0])/2, the bit field DIVIDER[15:0] is larger or equal to 1.
Q8: What is the 2-bit (2-channel) transfer mode and how to use it?
A8: The 2-bit transfer mode means that the SPI controller transmits 2-bit data output at the same edge of serial clock and at the same time it also receives 2-bit data input at the opposite edge of serial clock during a serial clock cycle. For the details, please refer the SPI application note (AN1022) for 2-bit transfer mode.
Q9: What is the limitation of 2-bit transfer mode?
A9: It only supports the single mode in 2-bit transfer mode. In this 2-bit transfer mode, the registers SPI_Tx0 and SPI_Rx0 are mapping to the channel 0 (MISOx0, MOSIx0), but the registers SPI_Tx1 and SPI_Rx1 are mapping to the channel 1 (MISOx1, MOSIx1).
Q10: What is the single and burst mode?
A10: The single mode means that the SPI controller transfers only a single Word (SPI_Tx0 and SPI_Rx0) during each transfer, but it transfers two Words (SPI_Tx0/1 and SPI_Rx0/1) during each transfer in burst mode. The single mode or burst mode can be set by the bit field Tx_NUM register.
Q11: How many bits can be transfer during each transfer?
A11: By setting the bit field Tx_BIT_LEN register, it can configure the bit length of Word to transfer from 1 to 32 bits. The maximum bit length is 32 bits in single mode, but is 64 bits in burst mode during each transfer.
Q12: What is level of slave select?
A12: By setting the SS_LVL register to decide the level of slave select.
Q13: What is automatic slave select in Master mode?
A13: It means that the SPI controller outputs the level (depends on the SS_LVL) of slave select automatically and synchronously with the serial clock when each time user triggers the SPI to transfer data.
Q14: What is the situation when user needs to control the slave select by manual? And, how to control it?
A14: It depends on the off-chip slave device, if the slave device needs to be triggered only one time by the level (decided by SS_LVL register) of slave select before a mass data transferring. You just need to set the SSR[0] (for SPISSx0 output pin) or SSR[1] (for SPISSx1 output pin) to enable the slave select output before data transferring and clear the SSR[0] or SSR[1] to disable the slave select output after data transferring.
Q15: Does SPI controller support the PDMA function?
A15: Yes, it supports the PDMA function for data transmitting and receiving on the SPI interface through PDMA channels without wasting CPU resource. But not all of NuMicro ™ family chip provide the PDMA controller, it depends on the part number.
Q16: Does SPI controller support the FIFO mode?
A16: Yes, it supports the FIFO mode for data transmitting and receiving continuously. But not all of NuMicro™ family chip provide the FIFO mode in SPI controller, it depends on the part number.
Q17: Does SPI controller can transmit/receive data continuously to speed up the data transferring?
A17: Yes, you can enable the FIFO mode or PDMA function if either of these two functions exists in your chip.
Q18: How to use FIFO mode of SPI controller?
A18: Please refer the SPI application note and sample code for FIFO mode.
Q19: How to use PDMA function with SPI controller?
A19: Please refer the SPI application note and sample code for PDMA function.
Q20: How to transmit 2 bytes data continuously?
A20: You can set the bit field Tx_BIT_LEN = 0x10 (16-bit length) and Tx_NUM = 0x0 (single mode), or you can set the bit filed Tx_BIT_LEN = 0x8 (8-bit length) and Tx_NUM = 0x1 (burst mode) to transmit 2 bytes data.
Q21: Does the SPI DIVIDER register can be set to 0 ?
A21: Not recommended. The DIVIDER value must be larger or equal to 1.
Q22: What is the maximum frequency of SPICLK in Master and Slave mode?
A22: The maximum frequency of SPICLK is 20 MHz (30 MHz for NUC122 series) in Master mode, but is 10 MHz in Slave mode.
Q23: Why SPI drive s up to eight slave devices in M aster mode?
A23: There are u p to four sets of SPI controller in a chip of NuMicro™ family and each SPI controller can drive s up to two SPI slave devices.
Q24: Does it support 3-wire SPI?A24: Yes, please refer the SPI application note and sample code for 3-wire SPI application.
10. TIMER CONTROLLER
Q1: How many Timer controllers in the NuMirco™ family?A1: There are u p to four sets of Timer controller in a chip of NuMicro™ family, but it depends on the part number. User also can use the Systick and the PWM Timer (if enable PWM Timer but disable the output) as the Timer.
Q2: Which are the clock sources of Timer controller? Does user can select these clock sources independently for each Timer controller?A2: The clock sources of Timer controller are the system clock HCLK, the internal 22 MHz RC, the external 12 MHz and 32 KHz (NUC100 series only) crystals. Yes, by setting the bit field of CLKSEL1 register user can select the different clock source for each Timer controller.
Q3: What are the resolutions of Prescaler and Timer counter in the Timer controller?A3: They are the 8-bit Prescaler and 24-bit up-counting Timer counter.
Q4: How to generate the period of Timer?A4: The time out period = (period of input clock source) * (8-bit Prescaler + 1) * (24-bit TCMP), (TCMP: Timer Compare Register).
Q5: What are the operation modes of Timer controller?A5: They are one-shot mode, periodic mode and continuous counting mode.
Q6: What is the one-shot operation mode for Timer controller?A6: The one-shot operation mode means that the Timer will stops counting when the value of 24-bit up-counting Timer counter matches the setting of TCMP (Timer Compare Register). At this moment, the Timer interrupt event flag (TIF) will be set by the hardware.
Q7: What is the periodic operation mode for Timer controller?A7: The periodic operation mode means that the Timer will resets the 24-bit Timer counter and restart to count from zero when each time the value of 24-bit up-counting Timer counter matches the setting of TCMP (Timer Compare Register). At this moment, the Timer interrupt event flag (TIF) will be set by the hardware.
Q8: What is the continuous counting operation mode for Timer controller?A8: The continuous counting operation mode means that the Timer will continuously counts from zero even when the 24-bit up-counting Timer counter is overflow. But each time the Timer interrupt event flag (TIF) will be set by the hardware when the value of 24-bit up-counting Timer counter matches the setting of TCMP (Timer Compare Register).
Q9: When does the Timer interrupt event flag (TIF) will be set by the hardware and how to clear it?A9: The Timer interrupt event flag (TIF) will be set by the hardware when the value of 24-bit up-counting Timer counter matches the setting of TCMP (Timer Compare Register). This flag needs the software to write 1 back to clear it.
11. WATCHDOG TIMER
Q1: What are the main functions of Watchdog Timer (WDT) controller?A1: The purpose of Watchdog Timer is to perform a system reset when system runs into an unknown state. User needs to clear the WDT counter before the WDT controller resets the chip if the chip is operating normally. Moreover, user also can use the WDT interrupt event flag (WTIF) if the bit WTWKE is set to wake up the CPU from the power down mode.
Q2: What are the resolutions of WDT counter in the Watchdog Timer controller?A2: 18-bit up-counting WDT counter.
Q3: How many kinds of timeout interval can be chosen in the WDT controller?A3: There are eight kinds of timeout interval that be provided in the WDT controller, they are 2^4 * T, 2^6 * T, 2^8 * T, 2^10 * T, 2^12 * T, 2^14 * T, 2^16 *T, or 2^18 * T. (T=1/WDT_CLK, WDT_CLK is the clock source of WDT).
Q4: When does the WDT interrupt event flag (WTIF) will be set by the hardware and how to clear it?A4: The WDT interrupt event flag (WTIF) will be set by the hardware when the 18-bit up-counting WDT counter is overflow at the bit that be selected for the timeout interval setting in the bit field of WTIS register. This flag needs the software to write 1 back to clear it.
Q5: How to generate the WDT interrupt?A5: If user sets the WDT interrupt enable bit WTIE, the WDT controller will generate the WDT interrupt to CPU once the interrupt event flag (WTIF) is set by hardware.
Q6: Does the WDT controller can wake up the CPU from power down mode?A6: Yes, if user sets the WDT wake up enable bit WTWKE, the WDT controller will wake up the CPU from power down mode once the interrupt event flag (WTIF) is set by hardware.
Q7: Does the WDT controller can reset the whole chip? How long is the delay time for the reset action after the WDT interrupt event flag is set?A7: Yes, if user sets the WDT reset enable bit WTRE, the WDT controller will postpones 1024 * T (T=1/WDT_CLK, WDT_CLK is the clock source of WDT) and then resets the whole chip once the interrupt event flag (WTIF) is set by hardware.
12. UART INTERFACE CONTROLLER
Q1: How to use UART /CTS to wake up the chip?A1: When the /CTS input pin changed the state from high to low or from low to high, it will generates the interrupt to wake up the chip if the interrupt is enable.
Q2: What is the difference of coding between UART high speed and low speed?A2: It is the same for high speed and low speed. The buffer length is 64 bytes for high speed, but 16 bytes for low speed.
Q3: What is the application field for LIN bus?A3: Car electrical field.
Q4: How much slaves can join the LIN bus?A4: 16 slaves are suggested in LIN specification.
Q5: How to generate a 9-bit data frame in UART function?A5: Use the parity bit function as the 9 th bit.
Q6: How to use PDMA function with UART controller?A6: Please refer the PDMA application note (AN1016) and sample code for PDMA function.
13. CONTROLLER AREA NETWORK (CAN BUS)
Q1: Is the Overload Frame different with Error Frame?A1: It is the same only in the passive error flag of Error Frame.
14. PS2 DEVICE CONTROLLER
15. I2S CONTROLLER
Q1: Is I2S able to handl e 24-bit data?A1: Yes, I2S can handle 8/16/24/32-bit data.
Q2: Where is receiving data from right or left channel in the mono mode?A2: The receiving data is from right channel.
16. ANALOG-TO-DIGITAL CONVERTER (ADC)
Q1: What is the ENOB of ADC at 600 KHz conversion rate?A1: 10 bits.
Q2: Does it support PDMA function for the ADC?A2: Yes.
Q3: How to use PDMA with ADC?A3: Please refer the ADC application note (AN1002).
Q4: Does the ADC support the audio recording function like NUC501? A4: No, it doesn't support this function.
Q5: What is the operation voltage for ADC converter?A5: The operation voltage is 3~5V for ADC converter.
Q6: How to setup the AVDD voltage?A6: The AVDD voltage should be the same as VDD, otherwise the leakage occurs. Please refer the hardware application note (AN1000).
Q7: What is timing for self-calibration?A7: After power on or switching input mode between single-end and differential.
Q8: What is band gap voltage?A8: 1.26V.
17. ANALOG COMPARATOR
18. PDMA CONTROLLER
Q1: What is PDMA controller?
A1: PDMA means the "Peripheral Direct Memory Access" controller.
Q2: What is the main function of PDMA controller?
A2: The main function of PDMA controller is to transfer data between internal memory and peripherals. It can move data from internal memory to internal memory or from internal memory to peripherals or from peripherals to internal memory through the PDMA channel without wasting the CPU resource.
Q3: What is the data width of moving data between PDMA channels?
A3: They can be set as byte, half-word or word.
Q4: How many channels of PDMA in NuMicro™ family chip?
A4: It provides up to 9 channels of PDMA in NUC100 series, but none channel in M051 series.
Q5: What kinds of peripheral that supports PDMA function in NUC100 series?
A5: They are SPI, UART, I2S and ADC peripherals but which chips have these peripherals that depend on the part number.
Q6: Does it also indicate that the data transfer had been finished in the peripheral if the event flag of PDMA block done is set by hardware?
A6: No, the PDMA block done flag be set by hardware that indicates the data transfer is finished just only in PDMA controller. After the event flag of PDMA block done is set, user needs to check the status of peripheral whether the data transfer in the peripheral had been finished or not.
Q7: Does PDMA take effect the CPU performance when CPU access peripheral?
A7: Basically, it does not take effect the CPU performance except that PDMA and CPU access the same APB bus simultaneously.
19. FLASH MEMORY CONTROLLER (FMC)
Q1: What is the Flash memory?A1: The Flash memory includes the APROM (application code), LDROM (load/boot code), Data Flash (data code) and User Configuration Word (power on setting).
Q2: What is the size of APROM?A2: It is size of 8K/16K/32K/64K/128K bytes that depend on the part number of chip.
Q3: What is the size of LDROM?A3: It is 4K bytes only.
Q4: What is the size of Data Flash?A4: It is 4K bytes only in the chip that its APROM size is 8K/16K/32K/64K, but it is configurable (512 bytes x N) in the chip that its APROM size is 128K bytes.
Q5: What is the page size of erase for the Flash memory?A5: It is 512 bytes per page to erase.
Q6: What is the data size of program for the Flash memory?A6: It is 4 bytes (a word) per data to program.
Q7: How to update the Flash memory?A7: Through the ICE, ICP, ISP, Writer or third party Writer like the High-Low.
Q8: What is ISP?A8: ISP means the "In System Programming", the target chip runs the boot/loader code of LDROM through the peripheral interface like as USB/UART/SPI/I2C... to update the internal APROM, Data Flash and User Configuration Word.
Q9: What is ICP?A9: ICP means the "In Circuit Programming", PC runs the software “NuMicro ICP Programming Tool” through the SWD (serial wire debug) port of Nu-Link circuit to update the internal APROM, LDROM, Data Flash and User Configuration Word of the target chip.
Q10: Does it can update the APROM when CPU is doing ISP procedure on the APROM code?A10: No, it does not agree to update APROM when CPU is doing ISP procedure on the APROM code.
Q11: Does it can update the LDROM when CPU is doing ISP procedure on the LDROM code?A11: No, it does not agree to update LDROM when CPU is doing ISP procedure on the LDROM code.
Q12: Does the chip can be booted from the code on the Data Flash?A12: No, chip only can be booted from the code on APROM or LDROM.
Q13: Does the chip support the code-protected for the user's program code?A13: Yes, it provides the LOCK bit on the User Configuration Word to protect the user's program code. When this LOCK bit is set, all of the data on the Flash memory will be read back as 0xFFFFFFFF.
Q14: How to unlock the LOCK bit on the User Configuration Word?A14: Only to do the "Whole Chip Erase" operation for the target chip to unlock the LOCK bit.
Q15: Does the flash support DES function?A15: No.
Q16: Which register can decide the CPU to fetch code from which boot ROM?A16: FMC Configuration Word register can decide the chip boot from APROM or LDROM.
20. ELECTRICAL CHARACTERISTICS
Q1: How much is drive and sink current and total current?A1: Please refer the absolute maximum ratings in the Technical Reference Manual file.
21. TOOLS
Q1: What are the prices of all NUC100 series tools?A1: Please contact your agent to get the tooling price.
Q2: Why does Nu-Link firmware update fails?A2: Please contact your agent or visit NuMicro™ family website to get the last version of firmware and drive.
Q3: Does Nu-Link support the other company's devices?A3: No, it only supports NuMicro™ family.
Q4: Does these files of data flash, APROM, and LDROM can merge to one file?A4: Not recommend.
Q5: Does Nu-Link support the Watch point?A5: No.
Q6: What version of Keil and IAR can support Nu-Link?A6: Keil is 3.87 version or above and IAR is 5.5 version or above.
Q7: Which companies can support the third-party Writer for NuMicro™ family chip?A7: Like the Hi-Lo, Leap or you can inquiry your agent.
Q8: What are the meanings of these words Code, RO-data, RW-data and ZI-data after code complier in Keil-MDK?A8:
- Code: Code in Flash. Shows how many bytes are occupied by code.
- RO-data: Constant data in RAM. Shows how many bytes are occupied by read-only data. This is in addition to the inline data included in the code.
- RW-data: Variable data in RAM. Shows how many bytes are occupied by read-write data.
- ZI-data: Shows how many bytes are occupied by zero-initialized data.
22. OTHERS
Q1: What is the naming rule for NUC100 series chip?A1: Please refer the naming rule as below.
Q2: Does NUC100 series support the real time OS(RTOS)?A2: Yes, uC/OS ‐ II, FreeRTOS and RTX can be supported.
Q3: Does NUC100 series support DAC in the future?A3: No, it does not support the DAC function in NUC100 series, but it will supports in N572 speech product line.
23. REVISION HISTORY
| Version |
Date |
Page / Chap. |
Description |
|
V 1.00 |
Apr. 23, 2010 |
- |
Preliminary version initial issued |
|
V 1.01 |
Feb. 21, 2011 |
All |
The second version issued |