46uint32_t
SPI_Open(
SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
48 if(u32DataWidth == 32)
67 SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk;
72 SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk;
77 SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk;
82 SYS->IPRST1 &= ~SYS_IPRST1_SPI3RST_Msk;
140 uint32_t u32ClkSrc, u32Div = 0;
171 if(u32BusClock > u32ClkSrc)
172 u32BusClock = u32ClkSrc;
174 if(u32BusClock != 0 )
176 u32Div = (u32ClkSrc / u32BusClock) - 1;
183 spi->
CLKDIV = (spi->
CLKDIV & ~SPI_CLKDIV_DIVIDER_Msk) | u32Div;
185 return ( u32ClkSrc / (u32Div+1) );
242 return (u32ClkSrc / (u32Div + 1));
322 spi->
CTL &= ~SPI_CTL_UNITIEN_Msk;
325 spi->
SSCTL &= ~SPI_SSCTL_SSINAIEN_Msk;
328 spi->
SSCTL &= ~SPI_SSCTL_SSACTIEN_Msk;
331 spi->
SSCTL &= ~SPI_SSCTL_SLVURIEN_Msk;
334 spi->
SSCTL &= ~SPI_SSCTL_SLVBEIEN_Msk;
337 spi->
SSCTL &= ~SPI_SSCTL_SLVTOIEN_Msk;
340 spi->
FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;
343 spi->
FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;
346 spi->
FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;
349 spi->
FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk;
352 spi->
FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;
NUC472/NUC442 peripheral access layer header file. This file contains all the peripheral register's d...
#define SPI_SSCTL_SSACTPOL_Msk
#define SPI_FIFOCTL_RXOVIEN_Msk
#define SPI_CTL_UNITIEN_Msk
#define SPI_FIFOCTL_RXTH_Pos
#define SPI_FIFOCTL_TXTH_Msk
#define SPI_CTL_DWIDTH_Pos
#define SPI_SSCTL_SLVTOIEN_Msk
#define SYS_IPRST1_SPI2RST_Msk
#define SPI_FIFOCTL_RXRST_Msk
#define CLK_CLKSEL1_SPI0SEL_Msk
#define SPI_FIFOCTL_TXRST_Msk
#define SPI_SSCTL_SSACTIEN_Msk
#define SYS_IPRST1_SPI1RST_Msk
#define SYS_IPRST1_SPI0RST_Msk
#define SPI_FIFOCTL_TXUFIEN_Msk
#define CLK_CLKSEL1_SPI2SEL_Msk
#define SPI_CLKDIV_DIVIDER_Msk
#define SPI_FIFOCTL_TXTH_Pos
#define SPI_SSCTL_SLVBEIEN_Msk
#define CLK_CLKSEL1_SPI3SEL_Msk
#define SPI_SSCTL_SSINAIEN_Msk
#define SPI_FIFOCTL_RXTOIEN_Msk
#define SPI_FIFOCTL_RXTHIEN_Msk
#define SPI_FIFOCTL_RXTH_Msk
#define CLK_CLKSEL1_SPI1SEL_Msk
#define SYS_IPRST1_SPI3RST_Msk
#define SPI_SSCTL_SLVURIEN_Msk
#define SPI_FIFOCTL_TXTHIEN_Msk
#define SPI_SSCTL_AUTOSS_Msk
#define CLK_CLKSEL1_SPI1SEL_PCLK
#define CLK_CLKSEL1_SPI2SEL_PCLK
#define CLK_CLKSEL1_SPI0SEL_PCLK
#define CLK_CLKSEL1_SPI3SEL_PCLK
uint32_t CLK_GetPCLKFreq(void)
This function get PCLK frequency. The frequency unit is Hz.
uint32_t CLK_GetPLLClockFreq(void)
This function get PLL frequency. The frequency unit is Hz.
#define SPI_SSINAIEN_MASK
#define SPI_SLVTOIEN_MASK
#define SPI_FIFO_TXUFIEN_MASK
#define SPI_FIFO_RXOVIEN_MASK
#define SPI_SLVBEIEN_MASK
#define SPI_FIFO_RXTOIEN_MASK
#define SPI_FIFO_RXTHIEN_MASK
#define SPI_SSACTIEN_MASK
#define SPI_SLVURIEN_MASK
#define SPI_FIFO_TXTHIEN_MASK
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
Disable FIFO related interrupts specified by u32Mask parameter.
void SPI_SetFIFOThreshold(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
Set Tx FIFO threshold and Rx FIFO threshold configurations.
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
Enable FIFO related interrupts specified by u32Mask parameter.
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
Enable the automatic slave select function. Only available in Master mode.
void SPI_DisableAutoSS(SPI_T *spi)
Disable the automatic slave select function.
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
Set the SPI bus clock. Only available in Master mode.
void SPI_Close(SPI_T *spi)
Reset SPI module and disable SPI peripheral clock.
void SPI_ClearTxFIFO(SPI_T *spi)
Clear Tx FIFO buffer.
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
This function make SPI module be ready to transfer. By default, the SPI transfer sequence is MSB firs...
uint32_t SPI_GetBusClock(SPI_T *spi)
Get the actual frequency of SPI bus clock. Only available in Master mode.
void SPI_ClearRxFIFO(SPI_T *spi)
Clear Rx FIFO buffer.