![]() |
NANO103 BSP V3.01.004
The Board Support Package for Nano103 Series
|
Modules | |
Device CMSIS Definitions | |
This file defines all structures and symbols for NANO103:
#define CLK_AHBCLK_GPIOCKEN_Msk (0x1ul << CLK_AHBCLK_GPIOCKEN_Pos) |
CLK_T::AHBCLK: GPIOCKEN Mask
#define CLK_AHBCLK_GPIOCKEN_Pos (0) |
CLK_T::AHBCLK: GPIOCKEN Position
#define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) |
CLK_T::AHBCLK: ISPCKEN Mask
#define CLK_AHBCLK_ISPCKEN_Pos (2) |
CLK_T::AHBCLK: ISPCKEN Position
#define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos) |
CLK_T::AHBCLK: PDMACKEN Mask
#define CLK_AHBCLK_PDMACKEN_Pos (1) |
CLK_T::AHBCLK: PDMACKEN Position
#define CLK_AHBCLK_SRAMCKEN_Msk (0x1ul << CLK_AHBCLK_SRAMCKEN_Pos) |
CLK_T::AHBCLK: SRAMCKEN Mask
#define CLK_AHBCLK_SRAMCKEN_Pos (4) |
CLK_T::AHBCLK: SRAMCKEN Position
#define CLK_AHBCLK_STCKEN_Msk (0x1ul << CLK_AHBCLK_STCKEN_Pos) |
CLK_T::AHBCLK: STCKEN Mask
#define CLK_AHBCLK_STCKEN_Pos (5) |
CLK_T::AHBCLK: STCKEN Position
#define CLK_APBCLK_ACMP0CKEN_Msk (0x1ul << CLK_APBCLK_ACMP0CKEN_Pos) |
CLK_T::APBCLK: ACMP0CKEN Mask
#define CLK_APBCLK_ACMP0CKEN_Pos (11) |
CLK_T::APBCLK: ACMP0CKEN Position
#define CLK_APBCLK_ADCCKEN_Msk (0x1ul << CLK_APBCLK_ADCCKEN_Pos) |
CLK_T::APBCLK: ADCCKEN Mask
#define CLK_APBCLK_ADCCKEN_Pos (28) |
CLK_T::APBCLK: ADCCKEN Position
#define CLK_APBCLK_CLKOCKEN_Msk (0x1ul << CLK_APBCLK_CLKOCKEN_Pos) |
CLK_T::APBCLK: CLKOCKEN Mask
#define CLK_APBCLK_CLKOCKEN_Pos (6) |
CLK_T::APBCLK: CLKOCKEN Position
#define CLK_APBCLK_I2C0CKEN_Msk (0x1ul << CLK_APBCLK_I2C0CKEN_Pos) |
CLK_T::APBCLK: I2C0CKEN Mask
#define CLK_APBCLK_I2C0CKEN_Pos (8) |
CLK_T::APBCLK: I2C0CKEN Position
#define CLK_APBCLK_I2C1CKEN_Msk (0x1ul << CLK_APBCLK_I2C1CKEN_Pos) |
CLK_T::APBCLK: I2C1CKEN Mask
#define CLK_APBCLK_I2C1CKEN_Pos (9) |
CLK_T::APBCLK: I2C1CKEN Position
#define CLK_APBCLK_PWM0CKEN_Msk (0x1ul << CLK_APBCLK_PWM0CKEN_Pos) |
CLK_T::APBCLK: PWM0CKEN Mask
#define CLK_APBCLK_PWM0CKEN_Pos (20) |
CLK_T::APBCLK: PWM0CKEN Position
#define CLK_APBCLK_RTCCKEN_Msk (0x1ul << CLK_APBCLK_RTCCKEN_Pos) |
CLK_T::APBCLK: RTCCKEN Mask
#define CLK_APBCLK_RTCCKEN_Pos (1) |
CLK_T::APBCLK: RTCCKEN Position
#define CLK_APBCLK_SC0CKEN_Msk (0x1ul << CLK_APBCLK_SC0CKEN_Pos) |
CLK_T::APBCLK: SC0CKEN Mask
#define CLK_APBCLK_SC0CKEN_Pos (30) |
CLK_T::APBCLK: SC0CKEN Position
#define CLK_APBCLK_SC1CKEN_Msk (0x1ul << CLK_APBCLK_SC1CKEN_Pos) |
CLK_T::APBCLK: SC1CKEN Mask
#define CLK_APBCLK_SC1CKEN_Pos (31) |
CLK_T::APBCLK: SC1CKEN Position
#define CLK_APBCLK_SPI0CKEN_Msk (0x1ul << CLK_APBCLK_SPI0CKEN_Pos) |
CLK_T::APBCLK: SPI0CKEN Mask
#define CLK_APBCLK_SPI0CKEN_Pos (12) |
CLK_T::APBCLK: SPI0CKEN Position
#define CLK_APBCLK_SPI1CKEN_Msk (0x1ul << CLK_APBCLK_SPI1CKEN_Pos) |
CLK_T::APBCLK: SPI1CKEN Mask
#define CLK_APBCLK_SPI1CKEN_Pos (13) |
CLK_T::APBCLK: SPI1CKEN Position
#define CLK_APBCLK_SPI2CKEN_Msk (0x1ul << CLK_APBCLK_SPI2CKEN_Pos) |
CLK_T::APBCLK: SPI2CKEN Mask
#define CLK_APBCLK_SPI2CKEN_Pos (14) |
CLK_T::APBCLK: SPI2CKEN Position
#define CLK_APBCLK_SPI3CKEN_Msk (0x1ul << CLK_APBCLK_SPI3CKEN_Pos) |
CLK_T::APBCLK: SPI3CKEN Mask
#define CLK_APBCLK_SPI3CKEN_Pos (15) |
CLK_T::APBCLK: SPI3CKEN Position
#define CLK_APBCLK_TMR0CKEN_Msk (0x1ul << CLK_APBCLK_TMR0CKEN_Pos) |
CLK_T::APBCLK: TMR0CKEN Mask
#define CLK_APBCLK_TMR0CKEN_Pos (2) |
CLK_T::APBCLK: TMR0CKEN Position
#define CLK_APBCLK_TMR1CKEN_Msk (0x1ul << CLK_APBCLK_TMR1CKEN_Pos) |
CLK_T::APBCLK: TMR1CKEN Mask
#define CLK_APBCLK_TMR1CKEN_Pos (3) |
CLK_T::APBCLK: TMR1CKEN Position
#define CLK_APBCLK_TMR2CKEN_Msk (0x1ul << CLK_APBCLK_TMR2CKEN_Pos) |
CLK_T::APBCLK: TMR2CKEN Mask
#define CLK_APBCLK_TMR2CKEN_Pos (4) |
CLK_T::APBCLK: TMR2CKEN Position
#define CLK_APBCLK_TMR3CKEN_Msk (0x1ul << CLK_APBCLK_TMR3CKEN_Pos) |
CLK_T::APBCLK: TMR3CKEN Mask
#define CLK_APBCLK_TMR3CKEN_Pos (5) |
CLK_T::APBCLK: TMR3CKEN Position
#define CLK_APBCLK_UART0CKEN_Msk (0x1ul << CLK_APBCLK_UART0CKEN_Pos) |
CLK_T::APBCLK: UART0CKEN Mask
#define CLK_APBCLK_UART0CKEN_Pos (16) |
CLK_T::APBCLK: UART0CKEN Position
#define CLK_APBCLK_UART1CKEN_Msk (0x1ul << CLK_APBCLK_UART1CKEN_Pos) |
CLK_T::APBCLK: UART1CKEN Mask
#define CLK_APBCLK_UART1CKEN_Pos (17) |
CLK_T::APBCLK: UART1CKEN Position
#define CLK_APBCLK_WDTCKEN_Msk (0x1ul << CLK_APBCLK_WDTCKEN_Pos) |
CLK_T::APBCLK: WDTCKEN Mask
#define CLK_APBCLK_WDTCKEN_Pos (0) |
CLK_T::APBCLK: WDTCKEN Position
#define CLK_APBDIV_APB0DIV_Msk (0x7ul << CLK_APBDIV_APB0DIV_Pos) |
CLK_T::APBDIV: APB0DIV Mask
#define CLK_APBDIV_APB0DIV_Pos (0) |
CLK_T::APBDIV: APB0DIV Position
#define CLK_APBDIV_APB1DIV_Msk (0x7ul << CLK_APBDIV_APB1DIV_Pos) |
CLK_T::APBDIV: APB1DIV Mask
#define CLK_APBDIV_APB1DIV_Pos (4) |
CLK_T::APBDIV: APB1DIV Position
#define CLK_CDLOWB_LOWERBD_Msk (0x7fful << CLK_CDLOWB_LOWERBD_Pos) |
CLK_T::CDLOWB: LOWERBD Mask
#define CLK_CDLOWB_LOWERBD_Pos (0) |
CLK_T::CDLOWB: LOWERBD Position
#define CLK_CDUPB_UPERBD_Msk (0x7fful << CLK_CDUPB_UPERBD_Pos) |
CLK_T::CDUPB: UPERBD Mask
#define CLK_CDUPB_UPERBD_Pos (0) |
CLK_T::CDUPB: UPERBD Position
#define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) |
CLK_T::CLKDCTL: HXTFDEN Mask
#define CLK_CLKDCTL_HXTFDEN_Pos (0) |
CLK_T::CLKDCTL: HXTFDEN Position
#define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) |
CLK_T::CLKDCTL: HXTFQDEN Mask
#define CLK_CLKDCTL_HXTFQDEN_Pos (2) |
CLK_T::CLKDCTL: HXTFQDEN Position
#define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) |
CLK_T::CLKDCTL: LXTFDEN Mask
#define CLK_CLKDCTL_LXTFDEN_Pos (1) |
CLK_T::CLKDCTL: LXTFDEN Position
#define CLK_CLKDIE_HXTFIEN_Msk (0x1ul << CLK_CLKDIE_HXTFIEN_Pos) |
CLK_T::CLKDIE: HXTFIEN Mask
#define CLK_CLKDIE_HXTFIEN_Pos (0) |
CLK_T::CLKDIE: HXTFIEN Position
#define CLK_CLKDIE_HXTFQIEN_Msk (0x1ul << CLK_CLKDIE_HXTFQIEN_Pos) |
CLK_T::CLKDIE: HXTFQIEN Mask
#define CLK_CLKDIE_HXTFQIEN_Pos (2) |
CLK_T::CLKDIE: HXTFQIEN Position
#define CLK_CLKDIE_LXTFIEN_Msk (0x1ul << CLK_CLKDIE_LXTFIEN_Pos) |
CLK_T::CLKDIE: LXTFIEN Mask
#define CLK_CLKDIE_LXTFIEN_Pos (1) |
CLK_T::CLKDIE: LXTFIEN Position
#define CLK_CLKDIV0_ADCDIV_Msk (0xfful << CLK_CLKDIV0_ADCDIV_Pos) |
CLK_T::CLKDIV0: ADCDIV Mask
#define CLK_CLKDIV0_ADCDIV_Pos (16) |
CLK_T::CLKDIV0: ADCDIV Position
#define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) |
CLK_T::CLKDIV0: HCLKDIV Mask
#define CLK_CLKDIV0_HCLKDIV_Pos (0) |
CLK_T::CLKDIV0: HCLKDIV Position
#define CLK_CLKDIV0_SC0DIV_Msk (0xful << CLK_CLKDIV0_SC0DIV_Pos) |
CLK_T::CLKDIV0: SC0DIV Mask
#define CLK_CLKDIV0_SC0DIV_Pos (28) |
CLK_T::CLKDIV0: SC0DIV Position
#define CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos) |
CLK_T::CLKDIV0: UART0DIV Mask
#define CLK_CLKDIV0_UART0DIV_Pos (8) |
CLK_T::CLKDIV0: UART0DIV Position
#define CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos) |
CLK_T::CLKDIV0: UART1DIV Mask
#define CLK_CLKDIV0_UART1DIV_Pos (12) |
CLK_T::CLKDIV0: UART1DIV Position
#define CLK_CLKDIV1_SC1DIV_Msk (0xful << CLK_CLKDIV1_SC1DIV_Pos) |
CLK_T::CLKDIV1: SC1DIV Mask
#define CLK_CLKDIV1_SC1DIV_Pos (0) |
CLK_T::CLKDIV1: SC1DIV Position
#define CLK_CLKDIV1_TMR0DIV_Msk (0xful << CLK_CLKDIV1_TMR0DIV_Pos) |
CLK_T::CLKDIV1: TMR0DIV Mask
#define CLK_CLKDIV1_TMR0DIV_Pos (8) |
CLK_T::CLKDIV1: TMR0DIV Position
#define CLK_CLKDIV1_TMR1DIV_Msk (0xful << CLK_CLKDIV1_TMR1DIV_Pos) |
CLK_T::CLKDIV1: TMR1DIV Mask
#define CLK_CLKDIV1_TMR1DIV_Pos (12) |
CLK_T::CLKDIV1: TMR1DIV Position
#define CLK_CLKDIV1_TMR2DIV_Msk (0xful << CLK_CLKDIV1_TMR2DIV_Pos) |
CLK_T::CLKDIV1: TMR2DIV Mask
#define CLK_CLKDIV1_TMR2DIV_Pos (16) |
CLK_T::CLKDIV1: TMR2DIV Position
#define CLK_CLKDIV1_TMR3DIV_Msk (0xful << CLK_CLKDIV1_TMR3DIV_Pos) |
CLK_T::CLKDIV1: TMR3DIV Mask
#define CLK_CLKDIV1_TMR3DIV_Pos (20) |
CLK_T::CLKDIV1: TMR3DIV Position
#define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) |
CLK_T::CLKDSTS: HXTFIF Mask
#define CLK_CLKDSTS_HXTFIF_Pos (0) |
CLK_T::CLKDSTS: HXTFIF Position
#define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) |
CLK_T::CLKDSTS: HXTFQIF Mask
#define CLK_CLKDSTS_HXTFQIF_Pos (2) |
CLK_T::CLKDSTS: HXTFQIF Position
#define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) |
CLK_T::CLKDSTS: LXTFIF Mask
#define CLK_CLKDSTS_LXTFIF_Pos (1) |
CLK_T::CLKDSTS: LXTFIF Position
#define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) |
CLK_T::CLKOCTL: CLKOEN Mask
#define CLK_CLKOCTL_CLKOEN_Pos (4) |
CLK_T::CLKOCTL: CLKOEN Position
#define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) |
CLK_T::CLKOCTL: DIV1EN Mask
#define CLK_CLKOCTL_DIV1EN_Pos (5) |
CLK_T::CLKOCTL: DIV1EN Position
#define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) |
CLK_T::CLKOCTL: FREQSEL Mask
#define CLK_CLKOCTL_FREQSEL_Pos (0) |
CLK_T::CLKOCTL: FREQSEL Position
#define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) |
CLK_T::CLKSEL0: HCLKSEL Mask
#define CLK_CLKSEL0_HCLKSEL_Pos (0) |
CLK_T::CLKSEL0: HCLKSEL Position
#define CLK_CLKSEL0_HIRCSEL_Msk (0x1ul << CLK_CLKSEL0_HIRCSEL_Pos) |
CLK_T::CLKSEL0: HIRCSEL Mask
#define CLK_CLKSEL0_HIRCSEL_Pos (3) |
CLK_T::CLKSEL0: HIRCSEL Position
#define CLK_CLKSEL0_ISPSEL_Msk (0x1ul << CLK_CLKSEL0_ISPSEL_Pos) |
CLK_T::CLKSEL0: ISPSEL Mask
#define CLK_CLKSEL0_ISPSEL_Pos (4) |
CLK_T::CLKSEL0: ISPSEL Position
#define CLK_CLKSEL1_ADCSEL_Msk (0x7ul << CLK_CLKSEL1_ADCSEL_Pos) |
CLK_T::CLKSEL1: ADCSEL Mask
#define CLK_CLKSEL1_ADCSEL_Pos (19) |
CLK_T::CLKSEL1: ADCSEL Position
#define CLK_CLKSEL1_PWM0SEL_Msk (0x1ul << CLK_CLKSEL1_PWM0SEL_Pos) |
CLK_T::CLKSEL1: PWM0SEL Mask
#define CLK_CLKSEL1_PWM0SEL_Pos (4) |
CLK_T::CLKSEL1: PWM0SEL Position
#define CLK_CLKSEL1_SPI0SEL_Msk (0x3ul << CLK_CLKSEL1_SPI0SEL_Pos) |
CLK_T::CLKSEL1: SPI0SEL Mask
#define CLK_CLKSEL1_SPI0SEL_Pos (24) |
CLK_T::CLKSEL1: SPI0SEL Position
#define CLK_CLKSEL1_SPI2SEL_Msk (0x3ul << CLK_CLKSEL1_SPI2SEL_Pos) |
CLK_T::CLKSEL1: SPI2SEL Mask
#define CLK_CLKSEL1_SPI2SEL_Pos (26) |
CLK_T::CLKSEL1: SPI2SEL Position
#define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) |
CLK_T::CLKSEL1: TMR0SEL Mask
#define CLK_CLKSEL1_TMR0SEL_Pos (8) |
CLK_T::CLKSEL1: TMR0SEL Position
#define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) |
CLK_T::CLKSEL1: TMR1SEL Mask
#define CLK_CLKSEL1_TMR1SEL_Pos (12) |
CLK_T::CLKSEL1: TMR1SEL Position
#define CLK_CLKSEL1_UART0SEL_Msk (0x7ul << CLK_CLKSEL1_UART0SEL_Pos) |
CLK_T::CLKSEL1: UART0SEL Mask
#define CLK_CLKSEL1_UART0SEL_Pos (0) |
CLK_T::CLKSEL1: UART0SEL Position
#define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) |
CLK_T::CLKSEL1: WDTSEL Mask
#define CLK_CLKSEL1_WDTSEL_Pos (28) |
CLK_T::CLKSEL1: WDTSEL Position
#define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) |
CLK_T::CLKSEL1: WWDTSEL Mask
#define CLK_CLKSEL1_WWDTSEL_Pos (30) |
CLK_T::CLKSEL1: WWDTSEL Position
#define CLK_CLKSEL2_CLKOSEL_Msk (0x7ul << CLK_CLKSEL2_CLKOSEL_Pos) |
CLK_T::CLKSEL2: CLKOSEL Mask
#define CLK_CLKSEL2_CLKOSEL_Pos (4) |
CLK_T::CLKSEL2: CLKOSEL Position
#define CLK_CLKSEL2_SC0SEL_Msk (0x7ul << CLK_CLKSEL2_SC0SEL_Pos) |
CLK_T::CLKSEL2: SC0SEL Mask
#define CLK_CLKSEL2_SC0SEL_Pos (16) |
CLK_T::CLKSEL2: SC0SEL Position
#define CLK_CLKSEL2_SC1SEL_Msk (0x7ul << CLK_CLKSEL2_SC1SEL_Pos) |
CLK_T::CLKSEL2: SC1SEL Mask
#define CLK_CLKSEL2_SC1SEL_Pos (20) |
CLK_T::CLKSEL2: SC1SEL Position
#define CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos) |
CLK_T::CLKSEL2: SPI1SEL Mask
#define CLK_CLKSEL2_SPI1SEL_Pos (24) |
CLK_T::CLKSEL2: SPI1SEL Position
#define CLK_CLKSEL2_SPI3SEL_Msk (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos) |
CLK_T::CLKSEL2: SPI3SEL Mask
#define CLK_CLKSEL2_SPI3SEL_Pos (26) |
CLK_T::CLKSEL2: SPI3SEL Position
#define CLK_CLKSEL2_TMR2SEL_Msk (0x7ul << CLK_CLKSEL2_TMR2SEL_Pos) |
CLK_T::CLKSEL2: TMR2SEL Mask
#define CLK_CLKSEL2_TMR2SEL_Pos (8) |
CLK_T::CLKSEL2: TMR2SEL Position
#define CLK_CLKSEL2_TMR3SEL_Msk (0x7ul << CLK_CLKSEL2_TMR3SEL_Pos) |
CLK_T::CLKSEL2: TMR3SEL Mask
#define CLK_CLKSEL2_TMR3SEL_Pos (12) |
CLK_T::CLKSEL2: TMR3SEL Position
#define CLK_CLKSEL2_UART1SEL_Msk (0x7ul << CLK_CLKSEL2_UART1SEL_Pos) |
CLK_T::CLKSEL2: UART1SEL Mask
#define CLK_CLKSEL2_UART1SEL_Pos (0) |
CLK_T::CLKSEL2: UART1SEL Position
#define CLK_PLLCTL_INDIV_Msk (0x3ful << CLK_PLLCTL_INDIV_Pos) |
CLK_T::PLLCTL: INDIV Mask
#define CLK_PLLCTL_INDIV_Pos (8) |
CLK_T::PLLCTL: INDIV Position
#define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) |
CLK_T::PLLCTL: PD Mask
#define CLK_PLLCTL_PD_Pos (16) |
CLK_T::PLLCTL: PD Position
#define CLK_PLLCTL_PLLMLP_Msk (0x3ful << CLK_PLLCTL_PLLMLP_Pos) |
CLK_T::PLLCTL: PLLMLP Mask
#define CLK_PLLCTL_PLLMLP_Pos (0) |
CLK_T::PLLCTL: PLLMLP Position
#define CLK_PLLCTL_PLLSRC_Msk (0x3ul << CLK_PLLCTL_PLLSRC_Pos) |
CLK_T::PLLCTL: PLLSRC Mask
#define CLK_PLLCTL_PLLSRC_Pos (17) |
CLK_T::PLLCTL: PLLSRC Position
#define CLK_PLLCTL_STBTSEL_Msk (0x3ul << CLK_PLLCTL_STBTSEL_Pos) |
CLK_T::PLLCTL: STBTSEL Mask
#define CLK_PLLCTL_STBTSEL_Pos (14) |
CLK_T::PLLCTL: STBTSEL Position
#define CLK_PWRCTL_HIRC0EN_Msk (0x1ul << CLK_PWRCTL_HIRC0EN_Pos) |
CLK_T::PWRCTL: HIRC0EN Mask
#define CLK_PWRCTL_HIRC0EN_Pos (2) |
CLK_T::PWRCTL: HIRC0EN Position
#define CLK_PWRCTL_HIRC0FSEL_Msk (0x1ul << CLK_PWRCTL_HIRC0FSEL_Pos) |
CLK_T::PWRCTL: HIRC0FSEL Mask
#define CLK_PWRCTL_HIRC0FSEL_Pos (13) |
CLK_T::PWRCTL: HIRC0FSEL Position
#define CLK_PWRCTL_HIRC0FSTOP_Msk (0x1ul << CLK_PWRCTL_HIRC0FSTOP_Pos) |
CLK_T::PWRCTL: HIRC0FSTOP Mask
#define CLK_PWRCTL_HIRC0FSTOP_Pos (14) |
CLK_T::PWRCTL: HIRC0FSTOP Position
#define CLK_PWRCTL_HIRC1EN_Msk (0x1ul << CLK_PWRCTL_HIRC1EN_Pos) |
CLK_T::PWRCTL: HIRC1EN Mask
#define CLK_PWRCTL_HIRC1EN_Pos (24) |
CLK_T::PWRCTL: HIRC1EN Position
#define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) |
CLK_T::PWRCTL: HXTEN Mask
#define CLK_PWRCTL_HXTEN_Pos (0) |
@addtogroup CLK_CONST CLK Bit Field Definition Constant Definitions for CLK Controller
CLK_T::PWRCTL: HXTEN Position
#define CLK_PWRCTL_HXTGAIN_Msk (0x7ul << CLK_PWRCTL_HXTGAIN_Pos) |
CLK_T::PWRCTL: HXTGAIN Mask
#define CLK_PWRCTL_HXTGAIN_Pos (10) |
CLK_T::PWRCTL: HXTGAIN Position
#define CLK_PWRCTL_HXTSLTYP_Msk (0x1ul << CLK_PWRCTL_HXTSLTYP_Pos) |
CLK_T::PWRCTL: HXTSLTYP Mask
#define CLK_PWRCTL_HXTSLTYP_Pos (8) |
CLK_T::PWRCTL: HXTSLTYP Position
#define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) |
CLK_T::PWRCTL: LIRCEN Mask
#define CLK_PWRCTL_LIRCEN_Pos (3) |
CLK_T::PWRCTL: LIRCEN Position
#define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) |
CLK_T::PWRCTL: LXTEN Mask
#define CLK_PWRCTL_LXTEN_Pos (1) |
CLK_T::PWRCTL: LXTEN Position
#define CLK_PWRCTL_MIRCEN_Msk (0x1ul << CLK_PWRCTL_MIRCEN_Pos) |
CLK_T::PWRCTL: MIRCEN Mask
#define CLK_PWRCTL_MIRCEN_Pos (25) |
CLK_T::PWRCTL: MIRCEN Position
#define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) |
CLK_T::PWRCTL: PDEN Mask
#define CLK_PWRCTL_PDEN_Pos (6) |
CLK_T::PWRCTL: PDEN Position
#define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) |
CLK_T::PWRCTL: PDWKDLY Mask
#define CLK_PWRCTL_PDWKDLY_Pos (4) |
CLK_T::PWRCTL: PDWKDLY Position
#define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) |
CLK_T::PWRCTL: PDWKIEN Mask
#define CLK_PWRCTL_PDWKIEN_Pos (5) |
CLK_T::PWRCTL: PDWKIEN Position
#define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) |
CLK_T::STATUS: CLKSFAIL Mask
#define CLK_STATUS_CLKSFAIL_Pos (7) |
CLK_T::STATUS: CLKSFAIL Position
#define CLK_STATUS_HIRC0STB_Msk (0x1ul << CLK_STATUS_HIRC0STB_Pos) |
CLK_T::STATUS: HIRC0STB Mask
#define CLK_STATUS_HIRC0STB_Pos (4) |
CLK_T::STATUS: HIRC0STB Position
#define CLK_STATUS_HIRC1STB_Msk (0x1ul << CLK_STATUS_HIRC1STB_Pos) |
CLK_T::STATUS: HIRC1STB Mask
#define CLK_STATUS_HIRC1STB_Pos (5) |
CLK_T::STATUS: HIRC1STB Position
#define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) |
CLK_T::STATUS: HXTSTB Mask
#define CLK_STATUS_HXTSTB_Pos (0) |
CLK_T::STATUS: HXTSTB Position
#define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) |
CLK_T::STATUS: LIRCSTB Mask
#define CLK_STATUS_LIRCSTB_Pos (3) |
CLK_T::STATUS: LIRCSTB Position
#define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) |
CLK_T::STATUS: LXTSTB Mask
#define CLK_STATUS_LXTSTB_Pos (1) |
CLK_T::STATUS: LXTSTB Position
#define CLK_STATUS_MIRCSTB_Msk (0x1ul << CLK_STATUS_MIRCSTB_Pos) |
CLK_T::STATUS: MIRCSTB Mask
#define CLK_STATUS_MIRCSTB_Pos (6) |
CLK_T::STATUS: MIRCSTB Position
#define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) |
CLK_T::STATUS: PLLSTB Mask
#define CLK_STATUS_PLLSTB_Pos (2) |
CLK_T::STATUS: PLLSTB Position
#define CLK_WKINTSTS_PDWKIF_Msk (0x1ul << CLK_WKINTSTS_PDWKIF_Pos) |
CLK_T::WKINTSTS: PDWKIF Mask
#define CLK_WKINTSTS_PDWKIF_Pos (0) |
CLK_T::WKINTSTS: PDWKIF Position