40 PDMAGCR->GCTL |= (u32Mask << 8);
72 pdma->
CTLn = (pdma->
CTLn & ~PDMA_CH_CTLn_TXWIDTH_Msk) | u32Width;
73 pdma->
CNTn = (u32TransCount & 0xffff);
89void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
94 pdma->
SAn = u32SrcAddr;
95 pdma->
DAn = u32DstAddr;
130 PDMAGCR->REQSEL1 = (
PDMAGCR->REQSEL1 & ~DMA_GCR_REQSEL1_REQSRC4_Msk) | u32Peripheral;
153 pdma->
TOCn &= ~PDMA_CH_TOCn_TOC_Msk;
154 pdma->
TOCn |= u32TimeOutCnt;
NANO103 peripheral access layer header file. This file contains all the peripheral register's definit...
#define DMA_GCR_REQSEL0_REQSRC2_Pos
#define DMA_GCR_REQSEL0_REQSRC1_Pos
#define PDMA_CH_CTLn_SASEL_Msk
#define DMA_GCR_REQSEL0_REQSRC3_Pos
#define PDMA_CH_CTLn_DASEL_Msk
#define PDMA_CH_CTLn_TRIGEN_Msk
#define PDMA_CH_CTLn_TOUTEN_Pos
#define PDMA_CH_CTLn_CHEN_Msk
void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
Set PDMA Transfer Address.
void PDMA_Trigger(uint32_t u32Ch)
Trigger PDMA.
void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
Set PDMA Timeout.
void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask)
Enable Interrupt.
void PDMA_Open(uint32_t u32Mask)
PDMA Open.
void PDMA_Close(void)
PDMA Close.
void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask)
Disable Interrupt.
void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Periphral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
Set PDMA Transfer Mode.
void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
Set PDMA Transfer Count.
#define PDMAGCR
Pointer to PDMA global control register structure.
#define PDMA0_BASE
PDMA0 register base address.