35#if defined ( __ICCARM__ )
36 #pragma system_include
37#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
38 #pragma clang system_header
41#ifndef __CORE_CM0_H_GENERIC
42#define __CORE_CM0_H_GENERIC
74#define __CM0_CMSIS_VERSION_MAIN (0x04U)
75#define __CM0_CMSIS_VERSION_SUB (0x1EU)
76#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
77 __CM0_CMSIS_VERSION_SUB )
79#define __CORTEX_M (0x00U)
82#if defined ( __CC_ARM )
84 #define __INLINE __inline
85 #define __STATIC_INLINE static __inline
87#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
89 #define __INLINE __inline
90 #define __STATIC_INLINE static __inline
92#elif defined ( __GNUC__ )
94 #define __INLINE inline
95 #define __STATIC_INLINE static inline
97#elif defined ( __ICCARM__ )
99 #define __INLINE inline
100 #define __STATIC_INLINE static inline
102#elif defined ( __TMS470__ )
104 #define __STATIC_INLINE static inline
106#elif defined ( __TASKING__ )
108 #define __INLINE inline
109 #define __STATIC_INLINE static inline
111#elif defined ( __CSMC__ )
114 #define __INLINE inline
115 #define __STATIC_INLINE static inline
118 #error Unknown compiler
126#if defined ( __CC_ARM )
127 #if defined __TARGET_FPU_VFP
128 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
131#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
132 #if defined __ARM_PCS_VFP
133 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
136#elif defined ( __GNUC__ )
137 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
141#elif defined ( __ICCARM__ )
142 #if defined __ARMVFP__
143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
146#elif defined ( __TMS470__ )
147 #if defined __TI_VFP_SUPPORT__
148 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
151#elif defined ( __TASKING__ )
152 #if defined __FPU_VFP__
153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
156#elif defined ( __CSMC__ )
157 #if ( __CSMC__ & 0x400U)
158 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
172#ifndef __CMSIS_GENERIC
174#ifndef __CORE_CM0_H_DEPENDANT
175#define __CORE_CM0_H_DEPENDANT
182#if defined __CHECK_DEVICE_DEFINES
184 #define __CM0_REV 0x0000U
185 #warning "__CM0_REV not defined in device header file; using default!"
188 #ifndef __NVIC_PRIO_BITS
189 #define __NVIC_PRIO_BITS 2U
190 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
193 #ifndef __Vendor_SysTickConfig
194 #define __Vendor_SysTickConfig 0U
195 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
210 #define __I volatile const
216#define __IM volatile const
218#define __IOM volatile
261#define APSR_N_Pos 31U
262#define APSR_N_Msk (1UL << APSR_N_Pos)
264#define APSR_Z_Pos 30U
265#define APSR_Z_Msk (1UL << APSR_Z_Pos)
267#define APSR_C_Pos 29U
268#define APSR_C_Msk (1UL << APSR_C_Pos)
270#define APSR_V_Pos 28U
271#define APSR_V_Msk (1UL << APSR_V_Pos)
288#define IPSR_ISR_Pos 0U
289#define IPSR_ISR_Msk (0x1FFUL )
312#define xPSR_N_Pos 31U
313#define xPSR_N_Msk (1UL << xPSR_N_Pos)
315#define xPSR_Z_Pos 30U
316#define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
318#define xPSR_C_Pos 29U
319#define xPSR_C_Msk (1UL << xPSR_C_Pos)
321#define xPSR_V_Pos 28U
322#define xPSR_V_Msk (1UL << xPSR_V_Pos)
324#define xPSR_T_Pos 24U
325#define xPSR_T_Msk (1UL << xPSR_T_Pos)
327#define xPSR_ISR_Pos 0U
328#define xPSR_ISR_Msk (0x1FFUL )
346#define CONTROL_SPSEL_Pos 1U
347#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
365 uint32_t RESERVED0[31U];
367 uint32_t RSERVED1[31U];
369 uint32_t RESERVED2[31U];
371 uint32_t RESERVED3[31U];
372 uint32_t RESERVED4[64U];
403#define SCB_CPUID_IMPLEMENTER_Pos 24U
404#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
406#define SCB_CPUID_VARIANT_Pos 20U
407#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
409#define SCB_CPUID_ARCHITECTURE_Pos 16U
410#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
412#define SCB_CPUID_PARTNO_Pos 4U
413#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
415#define SCB_CPUID_REVISION_Pos 0U
416#define SCB_CPUID_REVISION_Msk (0xFUL )
419#define SCB_ICSR_NMIPENDSET_Pos 31U
420#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
422#define SCB_ICSR_PENDSVSET_Pos 28U
423#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
425#define SCB_ICSR_PENDSVCLR_Pos 27U
426#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
428#define SCB_ICSR_PENDSTSET_Pos 26U
429#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
431#define SCB_ICSR_PENDSTCLR_Pos 25U
432#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
434#define SCB_ICSR_ISRPREEMPT_Pos 23U
435#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
437#define SCB_ICSR_ISRPENDING_Pos 22U
438#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
440#define SCB_ICSR_VECTPENDING_Pos 12U
441#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
443#define SCB_ICSR_VECTACTIVE_Pos 0U
444#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL )
447#define SCB_AIRCR_VECTKEY_Pos 16U
448#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
450#define SCB_AIRCR_VECTKEYSTAT_Pos 16U
451#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
453#define SCB_AIRCR_ENDIANESS_Pos 15U
454#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
456#define SCB_AIRCR_SYSRESETREQ_Pos 2U
457#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
459#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
460#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
463#define SCB_SCR_SEVONPEND_Pos 4U
464#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
466#define SCB_SCR_SLEEPDEEP_Pos 2U
467#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
469#define SCB_SCR_SLEEPONEXIT_Pos 1U
470#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
473#define SCB_CCR_STKALIGN_Pos 9U
474#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
476#define SCB_CCR_UNALIGN_TRP_Pos 3U
477#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
480#define SCB_SHCSR_SVCALLPENDED_Pos 15U
481#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
505#define SysTick_CTRL_COUNTFLAG_Pos 16U
506#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
508#define SysTick_CTRL_CLKSOURCE_Pos 2U
509#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
511#define SysTick_CTRL_TICKINT_Pos 1U
512#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
514#define SysTick_CTRL_ENABLE_Pos 0U
515#define SysTick_CTRL_ENABLE_Msk (1UL )
518#define SysTick_LOAD_RELOAD_Pos 0U
519#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL )
522#define SysTick_VAL_CURRENT_Pos 0U
523#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL )
526#define SysTick_CALIB_NOREF_Pos 31U
527#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
529#define SysTick_CALIB_SKEW_Pos 30U
530#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
532#define SysTick_CALIB_TENMS_Pos 0U
533#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL )
561#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
569#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
582#define SCS_BASE (0xE000E000UL)
583#define SysTick_BASE (SCS_BASE + 0x0010UL)
584#define NVIC_BASE (SCS_BASE + 0x0100UL)
585#define SCB_BASE (SCS_BASE + 0x0D00UL)
587#define SCB ((SCB_Type *) SCB_BASE )
588#define SysTick ((SysTick_Type *) SysTick_BASE )
589#define NVIC ((NVIC_Type *) NVIC_BASE )
619#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
620#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
621#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
631 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)
IRQn) & 0x1FUL));
642 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)
IRQn) & 0x1FUL));
655 return((uint32_t)(((
NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)
IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
666 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)
IRQn) & 0x1FUL));
677 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)
IRQn) & 0x1FUL));
690 if ((int32_t)(
IRQn) < 0)
715 if ((int32_t)(
IRQn) < 0)
756#if (__Vendor_SysTickConfig == 0U)
776 SysTick->LOAD = (uint32_t)(ticks - 1UL);
CMSIS Cortex-M Core Function Access Header File.
CMSIS Cortex-M Core Instruction Access Header File.
__STATIC_INLINE void NVIC_SystemReset(void)
System Reset.
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Disable External Interrupt.
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Enable External Interrupt.
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
System Tick Configuration.
#define SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_SYSRESETREQ_Msk
#define SysTick_CTRL_ENABLE_Msk
#define SysTick_LOAD_RELOAD_Msk
#define SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Structure type to access the System Control Block (SCB).
Structure type to access the System Timer (SysTick).
Union type to access the Application Program Status Register (APSR).
Union type to access the Control Registers (CONTROL).
Union type to access the Interrupt Program Status Register (IPSR).
Union type to access the Special-Purpose Program Status Registers (xPSR).