33#define ADC_CH7_EXT (0UL)
34#define ADC_CH7_BGP (ADC_ADCHER_PRESEL_Msk)
35#define ADC_CMP_LESS_THAN (0UL)
36#define ADC_CMP_GREATER_OR_EQUAL_TO (ADC_ADCMPR_CMPCOND_Msk)
37#define ADC_TRIGGER_BY_EXT_PIN (0UL)
38#define ADC_TRIGGER_BY_PWM (ADC_ADCR_TRGS_Msk)
39#define ADC_FALLING_EDGE_TRIGGER (0UL)
40#define ADC_RISING_EDGE_TRIGGER (ADC_ADCR_TRGCOND_Msk)
41#define ADC_ADF_INT (ADC_ADSR_ADF_Msk)
42#define ADC_CMP0_INT (ADC_ADSR_CMPF0_Msk)
43#define ADC_CMP1_INT (ADC_ADSR_CMPF1_Msk)
44#define ADC_SAMPLE_CLOCK_0 (0UL)
45#define ADC_SAMPLE_CLOCK_1 (1UL)
46#define ADC_SAMPLE_CLOCK_2 (2UL)
47#define ADC_SAMPLE_CLOCK_4 (3UL)
48#define ADC_SAMPLE_CLOCK_8 (4UL)
49#define ADC_SAMPLE_CLOCK_16 (5UL)
50#define ADC_SAMPLE_CLOCK_32 (6UL)
51#define ADC_SAMPLE_CLOCK_64 (7UL)
52#define ADC_SAMPLE_CLOCK_128 (8UL)
53#define ADC_SAMPLE_CLOCK_256 (9UL)
54#define ADC_SAMPLE_CLOCK_512 (10UL)
55#define ADC_SAMPLE_CLOCK_1024 (11UL)
75#define ADC_CONFIG_CH7(adc, u32Source) (ADC->ADCHER = (ADC->ADCHER & ~ADC_ADCHER_PRESEL_Msk) | (u32Source))
84#define ADC_GET_CONVERSION_DATA(adc, u32ChNum) (ADC->ADDR & ADC_ADDR_RSLT_Msk)
96#define ADC_GET_INT_FLAG(adc, u32Mask) (ADC->ADSR & (u32Mask))
108#define ADC_CLR_INT_FLAG(adc, u32Mask) (ADC->ADSR = (ADC->ADSR & ~(ADC_ADSR_ADF_Msk | \
109 ADC_ADSR_CMPF0_Msk | \
110 ADC_ADSR_CMPF1_Msk)) | (u32Mask))
120#define ADC_IS_BUSY(adc) (ADC->ADSR & ADC_ADSR_BUSY_Msk ? 1 : 0)
131#define ADC_IS_DATA_OVERRUN(adc, u32ChNum) (ADC->ADSR & ADC_ADSR_OVERRUN_Msk ? 1 : 0)
142#define ADC_IS_DATA_VALID(adc, u32ChNum) (ADC->ADSR & ADC_ADSR_VALID_Msk ? 1 : 0)
150#define ADC_POWER_DOWN(adc) (ADC->ADCR &= ~ADC_ADCR_ADEN_Msk)
158#define ADC_POWER_ON(adc) (ADC->ADCR |= ADC_ADCR_ADEN_Msk)
175#define ADC_ENABLE_CMP0(adc, \
179 u32MatchCount) (ADC->ADCMPR[0] = ((u32ChNum) << ADC_ADCMPR_CMPCH_Pos) | \
181 ((u32Data) << ADC_ADCMPR_CMPD_Pos) | \
182 (((u32MatchCount) - 1) << ADC_ADCMPR_CMPMATCNT_Pos) |\
183 ADC_ADCMPR_CMPEN_Msk)
190#define ADC_DISABLE_CMP0(adc) (ADC->ADCMPR[0] = 0)
207#define ADC_ENABLE_CMP1(adc, \
211 u32MatchCount) (ADC->ADCMPR[1] = ((u32ChNum) << ADC_ADCMPR_CMPCH_Pos) | \
213 ((u32Data) << ADC_ADCMPR_CMPD_Pos) | \
214 ((u32MatchCount - 1) << ADC_ADCMPR_CMPMATCNT_Pos) |\
215 ADC_ADCMPR_CMPEN_Msk)
222#define ADC_DISABLE_CMP1(adc) (ADC->ADCMPR[1] = 0)
233#define ADC_SET_INPUT_CHANNEL(adc, u32Mask) (ADC->ADCHER = (ADC->ADCHER & ~ADC_ADCHER_CHEN_Msk) | (u32Mask))
241#define ADC_START_CONV(adc) (ADC->ADCR |= ADC_ADCR_ADST_Msk)
249#define ADC_STOP_CONV(adc) (ADC->ADCR &= ~ADC_ADCR_ADST_Msk)
252 uint32_t u32InputMode,
262 uint32_t u32SampleTime);
void ADC_EnableHWTrigger(ADC_T *adc, uint32_t u32Source, uint32_t u32Param)
Configure the hardware trigger condition and enable hardware trigger.
void ADC_Close(ADC_T *adc)
Disable ADC module.
void ADC_SetExtraSampleTime(ADC_T *adc, uint32_t u32ChNum, uint32_t u32SampleTime)
Set ADC sample time for designated channel.
void ADC_Open(ADC_T *adc, uint32_t u32InputMode, uint32_t u32OpMode, uint32_t u32ChMask)
This API configures ADC module to be ready for convert the input from selected channel.
void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask)
Disable the interrupt(s) selected by u32Mask parameter.
void ADC_DisableHWTrigger(ADC_T *adc)
Disable hardware trigger ADC function.
void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask)
Enable the interrupt(s) selected by u32Mask parameter.