BLE_API  v2.1.3

Macros

#define SPI_MASTER_TX_DMA_CH   3
 
#define SPI_MASTER_RX_DMA_CH   4
 
#define SPI_OPENED_CH   ((1 << SPI_MASTER_TX_DMA_CH) | (1 << SPI_MASTER_RX_DMA_CH))
 
#define SPI_CLK_FREQ   16000000
 
#define SPI0_ClearRxFIFO()   (SPI0->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk)
 

Detailed Description

Macro Definition Documentation

◆ SPI0_ClearRxFIFO

#define SPI0_ClearRxFIFO ( )    (SPI0->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk)

SPI clear RX FIFO function definition.

◆ SPI_CLK_FREQ

#define SPI_CLK_FREQ   16000000

The expected frequency of SPI bus clock in Hz.

◆ SPI_MASTER_RX_DMA_CH

#define SPI_MASTER_RX_DMA_CH   4

The selected RX DMA channel.

◆ SPI_MASTER_TX_DMA_CH

#define SPI_MASTER_TX_DMA_CH   3

The selected TX DMA channel.

◆ SPI_OPENED_CH

#define SPI_OPENED_CH   ((1 << SPI_MASTER_TX_DMA_CH) | (1 << SPI_MASTER_RX_DMA_CH))

The SPI channel enable bits.