12#if defined ( __CC_ARM )
1206 __IO uint32_t HcRhPortStatus[2];
1208 __I uint32_t RESERVE0[105];
1220#define USBH_HcRevision_REV_Pos (0)
1221#define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos)
1223#define USBH_HcControl_CBSR_Pos (0)
1224#define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos)
1226#define USBH_HcControl_PLE_Pos (2)
1227#define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos)
1229#define USBH_HcControl_IE_Pos (3)
1230#define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos)
1232#define USBH_HcControl_CLE_Pos (4)
1233#define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos)
1235#define USBH_HcControl_BLE_Pos (5)
1236#define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos)
1238#define USBH_HcControl_HCFS_Pos (6)
1239#define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos)
1241#define USBH_HcCommandStatus_HCR_Pos (0)
1242#define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos)
1244#define USBH_HcCommandStatus_CLF_Pos (1)
1245#define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos)
1247#define USBH_HcCommandStatus_BLF_Pos (2)
1248#define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos)
1250#define USBH_HcCommandStatus_SOC_Pos (16)
1251#define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos)
1253#define USBH_HcInterruptStatus_SO_Pos (0)
1254#define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos)
1256#define USBH_HcInterruptStatus_WDH_Pos (1)
1257#define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos)
1259#define USBH_HcInterruptStatus_SF_Pos (2)
1260#define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos)
1262#define USBH_HcInterruptStatus_RD_Pos (3)
1263#define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos)
1265#define USBH_HcInterruptStatus_FNO_Pos (5)
1266#define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos)
1268#define USBH_HcInterruptStatus_RHSC_Pos (6)
1269#define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos)
1271#define USBH_HcInterruptEnable_SO_Pos (0)
1272#define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos)
1274#define USBH_HcInterruptEnable_WDH_Pos (1)
1275#define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos)
1277#define USBH_HcInterruptEnable_SF_Pos (2)
1278#define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos)
1280#define USBH_HcInterruptEnable_RD_Pos (3)
1281#define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos)
1283#define USBH_HcInterruptEnable_FNO_Pos (5)
1284#define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos)
1286#define USBH_HcInterruptEnable_RHSC_Pos (6)
1287#define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos)
1289#define USBH_HcInterruptEnable_MIE_Pos (31)
1290#define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos)
1292#define USBH_HcInterruptDisable_SO_Pos (0)
1293#define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos)
1295#define USBH_HcInterruptDisable_WDH_Pos (1)
1296#define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos)
1298#define USBH_HcInterruptDisable_SF_Pos (2)
1299#define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos)
1301#define USBH_HcInterruptDisable_RD_Pos (3)
1302#define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos)
1304#define USBH_HcInterruptDisable_FNO_Pos (5)
1305#define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos)
1307#define USBH_HcInterruptDisable_RHSC_Pos (6)
1308#define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos)
1310#define USBH_HcInterruptDisable_MIE_Pos (31)
1311#define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos)
1313#define USBH_HcHCCA_HCCA_Pos (8)
1314#define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos)
1316#define USBH_HcPeriodCurrentED_PCED_Pos (4)
1317#define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos)
1319#define USBH_HcControlHeadED_CHED_Pos (4)
1320#define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos)
1322#define USBH_HcControlCurrentED_CCED_Pos (4)
1323#define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos)
1325#define USBH_HcBulkHeadED_BHED_Pos (4)
1326#define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos)
1328#define USBH_HcBulkCurrentED_BCED_Pos (4)
1329#define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos)
1331#define USBH_HcDoneHead_DH_Pos (4)
1332#define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos)
1334#define USBH_HcFmInterval_FI_Pos (0)
1335#define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos)
1337#define USBH_HcFmInterval_FSMPS_Pos (16)
1338#define USBH_HcFmInterval_FSMPS_Msk (0x7ffful << USBH_HcFmInterval_FSMPS_Pos)
1340#define USBH_HcFmInterval_FIT_Pos (31)
1341#define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos)
1343#define USBH_HcFmRemaining_FR_Pos (0)
1344#define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos)
1346#define USBH_HcFmRemaining_FRT_Pos (31)
1347#define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos)
1349#define USBH_HcFmNumber_FN_Pos (0)
1350#define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos)
1352#define USBH_HcPeriodicStart_PS_Pos (0)
1353#define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos)
1355#define USBH_HcLSThreshold_LST_Pos (0)
1356#define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos)
1358#define USBH_HcRhDescriptorA_NDP_Pos (0)
1359#define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos)
1361#define USBH_HcRhDescriptorA_PSM_Pos (8)
1362#define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos)
1364#define USBH_HcRhDescriptorA_OCPM_Pos (11)
1365#define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos)
1367#define USBH_HcRhDescriptorA_NOCP_Pos (12)
1368#define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos)
1370#define USBH_HcRhDescriptorB_PPCM_Pos (16)
1371#define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos)
1373#define USBH_HcRhStatus_LPS_Pos (0)
1374#define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos)
1376#define USBH_HcRhStatus_OCI_Pos (1)
1377#define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos)
1379#define USBH_HcRhStatus_DRWE_Pos (15)
1380#define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos)
1382#define USBH_HcRhStatus_LPSC_Pos (16)
1383#define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos)
1385#define USBH_HcRhStatus_OCIC_Pos (17)
1386#define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos)
1388#define USBH_HcRhStatus_CRWE_Pos (31)
1389#define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos)
1391#define USBH_HcRhPortStatus_CCS_Pos (0)
1392#define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos)
1394#define USBH_HcRhPortStatus_PES_Pos (1)
1395#define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos)
1397#define USBH_HcRhPortStatus_PSS_Pos (2)
1398#define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos)
1400#define USBH_HcRhPortStatus_POCI_Pos (3)
1401#define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos)
1403#define USBH_HcRhPortStatus_PRS_Pos (4)
1404#define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos)
1406#define USBH_HcRhPortStatus_PPS_Pos (8)
1407#define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos)
1409#define USBH_HcRhPortStatus_LSDA_Pos (9)
1410#define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos)
1412#define USBH_HcRhPortStatus_CSC_Pos (16)
1413#define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos)
1415#define USBH_HcRhPortStatus_PESC_Pos (17)
1416#define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos)
1418#define USBH_HcRhPortStatus_PSSC_Pos (18)
1419#define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos)
1421#define USBH_HcRhPortStatus_OCIC_Pos (19)
1422#define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos)
1424#define USBH_HcRhPortStatus_PRSC_Pos (20)
1425#define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos)
1427#define USBH_HcPhyControl_STBYEN_Pos (27)
1428#define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos)
1430#define USBH_HcMiscControl_ABORT_Pos (1)
1431#define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos)
1433#define USBH_HcMiscControl_OCAL_Pos (3)
1434#define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos)
1436#define USBH_HcMiscControl_DPRT1_Pos (16)
1437#define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos)
1443#if defined ( __CC_ARM )
1444#pragma no_anon_unions
__IO uint32_t HcBulkCurrentED
__IO uint32_t HcRhDescriptorB
__IO uint32_t HcPhyControl
__IO uint32_t HcFmInterval
__IO uint32_t HcInterruptDisable
__IO uint32_t HcLSThreshold
__IO uint32_t HcPeriodCurrentED
__IO uint32_t HcBulkHeadED
__IO uint32_t HcControlCurrentED
__I uint32_t HcFmRemaining
__IO uint32_t HcMiscControl
__IO uint32_t HcInterruptStatus
__IO uint32_t HcPeriodicStart
__IO uint32_t HcInterruptEnable
__IO uint32_t HcRhDescriptorA
__IO uint32_t HcCommandStatus
__IO uint32_t HcControlHeadED