M480 BSP V3.05.006
The Board Support Package for M480 Series
usci_spi.c
Go to the documentation of this file.
1/****************************************************************************/
9#include "NuMicro.h"
10
43uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
44{
45 uint32_t u32ClkDiv = 0ul;
46 uint32_t u32Pclk;
47 uint32_t u32UspiClk = 0ul;
48
49 if(uspi == (USPI_T *)USPI0)
50 {
51 u32Pclk = CLK_GetPCLK0Freq();
52 }
53 else
54 {
55 u32Pclk = CLK_GetPCLK1Freq();
56 }
57
58 if(u32BusClock != 0ul)
59 {
60 u32ClkDiv = (uint32_t) ((((((u32Pclk/2ul)*10ul)/(u32BusClock))+5ul)/10ul)-1ul); /* Compute proper divider for USCI_SPI clock */
61 }
62
63 /* Enable USCI_SPI protocol */
64 uspi->CTL &= ~USPI_CTL_FUNMODE_Msk;
65 uspi->CTL = 1ul << USPI_CTL_FUNMODE_Pos;
66
67 /* Data format configuration */
68 if(u32DataWidth == 16ul)
69 {
70 u32DataWidth = 0ul;
71 }
72 uspi->LINECTL &= ~USPI_LINECTL_DWIDTH_Msk;
73 uspi->LINECTL |= (u32DataWidth << USPI_LINECTL_DWIDTH_Pos);
74
75 /* MSB data format */
76 uspi->LINECTL &= ~USPI_LINECTL_LSB_Msk;
77
78 /* Set slave selection signal active low */
79 if(u32MasterSlave == USPI_MASTER)
80 {
82 }
83 else
84 {
86 }
87
88 /* Set operating mode and transfer timing */
90 uspi->PROTCTL |= (u32MasterSlave | u32SPIMode);
91
92 /* Set USCI_SPI bus clock */
93 uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk;
94 uspi->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos);
96
97 if(u32BusClock != 0ul)
98 {
99 u32UspiClk = (uint32_t)( u32Pclk / ((u32ClkDiv+1ul)<<1) );
100 }
101
102 return u32UspiClk;
103}
104
111{
112 uspi->CTL &= ~USPI_CTL_FUNMODE_Msk;
113}
114
121{
123}
124
131{
133}
134
141{
143}
144
154void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
155{
156 uspi->LINECTL = (uspi->LINECTL & ~USPI_LINECTL_CTLOINV_Msk) | u32ActiveLevel;
158}
159
166uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock)
167{
168 uint32_t u32ClkDiv;
169 uint32_t u32Pclk;
170
171 if(uspi == USPI0)
172 {
173 u32Pclk = CLK_GetPCLK0Freq();
174 }
175 else
176 {
177 u32Pclk = CLK_GetPCLK1Freq();
178 }
179
180 u32ClkDiv = (uint32_t) ((((((u32Pclk/2ul)*10ul)/(u32BusClock))+5ul)/10ul)-1ul); /* Compute proper divider for USCI_SPI clock */
181
182 /* Set USCI_SPI bus clock */
183 uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk;
184 uspi->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos);
185
186 return ( u32Pclk / ((u32ClkDiv+1ul)<<1) );
187}
188
195{
196 uint32_t u32BusClk;
197 uint32_t u32ClkDiv;
198
199 u32ClkDiv = (uspi->BRGEN & USPI_BRGEN_CLKDIV_Msk) >> USPI_BRGEN_CLKDIV_Pos;
200
201 if(uspi == USPI0)
202 {
203 u32BusClk = (uint32_t)( CLK_GetPCLK0Freq() / ((u32ClkDiv+1ul)<<1) );
204 }
205 else
206 {
207 u32BusClk = (uint32_t)( CLK_GetPCLK1Freq() / ((u32ClkDiv+1ul)<<1) );
208 }
209
210 return u32BusClk;
211}
212
231void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask)
232{
233 /* Enable slave selection signal inactive interrupt flag */
235 {
237 }
238 /* Enable slave selection signal active interrupt flag */
240 {
242 }
243 /* Enable slave time-out interrupt flag */
245 {
247 }
248
249 /* Enable slave bit count error interrupt flag */
251 {
253 }
254 /* Enable TX under run interrupt flag */
256 {
258 }
259 /* Enable RX overrun interrupt flag */
260 if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK)
261 {
263 }
264 /* Enable TX start interrupt flag */
265 if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK)
266 {
268 }
269 /* Enable TX end interrupt flag */
271 {
273 }
274 /* Enable RX start interrupt flag */
275 if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK)
276 {
278 }
279 /* Enable RX end interrupt flag */
281 {
283 }
284}
285
304void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask)
305{
306 /* Disable slave selection signal inactive interrupt flag */
308 {
309 uspi->PROTIEN &= ~USPI_PROTIEN_SSINAIEN_Msk;
310 }
311 /* Disable slave selection signal active interrupt flag */
313 {
314 uspi->PROTIEN &= ~USPI_PROTIEN_SSACTIEN_Msk;
315 }
316 /* Disable slave time-out interrupt flag */
318 {
319 uspi->PROTIEN &= ~USPI_PROTIEN_SLVTOIEN_Msk;
320 }
321 /* Disable slave bit count error interrupt flag */
323 {
324 uspi->PROTIEN &= ~USPI_PROTIEN_SLVBEIEN_Msk;
325 }
326 /* Disable TX under run interrupt flag */
328 {
329 uspi->BUFCTL &= ~USPI_BUFCTL_TXUDRIEN_Msk;
330 }
331 /* Disable RX overrun interrupt flag */
332 if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK)
333 {
334 uspi->BUFCTL &= ~USPI_BUFCTL_RXOVIEN_Msk;
335 }
336 /* Disable TX start interrupt flag */
337 if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK)
338 {
339 uspi->INTEN &= ~USPI_INTEN_TXSTIEN_Msk;
340 }
341 /* Disable TX end interrupt flag */
343 {
344 uspi->INTEN &= ~USPI_INTEN_TXENDIEN_Msk;
345 }
346 /* Disable RX start interrupt flag */
347 if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK)
348 {
349 uspi->INTEN &= ~USPI_INTEN_RXSTIEN_Msk;
350 }
351 /* Disable RX end interrupt flag */
353 {
354 uspi->INTEN &= ~USPI_INTEN_RXENDIEN_Msk;
355 }
356}
357
376uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask)
377{
378 uint32_t u32TmpFlag;
379 uint32_t u32IntFlag = 0ul;
380
381 /* Check slave selection signal inactive interrupt flag */
382 u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SSINAIF_Msk;
383 if(((u32Mask & USPI_SSINACT_INT_MASK)==USPI_SSINACT_INT_MASK) && (u32TmpFlag==USPI_PROTSTS_SSINAIF_Msk) )
384 {
385 u32IntFlag |= USPI_SSINACT_INT_MASK;
386 }
387 /* Check slave selection signal active interrupt flag */
388
389 u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SSACTIF_Msk;
390 if(((u32Mask & USPI_SSACT_INT_MASK)==USPI_SSACT_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SSACTIF_Msk))
391 {
392 u32IntFlag |= USPI_SSACT_INT_MASK;
393 }
394
395 /* Check slave time-out interrupt flag */
396 u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SLVTOIF_Msk;
397 if(((u32Mask & USPI_SLVTO_INT_MASK)==USPI_SLVTO_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SLVTOIF_Msk))
398 {
399 u32IntFlag |= USPI_SLVTO_INT_MASK;
400 }
401
402 /* Check slave bit count error interrupt flag */
403 u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SLVBEIF_Msk;
404 if(((u32Mask & USPI_SLVBE_INT_MASK)==USPI_SLVBE_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_SLVBEIF_Msk))
405 {
406 u32IntFlag |= USPI_SLVBE_INT_MASK;
407 }
408
409 /* Check TX under run interrupt flag */
410 u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXUDRIF_Msk;
411 if(((u32Mask & USPI_TXUDR_INT_MASK)==USPI_TXUDR_INT_MASK) && (u32TmpFlag == USPI_BUFSTS_TXUDRIF_Msk))
412 {
413 u32IntFlag |= USPI_TXUDR_INT_MASK;
414 }
415
416 /* Check RX overrun interrupt flag */
417 u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXOVIF_Msk;
418 if(((u32Mask & USPI_RXOV_INT_MASK)==USPI_RXOV_INT_MASK) && (u32TmpFlag == USPI_BUFSTS_RXOVIF_Msk))
419 {
420 u32IntFlag |= USPI_RXOV_INT_MASK;
421 }
422
423 /* Check TX start interrupt flag */
424 u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_TXSTIF_Msk;
425 if(((u32Mask & USPI_TXST_INT_MASK)==USPI_TXST_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_TXSTIF_Msk))
426 {
427 u32IntFlag |= USPI_TXST_INT_MASK;
428 }
429
430 /* Check TX end interrupt flag */
431 u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_TXENDIF_Msk;
432 if(((u32Mask & USPI_TXEND_INT_MASK)==USPI_TXEND_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_TXENDIF_Msk))
433 {
434 u32IntFlag |= USPI_TXEND_INT_MASK;
435 }
436
437 /* Check RX start interrupt flag */
438 u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_RXSTIF_Msk;
439 if(((u32Mask & USPI_RXST_INT_MASK)==USPI_RXST_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_RXSTIF_Msk))
440 {
441 u32IntFlag |= USPI_RXST_INT_MASK;
442 }
443
444 /* Check RX end interrupt flag */
445 u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_RXENDIF_Msk;
446 if(((u32Mask & USPI_RXEND_INT_MASK)==USPI_RXEND_INT_MASK) && (u32TmpFlag == USPI_PROTSTS_RXENDIF_Msk))
447 {
448 u32IntFlag |= USPI_RXEND_INT_MASK;
449 }
450 return u32IntFlag;
451}
452
471void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask)
472{
473 /* Clear slave selection signal inactive interrupt flag */
475 {
477 }
478 /* Clear slave selection signal active interrupt flag */
480 {
482 }
483 /* Clear slave time-out interrupt flag */
485 {
487 }
488 /* Clear slave bit count error interrupt flag */
490 {
492 }
493 /* Clear TX under run interrupt flag */
495 {
497 }
498 /* Clear RX overrun interrupt flag */
500 {
502 }
503 /* Clear TX start interrupt flag */
505 {
507 }
508 /* Clear TX end interrupt flag */
510 {
512 }
513 /* Clear RX start interrupt flag */
515 {
517 }
518
519 /* Clear RX end interrupt flag */
521 {
523 }
524}
525
540uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask)
541{
542 uint32_t u32Flag = 0ul;
543 uint32_t u32TmpFlag;
544
545 /* Check busy status */
546 u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_BUSY_Msk;
547 if(((u32Mask & USPI_BUSY_MASK)==USPI_BUSY_MASK) && (u32TmpFlag & USPI_PROTSTS_BUSY_Msk))
548 {
549 u32Flag |= USPI_BUSY_MASK;
550 }
551
552 /* Check RX empty flag */
553 u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXEMPTY_Msk;
554 if(((u32Mask & USPI_RX_EMPTY_MASK)==USPI_RX_EMPTY_MASK) && (u32TmpFlag == USPI_BUFSTS_RXEMPTY_Msk))
555 {
556 u32Flag |= USPI_RX_EMPTY_MASK;
557 }
558
559 /* Check RX full flag */
560 u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_RXFULL_Msk;
561 if(((u32Mask & USPI_RX_FULL_MASK)==USPI_RX_FULL_MASK) && (u32TmpFlag == USPI_BUFSTS_RXFULL_Msk))
562 {
563 u32Flag |= USPI_RX_FULL_MASK;
564 }
565
566 /* Check TX empty flag */
567 u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXEMPTY_Msk;
568 if(((u32Mask & USPI_TX_EMPTY_MASK)==USPI_TX_EMPTY_MASK) && (u32TmpFlag == USPI_BUFSTS_TXEMPTY_Msk))
569 {
570 u32Flag |= USPI_TX_EMPTY_MASK;
571 }
572
573 /* Check TX full flag */
574 u32TmpFlag = uspi->BUFSTS & USPI_BUFSTS_TXFULL_Msk;
575 if(((u32Mask & USPI_TX_FULL_MASK)==USPI_TX_FULL_MASK) && (u32TmpFlag == USPI_BUFSTS_TXFULL_Msk))
576 {
577 u32Flag |= USPI_TX_FULL_MASK;
578 }
579
580 /* Check USCI_SPI_SS line status */
581 u32TmpFlag = uspi->PROTSTS & USPI_PROTSTS_SSLINE_Msk;
582 if(((u32Mask & USPI_SSLINE_STS_MASK)==USPI_SSLINE_STS_MASK) && (u32TmpFlag & USPI_PROTSTS_SSLINE_Msk))
583 {
584 u32Flag |= USPI_SSLINE_STS_MASK;
585 }
586 return u32Flag;
587}
588
595{
596 uspi->WKCTL |= USPI_WKCTL_WKEN_Msk;
597}
598
605{
606 uspi->WKCTL &= ~USPI_WKCTL_WKEN_Msk;
607}
608 /* end of group USCI_SPI_EXPORTED_FUNCTIONS */
610 /* end of group USCI_SPI_Driver */
612 /* end of group Standard_Driver */
614
615/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
NuMicro peripheral access layer header file.
uint32_t CLK_GetPCLK1Freq(void)
Get PCLK1 frequency.
Definition: clk.c:206
uint32_t CLK_GetPCLK0Freq(void)
Get PCLK0 frequency.
Definition: clk.c:166
#define USPI0
Definition: M480.h:451
#define USPI_PROTIEN_SSINAIEN_Msk
Definition: uspi_reg.h:1141
#define USPI_PROTCTL_SS_Msk
Definition: uspi_reg.h:1117
#define USPI_PROTSTS_TXENDIF_Msk
Definition: uspi_reg.h:1156
#define USPI_PROTSTS_SLVTOIF_Msk
Definition: uspi_reg.h:1165
#define USPI_INTEN_RXSTIEN_Msk
Definition: uspi_reg.h:991
#define USPI_BUFCTL_RXOVIEN_Msk
Definition: uspi_reg.h:1057
#define USPI_BUFSTS_TXEMPTY_Msk
Definition: uspi_reg.h:1078
#define USPI_CTLIN0_ININV_Msk
Definition: uspi_reg.h:1024
#define USPI_BRGEN_CLKDIV_Msk
Definition: uspi_reg.h:1012
#define USPI_BUFSTS_TXUDRIF_Msk
Definition: uspi_reg.h:1084
#define USPI_BUFCTL_TXUDRIEN_Msk
Definition: uspi_reg.h:1051
#define USPI_INTEN_RXENDIEN_Msk
Definition: uspi_reg.h:994
#define USPI_LINECTL_CTLOINV_Msk
Definition: uspi_reg.h:1036
#define USPI_BRGEN_CLKDIV_Pos
Definition: uspi_reg.h:1011
#define USPI_INTEN_TXENDIEN_Msk
Definition: uspi_reg.h:988
#define USPI_PROTCTL_SLAVE_Msk
Definition: uspi_reg.h:1111
#define USPI_LINECTL_DWIDTH_Pos
Definition: uspi_reg.h:1038
#define USPI_BUFSTS_RXEMPTY_Msk
Definition: uspi_reg.h:1069
#define USPI_BUFCTL_TXCLR_Msk
Definition: uspi_reg.h:1054
#define USPI_PROTSTS_TXSTIF_Msk
Definition: uspi_reg.h:1153
#define USPI_WKCTL_WKEN_Msk
Definition: uspi_reg.h:1099
#define USPI_PROTSTS_BUSY_Msk
Definition: uspi_reg.h:1180
#define USPI_BUFCTL_RXCLR_Msk
Definition: uspi_reg.h:1060
#define USPI_BUFSTS_TXFULL_Msk
Definition: uspi_reg.h:1081
#define USPI_INTEN_TXSTIEN_Msk
Definition: uspi_reg.h:985
#define USPI_PROTIEN_SLVBEIEN_Msk
Definition: uspi_reg.h:1150
#define USPI_PROTCTL_SCLKMODE_Msk
Definition: uspi_reg.h:1123
#define USPI_PROTSTS_SLVBEIF_Msk
Definition: uspi_reg.h:1168
#define USPI_PROTIEN_SSACTIEN_Msk
Definition: uspi_reg.h:1144
#define USPI_BUFSTS_RXFULL_Msk
Definition: uspi_reg.h:1072
#define USPI_PROTSTS_SSACTIF_Msk
Definition: uspi_reg.h:1174
#define USPI_PROTSTS_RXSTIF_Msk
Definition: uspi_reg.h:1159
#define USPI_CTL_FUNMODE_Pos
Definition: uspi_reg.h:981
#define USPI_PROTCTL_PROTEN_Msk
Definition: uspi_reg.h:1138
#define USPI_PROTSTS_RXENDIF_Msk
Definition: uspi_reg.h:1162
#define USPI_PROTCTL_AUTOSS_Msk
Definition: uspi_reg.h:1120
#define USPI_BUFSTS_RXOVIF_Msk
Definition: uspi_reg.h:1075
#define USPI_PROTIEN_SLVTOIEN_Msk
Definition: uspi_reg.h:1147
#define USPI_PROTSTS_SSINAIF_Msk
Definition: uspi_reg.h:1171
#define USPI_PROTSTS_SSLINE_Msk
Definition: uspi_reg.h:1177
#define USPI_RXST_INT_MASK
Definition: usci_spi.h:51
#define USPI_TXEND_INT_MASK
Definition: usci_spi.h:50
#define USPI_TX_EMPTY_MASK
Definition: usci_spi.h:58
#define USPI_MASTER
Definition: usci_spi.h:36
#define USPI_SLVTO_INT_MASK
Definition: usci_spi.h:45
#define USPI_TXST_INT_MASK
Definition: usci_spi.h:49
#define USPI_TX_FULL_MASK
Definition: usci_spi.h:59
#define USPI_RXEND_INT_MASK
Definition: usci_spi.h:52
#define USPI_SSINACT_INT_MASK
Definition: usci_spi.h:43
#define USPI_SSACT_INT_MASK
Definition: usci_spi.h:44
#define USPI_RXOV_INT_MASK
Definition: usci_spi.h:48
#define USPI_RX_EMPTY_MASK
Definition: usci_spi.h:56
#define USPI_BUSY_MASK
Definition: usci_spi.h:55
#define USPI_RX_FULL_MASK
Definition: usci_spi.h:57
#define USPI_SLVBE_INT_MASK
Definition: usci_spi.h:46
#define USPI_TXUDR_INT_MASK
Definition: usci_spi.h:47
#define USPI_SSLINE_STS_MASK
Definition: usci_spi.h:60
void USPI_Close(USPI_T *uspi)
Disable USCI_SPI function mode.
Definition: usci_spi.c:110
void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask)
Clear interrupt flag.
Definition: usci_spi.c:471
void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask)
Enable related interrupts specified by u32Mask parameter.
Definition: usci_spi.c:231
uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
This function make USCI_SPI module be ready to transfer. By default, the USCI_SPI transfer sequence i...
Definition: usci_spi.c:43
uint32_t USPI_GetBusClock(USPI_T *uspi)
Get the actual frequency of USCI_SPI bus clock. Only available in Master mode.
Definition: usci_spi.c:194
void USPI_DisableAutoSS(USPI_T *uspi)
Disable the automatic slave select function.
Definition: usci_spi.c:140
void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
Enable the automatic slave select function. Only available in Master mode.
Definition: usci_spi.c:154
uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock)
Set the USCI_SPI bus clock. Only available in Master mode.
Definition: usci_spi.c:166
void USPI_EnableWakeup(USPI_T *uspi)
Enable USCI_SPI Wake-up Function.
Definition: usci_spi.c:594
void USPI_DisableWakeup(USPI_T *uspi)
Disable USCI_SPI Wake-up Function.
Definition: usci_spi.c:604
void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask)
Disable related interrupts specified by u32Mask parameter.
Definition: usci_spi.c:304
void USPI_ClearTxBuf(USPI_T *uspi)
Clear Tx buffer.
Definition: usci_spi.c:130
uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask)
Get interrupt flag.
Definition: usci_spi.c:376
uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask)
Get USCI_SPI status.
Definition: usci_spi.c:540
void USPI_ClearRxBuf(USPI_T *uspi)
Clear Rx buffer.
Definition: usci_spi.c:120
__IO uint32_t CTLIN0
Definition: uspi_reg.h:954
__IO uint32_t PROTSTS
Definition: uspi_reg.h:972
__IO uint32_t WKCTL
Definition: uspi_reg.h:968
__IO uint32_t INTEN
Definition: uspi_reg.h:945
__IO uint32_t BUFCTL
Definition: uspi_reg.h:962
__IO uint32_t PROTIEN
Definition: uspi_reg.h:971
__IO uint32_t LINECTL
Definition: uspi_reg.h:959
__IO uint32_t BRGEN
Definition: uspi_reg.h:946
__IO uint32_t PROTCTL
Definition: uspi_reg.h:970
__IO uint32_t CTL
Definition: uspi_reg.h:944
__IO uint32_t BUFSTS
Definition: uspi_reg.h:963