34#define SPIM_DBGMSG printf
36#define SPIM_DBGMSG(...) do { } while (0)
39static volatile uint8_t g_Supported_List[] =
48static void N_delay(
int n);
49static void SwitchNBitOutput(uint32_t u32NBit);
50static void SwitchNBitInput(uint32_t u32NBit);
51static void spim_write(uint8_t pu8TxBuf[], uint32_t u32NTx);
52static void spim_read(uint8_t pu8RxBuf[], uint32_t u32NRx);
53static void SPIM_WriteStatusRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit);
54static void SPIM_ReadStatusRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
55static void SPIM_ReadStatusRegister2(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
56static void SPIM_WriteStatusRegister2(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit);
57static void SPIM_ReadStatusRegister3(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
58static void SPIM_ReadSecurityRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit);
59static int spim_is_write_done(uint32_t u32NBit);
60static int spim_wait_write_done(uint32_t u32NBit);
61static void spim_set_write_enable(
int isEn, uint32_t u32NBit);
62static void spim_enable_spansion_quad_mode(
int isEn);
65static void SPIM_WriteInPageDataByIo(uint32_t u32Addr,
int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd,
66 uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat,
int isSync);
67static void SPIM_WriteInPageDataByPageWrite(uint32_t u32Addr,
int is4ByteAddr, uint32_t u32NTx,
68 uint8_t pu8TxBuf[], uint32_t wrCmd,
int isSync);
71static void N_delay(
int n)
79static void SwitchNBitOutput(uint32_t u32NBit)
100static void SwitchNBitInput(uint32_t u32NBit)
128static void spim_write(uint8_t pu8TxBuf[], uint32_t u32NTx)
130 uint32_t buf_idx = 0UL;
134 uint32_t dataNum = 0UL, dataNum2;
140 else if (u32NTx >= 12UL)
144 else if (u32NTx >= 8UL)
148 else if (u32NTx >= 4UL)
158 memcpy(&tmp, &pu8TxBuf[buf_idx], 4U);
164 SPIM->TX[dataNum2] = tmp;
176 if (u32NTx && (u32NTx < 4UL))
181 memcpy(&tmp, &pu8TxBuf[buf_idx], u32NTx);
201static void spim_read(uint8_t pu8RxBuf[], uint32_t u32NRx)
203 uint32_t buf_idx = 0UL;
207 uint32_t dataNum = 0UL;
213 else if (u32NRx >= 12UL)
217 else if (u32NRx >= 8UL)
221 else if (u32NRx >= 4UL)
239 tmp =
SPIM->RX[dataNum-1UL];
240 memcpy(&pu8RxBuf[buf_idx], &tmp, 4U);
246 if (u32NRx && (u32NRx < 4UL))
257 memcpy(&pu8RxBuf[buf_idx], &tmp, u32NRx);
271static void SPIM_ReadStatusRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit)
273 uint8_t cmdBuf[] = {OPCODE_RDSR};
276 SwitchNBitOutput(u32NBit);
277 spim_write(cmdBuf,
sizeof (cmdBuf));
278 SwitchNBitInput(u32NBit);
279 spim_read(dataBuf, u32NRx);
290static void SPIM_WriteStatusRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit)
292 uint8_t cmdBuf[] = {OPCODE_WRSR, 0x00U};
294 cmdBuf[1] = dataBuf[0];
296 SwitchNBitOutput(u32NBit);
297 spim_write(cmdBuf,
sizeof (cmdBuf));
308static void SPIM_ReadStatusRegister2(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit)
310 uint8_t cmdBuf[] = {OPCODE_RDSR2};
313 SwitchNBitOutput(u32NBit);
314 spim_write(cmdBuf,
sizeof (cmdBuf));
315 SwitchNBitInput(u32NBit);
316 spim_read(dataBuf, u32NRx);
328static void SPIM_WriteStatusRegister2(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit)
330 uint8_t cmdBuf[3] = {OPCODE_WRSR, 0U, 0U};
332 cmdBuf[1] = dataBuf[0];
333 cmdBuf[2] = dataBuf[1];
336 SwitchNBitOutput(u32NBit);
337 spim_write(cmdBuf,
sizeof (cmdBuf));
349static void SPIM_WriteStatusRegister3(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit)
351 uint8_t cmdBuf[] = {OPCODE_WRSR3, 0x00U};
352 cmdBuf[1] = dataBuf[0];
355 SwitchNBitOutput(u32NBit);
356 spim_write(cmdBuf,
sizeof (cmdBuf));
368static void SPIM_ReadStatusRegister3(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit)
370 uint8_t cmdBuf[] = {OPCODE_RDSR3};
373 SwitchNBitOutput(u32NBit);
374 spim_write(cmdBuf,
sizeof (cmdBuf));
375 SwitchNBitInput(u32NBit);
376 spim_read(dataBuf, u32NRx);
388static void SPIM_WriteSecurityRegister(uint8_t dataBuf[], uint32_t u32NTx, uint32_t u32NBit)
390 uint8_t cmdBuf[] = {OPCODE_WRSCUR, 0x00U};
391 cmdBuf[1] = dataBuf[0];
394 SwitchNBitOutput(u32NBit);
395 spim_write(cmdBuf,
sizeof (cmdBuf));
407static void SPIM_ReadSecurityRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32_t u32NBit)
409 uint8_t cmdBuf[] = {OPCODE_RDSCUR};
412 SwitchNBitOutput(u32NBit);
413 spim_write(cmdBuf,
sizeof (cmdBuf));
414 SwitchNBitInput(u32NBit);
415 spim_read(dataBuf, u32NRx);
423static int spim_is_write_done(uint32_t u32NBit)
426 SPIM_ReadStatusRegister(status,
sizeof (status), u32NBit);
427 return ! (status[0] & SR_WIP);
435static int spim_wait_write_done(uint32_t u32NBit)
442 if (spim_is_write_done(u32NBit))
450 SPIM_DBGMSG(
"spim_wait_write_done time-out!!\n");
461static void spim_set_write_enable(
int isEn, uint32_t u32NBit)
463 uint8_t cmdBuf[] = {0U};
464 cmdBuf[0] = isEn ? OPCODE_WREN : OPCODE_WRDI;
467 SwitchNBitOutput(u32NBit);
468 spim_write(cmdBuf,
sizeof (cmdBuf));
505 cmdBuf[0] = OPCODE_RSTEN;
508 spim_write(cmdBuf,
sizeof (cmdBuf));
512 cmdBuf[0] = OPCODE_RST;
515 spim_write(cmdBuf,
sizeof (cmdBuf));
519 cmdBuf[0] = OPCODE_RSTEN;
522 spim_write(cmdBuf,
sizeof (cmdBuf));
526 cmdBuf[0] = OPCODE_RST;
529 spim_write(cmdBuf,
sizeof (cmdBuf));
534 uint8_t dataBuf[] = {0x00U};
536 spim_set_write_enable(1, 1UL);
537 SPIM_WriteStatusRegister(dataBuf,
sizeof (dataBuf), 1U);
538 spim_wait_write_done(1UL);
545 for (i = 0UL; i <
sizeof(g_Supported_List)/
sizeof(g_Supported_List[0]); i++)
547 if (idBuf[0] == g_Supported_List[i])
554 SPIM_DBGMSG(
"Flash initialize failed!! 0x%x\n", idBuf[0]);
568 uint8_t cmdBuf[] = { OPCODE_RDID };
571 SwitchNBitOutput(u32NBit);
572 spim_write(cmdBuf,
sizeof (cmdBuf));
573 SwitchNBitInput(u32NBit);
574 spim_read(idBuf, u32NRx);
580static void spim_enable_spansion_quad_mode(
int isEn)
583 uint8_t dataBuf[1], status1;
588 SwitchNBitOutput(1UL);
589 spim_write(cmdBuf,
sizeof (cmdBuf));
590 SwitchNBitInput(1UL);
591 spim_read(dataBuf,
sizeof (dataBuf));
595 status1 = dataBuf[0];
600 SwitchNBitOutput(1UL);
601 spim_write(cmdBuf,
sizeof (cmdBuf));
602 SwitchNBitInput(1UL);
603 spim_read(dataBuf,
sizeof (dataBuf));
607 spim_set_write_enable(1, 1UL);
614 cmdBuf[2] = dataBuf[0] | 0x2U;
618 cmdBuf[2] = dataBuf[0] & ~0x2U;
622 SwitchNBitOutput(1UL);
623 spim_write(cmdBuf, 3UL);
626 spim_set_write_enable(0, 1UL);
632 SwitchNBitOutput(1UL);
633 spim_write(cmdBuf,
sizeof (cmdBuf));
634 SwitchNBitInput(1UL);
635 spim_read(dataBuf,
sizeof (dataBuf));
657 SPIM_DBGMSG(
"SPIM_SetQuadEnable - Flash ID is 0x%x\n", idBuf[0]);
662 SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit);
663 SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit);
664 SPIM_DBGMSG(
"Status Register: 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]);
667 dataBuf[1] |= SR2_QE;
671 dataBuf[1] &= ~SR2_QE;
674 spim_set_write_enable(1, u32NBit);
675 SPIM_WriteStatusRegister2(dataBuf,
sizeof (dataBuf), u32NBit);
676 spim_wait_write_done(u32NBit);
678 SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit);
679 SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit);
680 SPIM_DBGMSG(
"Status Register: 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]);
686 spim_set_write_enable(1, u32NBit);
687 dataBuf[0] = isEn ? SR_QE : 0U;
688 SPIM_WriteStatusRegister(dataBuf,
sizeof (dataBuf), u32NBit);
689 spim_wait_write_done(u32NBit);
693 spim_enable_spansion_quad_mode(isEn);
711 SPIM_ReadStatusRegister(status,
sizeof (status), 1UL);
712 SPIM_DBGMSG(
"Status: 0x%x\n", status[0]);
716 cmdBuf[0] = OPCODE_ENQPI;
719 SwitchNBitOutput(1UL);
720 spim_write(cmdBuf,
sizeof (cmdBuf));
725 cmdBuf[0] = OPCODE_EXQPI;
728 SwitchNBitOutput(4UL);
729 spim_write(cmdBuf,
sizeof (cmdBuf));
733 SPIM_ReadStatusRegister(status,
sizeof (status), 1UL);
734 SPIM_DBGMSG(
"Status: 0x%x\n", status[0]);
743 cmdBuf[0] = OPCODE_BRRD;
745 SwitchNBitOutput(u32NBit);
746 spim_write(cmdBuf, 1UL);
747 SwitchNBitInput(1UL);
748 spim_read(dataBuf, 1UL);
751 SPIM_DBGMSG(
"Bank Address register= 0x%x\n", dataBuf[0]);
753 cmdBuf[0] = OPCODE_BRWR;
757 cmdBuf[1] = dataBuf[0] | 0x80U;
761 cmdBuf[1] = dataBuf[0] & ~0x80U;
765 SwitchNBitOutput(1UL);
766 spim_write(cmdBuf, 2UL);
792 isSupt = (idBuf[2] < 0x19U) ? 0L : 1L;
796 isSupt = (idBuf[2] < 0x49U) ? 0L : 1L;
805 if (idBuf[0] == MFGID_WINBOND)
808 SPIM_ReadStatusRegister3(dataBuf,
sizeof (dataBuf), u32NBit);
809 isEn = !! (dataBuf[0] & SR3_ADR);
811 else if ((idBuf[0] == MFGID_MXIC) || (idBuf[0] ==MFGID_EON))
814 SPIM_ReadSecurityRegister(dataBuf,
sizeof (dataBuf), u32NBit);
815 isEn = !! (dataBuf[0] & SCUR_4BYTE);
834 int isSupt = 0L, ret = -1;
847 isSupt = (idBuf[2] < 0x19U) ? 0L : 1L;
851 isSupt = (idBuf[2] < 0x49U) ? 0L : 1L;
864 if ((isSupt) && (idBuf[0] != MFGID_SPANSION))
866 cmdBuf[0] = isEn ? OPCODE_EN4B : OPCODE_EX4B;
869 SwitchNBitOutput(u32NBit);
870 spim_write(cmdBuf,
sizeof (cmdBuf));
878 if (idBuf[0] != MFGID_MXIC)
909 if ((idBuf[0] != MFGID_WINBOND) || (idBuf[1] != 0x40) || (idBuf[2] != 0x16))
911 SPIM_DBGMSG(
"SPIM_WinbondUnlock - Not W25Q32, do nothing.\n");
915 SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit);
916 SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit);
917 SPIM_DBGMSG(
"Status Register: 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]);
920 spim_set_write_enable(1, u32NBit);
921 SPIM_WriteStatusRegister2(dataBuf,
sizeof (dataBuf), u32NBit);
922 spim_wait_write_done(u32NBit);
924 SPIM_ReadStatusRegister(&dataBuf[0], 1UL, u32NBit);
925 SPIM_ReadStatusRegister2(&dataBuf[1], 1UL, u32NBit);
926 SPIM_DBGMSG(
"Status Register (after unlock): 0x%x - 0x%x\n", dataBuf[0], dataBuf[1]);
937 uint8_t cmdBuf[] = { OPCODE_CHIP_ERASE };
939 spim_set_write_enable(1, u32NBit);
942 SwitchNBitOutput(u32NBit);
943 spim_write(cmdBuf,
sizeof (cmdBuf));
948 spim_wait_write_done(u32NBit);
962void SPIM_EraseBlock(uint32_t u32Addr,
int is4ByteAddr, uint8_t u8ErsCmd, uint32_t u32NBit,
int isSync)
965 uint32_t buf_idx = 0UL;
967 spim_set_write_enable(1, u32NBit);
969 cmdBuf[buf_idx++] = u8ErsCmd;
973 cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 24);
974 cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16);
975 cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8);
976 cmdBuf[buf_idx++] = (uint8_t) (u32Addr & 0xFFUL);
980 cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16);
981 cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8);
982 cmdBuf[buf_idx++] = (uint8_t) (u32Addr & 0xFFUL);
986 SwitchNBitOutput(u32NBit);
987 spim_write(cmdBuf, buf_idx);
992 spim_wait_write_done(u32NBit);
1012static void SPIM_WriteInPageDataByIo(uint32_t u32Addr,
int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd,
1013 uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat,
int isSync)
1018 spim_set_write_enable(1, u32NBitCmd);
1022 SwitchNBitOutput(u32NBitCmd);
1024 spim_write(cmdBuf, 1UL);
1029 cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 24);
1030 cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16);
1031 cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8);
1032 cmdBuf[buf_idx++] = (uint8_t) u32Addr;
1036 cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16);
1037 cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8);
1038 cmdBuf[buf_idx++] = (uint8_t) u32Addr;
1041 SwitchNBitOutput(u32NBitAddr);
1042 spim_write(cmdBuf, buf_idx);
1044 SwitchNBitOutput(u32NBitDat);
1045 spim_write(pu8TxBuf, u32NTx);
1051 spim_wait_write_done(u32NBitCmd);
1065static void SPIM_WriteInPageDataByPageWrite(uint32_t u32Addr,
int is4ByteAddr, uint32_t u32NTx,
1066 uint8_t pu8TxBuf[], uint32_t wrCmd,
int isSync)
1083 SPIM->SRAMADDR = (uint32_t) pu8TxBuf;
1084 SPIM->DMACNT = u32NTx;
1085 SPIM->FADDR = u32Addr;
1113void SPIM_IO_Write(uint32_t u32Addr,
int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd,
1114 uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat)
1116 uint32_t pageOffset, toWr;
1117 uint32_t buf_idx = 0UL;
1119 pageOffset = u32Addr % 256UL;
1121 if ((pageOffset + u32NTx) <= 256UL)
1123 SPIM_WriteInPageDataByIo(u32Addr, is4ByteAddr, u32NTx, &pu8TxBuf[buf_idx],
1124 wrCmd, u32NBitCmd, u32NBitAddr, u32NBitDat, 1);
1128 toWr = 256UL - pageOffset;
1130 SPIM_WriteInPageDataByIo(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx],
1131 wrCmd, u32NBitCmd, u32NBitAddr, u32NBitDat, 1);
1144 SPIM_WriteInPageDataByIo(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx],
1145 wrCmd, u32NBitCmd, u32NBitAddr, u32NBitDat, 1);
1166void SPIM_IO_Read(uint32_t u32Addr,
int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint8_t rdCmd,
1167 uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat,
int u32NDummy)
1175 SwitchNBitOutput(u32NBitCmd);
1176 spim_write(cmdBuf, 1UL);
1181 cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 24);
1182 cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16);
1183 cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8);
1184 cmdBuf[buf_idx++] = (uint8_t) u32Addr;
1188 cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 16);
1189 cmdBuf[buf_idx++] = (uint8_t) (u32Addr >> 8);
1190 cmdBuf[buf_idx++] = (uint8_t) u32Addr;
1192 SwitchNBitOutput(u32NBitAddr);
1193 spim_write(cmdBuf, buf_idx);
1196 while (u32NDummy --)
1198 cmdBuf[buf_idx++] = 0x00U;
1202 spim_write(cmdBuf, buf_idx);
1204 SwitchNBitInput(u32NBitDat);
1205 spim_read(pu8RxBuf, u32NRx);
1219void SPIM_DMA_Write(uint32_t u32Addr,
int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint32_t wrCmd)
1221 uint32_t pageOffset, toWr;
1222 uint32_t buf_idx = 0UL;
1224 pageOffset = u32Addr % 256UL;
1226 if ((pageOffset + u32NTx) <= 256UL)
1229 SPIM_WriteInPageDataByPageWrite(u32Addr, is4ByteAddr, u32NTx, pu8TxBuf, wrCmd, 1);
1233 toWr = 256UL - pageOffset;
1235 SPIM_WriteInPageDataByPageWrite(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx], wrCmd, 1);
1249 SPIM_WriteInPageDataByPageWrite(u32Addr, is4ByteAddr, toWr, &pu8TxBuf[buf_idx], wrCmd, 1);
1268void SPIM_DMA_Read(uint32_t u32Addr,
int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[],
1269 uint32_t u32RdCmd,
int isSync)
1275 SPIM->SRAMADDR = (uint32_t) pu8RxBuf;
1276 SPIM->DMACNT = u32NRx;
1277 SPIM->FADDR = u32Addr;
NuMicro peripheral access layer header file.
#define SPIM_CTL0_OPMODE_PAGEWRITE
#define CMD_QUAD_PAGE_PROGRAM_EON
#define CMD_QUAD_PAGE_PROGRAM_WINBOND
#define CMD_QUAD_PAGE_PROGRAM_MXIC
#define SPIM_CTL0_OPMODE_IO
#define SPIM_CTL0_OPMODE_DIRECTMAP
#define SPIM_CTL0_OPMODE_PAGEREAD
void SPIM_EnterDirectMapMode(int is4ByteAddr, uint32_t u32RdCmd, uint32_t u32IdleIntvl)
Enter Direct Map mode.
#define SPIM_ENABLE_QUAD_OUTPUT_MODE()
void SPIM_SetQuadEnable(int isEn, uint32_t u32NBit)
Set Quad Enable/disable.
#define SPIM_ENABLE_SING_OUTPUT_MODE()
#define SPIM_SET_DATA_NUM(x)
#define SPIM_SET_OPMODE(x)
#define SPIM_SET_DATA_WIDTH(x)
#define SPIM_SET_SS_EN(x)
void SPIM_IO_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint8_t wrCmd, uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat)
Write data to SPI Flash by sending commands manually (I/O mode).
void SPIM_DMA_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint32_t u32RdCmd, int isSync)
Read data from SPI Flash by Page Read mode.
#define SPIM_GET_CLOCK_DIVIDER()
int SPIM_Enable_4Bytes_Mode(int isEn, uint32_t u32NBit)
Enter/Exit 4-byte address mode.
#define SPIM_SET_SPIM_MODE(x)
#define SPIM_ENABLE_DUAL_INPUT_MODE()
#define SPIM_ENABLE_QUAD_INPUT_MODE()
void SPIM_WinbondUnlock(uint32_t u32NBit)
uint32_t SPIM_GetSClkFreq(void)
Get SPIM serial clock.
void SPIM_EraseBlock(uint32_t u32Addr, int is4ByteAddr, uint8_t u8ErsCmd, uint32_t u32NBit, int isSync)
Erase one block.
#define SPIM_SET_SS_ACTLVL(x)
static void SPIM_SPANSION_4Bytes_Enable(int isEn, uint32_t u32NBit)
void SPIM_ExitDirectMapMode(void)
Exit Direct Map mode.
#define SPIM_ENABLE_SING_INPUT_MODE()
#define SPIM_SET_IDL_INTVL(x)
void SPIM_ReadJedecId(uint8_t idBuf[], uint32_t u32NRx, uint32_t u32NBit)
Issue JEDEC ID command.
#define SPIM_ENABLE_DUAL_OUTPUT_MODE()
#define SPIM_SET_4BYTE_ADDR_EN(x)
void SPIM_ChipErase(uint32_t u32NBit, int isSync)
Erase whole chip.
static void spim_eon_set_qpi_mode(int isEn)
Enter/exit QPI mode.
int SPIM_Is4ByteModeEnable(uint32_t u32NBit)
int SPIM_InitFlash(int clrWP)
Initialize SPIM flash.
void SPIM_DMA_Write(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NTx, uint8_t pu8TxBuf[], uint32_t wrCmd)
Write data to SPI Flash by Page Write mode.
void SPIM_IO_Read(uint32_t u32Addr, int is4ByteAddr, uint32_t u32NRx, uint8_t pu8RxBuf[], uint8_t rdCmd, uint32_t u32NBitCmd, uint32_t u32NBitAddr, uint32_t u32NBitDat, int u32NDummy)
Read data from SPI Flash by sending commands manually (I/O mode).