M480 BSP V3.05.006
The Board Support Package for M480 Series
system_M480.c
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1/**************************************************************************/
10#include "NuMicro.h"
11
12
13/*----------------------------------------------------------------------------
14 DEFINES
15 *----------------------------------------------------------------------------*/
16
17
18/*----------------------------------------------------------------------------
19 Clock Variable definitions
20 *----------------------------------------------------------------------------*/
22uint32_t CyclesPerUs = (__HSI / 1000000UL); /* Cycles per micro second */
23uint32_t PllClock = __HSI;
24uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, 0UL, __LIRC, 0UL, 0UL, 0UL, __HIRC};
25
26/*----------------------------------------------------------------------------
27 Clock functions
28 *----------------------------------------------------------------------------*/
29void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
30{
31 uint32_t u32Freq, u32ClkSrc;
32 uint32_t u32HclkDiv;
33
34 /* Update PLL Clock */
36
37 u32ClkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk;
38
39 if(u32ClkSrc == CLK_CLKSEL0_HCLKSEL_PLL)
40 {
41 /* Use PLL clock */
42 u32Freq = PllClock;
43 }
44 else
45 {
46 /* Use the clock sources directly */
47 u32Freq = gau32ClkSrcTbl[u32ClkSrc];
48 }
49
50 u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1UL;
51
52 /* Update System Core Clock */
53 SystemCoreClock = u32Freq / u32HclkDiv;
54
55
56 //if(SystemCoreClock == 0)
57 // __BKPT(0);
58
59 CyclesPerUs = (SystemCoreClock + 500000UL) / 1000000UL;
60}
61
70static __INLINE void HXTInit(void)
71{
73
74}
75
82void SystemInit (void)
83{
84 /* Add your system initialize code here.
85 Do not use global variables because this function is called before
86 reaching pre-main. RW section maybe overwritten afterwards. */
87
88
89 /* FPU settings ------------------------------------------------------------*/
90#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
91 SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
92 (3UL << 11*2) ); /* set CP11 Full Access */
93#endif
94
95 /* Set access cycle for CPU @ 192MHz */
96 FMC->CYCCTL = (FMC->CYCCTL & ~FMC_CYCCTL_CYCLE_Msk) | (8 << FMC_CYCCTL_CYCLE_Pos);
97 /* Configure power down bias, must set 1 before entering power down mode.
98 So set it at the very beginning */
100 /* Hand over the control of PF.4~11 I/O function from RTC module to GPIO module */
101 CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk;
106 CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk;
107 HXTInit();
108
109}
110/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
NuMicro peripheral access layer header file.
#define CLK_CLKSEL0_HCLKSEL_PLL
Definition: clk.h:48
uint32_t CLK_GetPLLClockFreq(void)
Get PLL clock frequency.
Definition: clk.c:1201
#define CLK
Definition: M480.h:368
#define RTC
Definition: M480.h:400
#define FMC
Definition: M480.h:391
#define PF
Definition: M480.h:375
#define GPIO_MODE_MODE2_Msk
Definition: gpio_reg.h:588
#define FMC_CYCCTL_CYCLE_Pos
Definition: fmc_reg.h:1078
#define CLK_CLKDIV0_HCLKDIV_Msk
Definition: clk_reg.h:2616
#define CLK_CLKSEL0_HCLKSEL_Msk
Definition: clk_reg.h:2508
#define RTC_GPIOCTL1_CTLSEL6_Msk
Definition: rtc_reg.h:2042
#define RTC_GPIOCTL1_CTLSEL5_Msk
Definition: rtc_reg.h:2030
#define CLK_APBCLK0_RTCCKEN_Msk
Definition: clk_reg.h:2361
#define RTC_GPIOCTL1_CTLSEL4_Msk
Definition: rtc_reg.h:2018
#define RTC_GPIOCTL0_CTLSEL3_Msk
Definition: rtc_reg.h:2006
#define GPIO_MODE_MODE3_Msk
Definition: gpio_reg.h:591
#define RTC_GPIOCTL1_CTLSEL7_Msk
Definition: rtc_reg.h:2054
#define RTC_GPIOCTL0_CTLSEL2_Msk
Definition: rtc_reg.h:1994
#define CLK_LDOCTL_PDBIASEN_Msk
Definition: clk_reg.h:2856
#define RTC_GPIOCTL0_CTLSEL0_Msk
Definition: rtc_reg.h:1970
#define RTC_GPIOCTL0_CTLSEL1_Msk
Definition: rtc_reg.h:1982
static __INLINE void HXTInit(void)
Set PF.2 and PF.3 to input mode.
Definition: system_M480.c:70
uint32_t gau32ClkSrcTbl[]
Definition: system_M480.c:24
uint32_t CyclesPerUs
Definition: system_M480.c:22
void SystemInit(void)
Initialize the System.
Definition: system_M480.c:82
uint32_t PllClock
Definition: system_M480.c:23
uint32_t SystemCoreClock
Definition: system_M480.c:21
void SystemCoreClockUpdate(void)
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
Definition: system_M480.c:29
#define __HIRC
Definition: system_M480.h:36
#define __SYSTEM_CLOCK
Definition: system_M480.h:41
#define __HXT
Definition: system_M480.h:29
#define __LIRC
Definition: system_M480.h:37
#define __LXT
Definition: system_M480.h:33
#define __HSI
Definition: system_M480.h:25